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1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (C) 2015 Intel Corporation. All rights reserved.
3 : : * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.
4 : : * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 : : */
6 : :
7 : : #include "spdk/stdinc.h"
8 : :
9 : : #include "nvme_internal.h"
10 : : #include "nvme_io_msg.h"
11 : :
12 : : #include "spdk/env.h"
13 : : #include "spdk/string.h"
14 : : #include "spdk/endian.h"
15 : :
16 : : struct nvme_active_ns_ctx;
17 : :
18 : : static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
19 : : struct nvme_async_event_request *aer);
20 : : static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx);
21 : : static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns);
22 : : static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns);
23 : : static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns);
24 : : static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr);
25 : : static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
26 : : uint64_t timeout_in_ms);
27 : :
28 : : static int
29 : 2888755 : nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2)
30 : : {
31 [ + + ]: 2888755 : if (ns1->id < ns2->id) {
32 : 989852 : return -1;
33 [ + + ]: 1898903 : } else if (ns1->id > ns2->id) {
34 : 1657902 : return 1;
35 : : } else {
36 : 241001 : return 0;
37 : : }
38 : : }
39 : :
40 [ + + + + : 3691674 : RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp);
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41 : :
42 : : #define CTRLR_STRING(ctrlr) \
43 : : ((ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP || ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA) ? \
44 : : ctrlr->trid.subnqn : ctrlr->trid.traddr)
45 : :
46 : : #define NVME_CTRLR_ERRLOG(ctrlr, format, ...) \
47 : : SPDK_ERRLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
48 : :
49 : : #define NVME_CTRLR_WARNLOG(ctrlr, format, ...) \
50 : : SPDK_WARNLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
51 : :
52 : : #define NVME_CTRLR_NOTICELOG(ctrlr, format, ...) \
53 : : SPDK_NOTICELOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
54 : :
55 : : #define NVME_CTRLR_INFOLOG(ctrlr, format, ...) \
56 : : SPDK_INFOLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
57 : :
58 : : #ifdef DEBUG
59 : : #define NVME_CTRLR_DEBUGLOG(ctrlr, format, ...) \
60 : : SPDK_DEBUGLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
61 : : #else
62 : : #define NVME_CTRLR_DEBUGLOG(ctrlr, ...) do { } while (0)
63 : : #endif
64 : :
65 : : #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \
66 : : nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \
67 : : offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg)
68 : :
69 : : #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \
70 : : nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \
71 : : offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg)
72 : :
73 : : #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \
74 : : nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg)
75 : :
76 : : #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \
77 : : nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg)
78 : :
79 : : #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \
80 : : nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg)
81 : :
82 : : #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \
83 : : nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg)
84 : :
85 : : #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \
86 : : nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg)
87 : :
88 : : static int
89 : 0 : nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
90 : : {
91 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
92 : : &cc->raw);
93 : : }
94 : :
95 : : static int
96 : 34492 : nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
97 : : {
98 : 34492 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
99 : : &csts->raw);
100 : : }
101 : :
102 : : int
103 : 757 : nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
104 : : {
105 : 757 : return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
106 : : &cap->raw);
107 : : }
108 : :
109 : : int
110 : 6 : nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
111 : : {
112 : 6 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
113 : : &vs->raw);
114 : : }
115 : :
116 : : int
117 : 8 : nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz)
118 : : {
119 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
120 : : &cmbsz->raw);
121 : : }
122 : :
123 : : int
124 : 8 : nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap)
125 : : {
126 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
127 : : &pmrcap->raw);
128 : : }
129 : :
130 : : int
131 : 0 : nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo)
132 : : {
133 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw),
134 : : &bpinfo->raw);
135 : : }
136 : :
137 : : int
138 : 0 : nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel)
139 : : {
140 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw),
141 : : bprsel->raw);
142 : : }
143 : :
144 : : int
145 : 0 : nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value)
146 : : {
147 : 0 : return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl),
148 : : bpmbl_value);
149 : : }
150 : :
151 : : static int
152 : 0 : nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
153 : : {
154 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr),
155 : : nssr_value);
156 : : }
157 : :
158 : : bool
159 : 4912 : nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr)
160 : : {
161 [ + + ]: 6918 : return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS &&
162 [ + + ]: 2006 : ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS;
163 : : }
164 : :
165 : : /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please
166 : : * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c
167 : : */
168 : : void
169 : 4169 : spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size)
170 : : {
171 : 903 : char host_id_str[SPDK_UUID_STRING_LEN];
172 : :
173 [ - + ]: 4169 : assert(opts);
174 : :
175 : 4169 : opts->opts_size = opts_size;
176 : :
177 : : #define FIELD_OK(field) \
178 : : offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size
179 : :
180 : : #define SET_FIELD(field, value) \
181 : : if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \
182 : : opts->field = value; \
183 : : } \
184 : :
185 [ + - ]: 4169 : SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES);
186 [ + - ]: 4169 : SET_FIELD(use_cmb_sqs, false);
187 [ + - ]: 4169 : SET_FIELD(no_shn_notification, false);
188 [ + + ]: 4169 : SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR);
189 [ + + ]: 4169 : SET_FIELD(arbitration_burst, 0);
190 [ + + ]: 4169 : SET_FIELD(low_priority_weight, 0);
191 [ + + ]: 4169 : SET_FIELD(medium_priority_weight, 0);
192 [ + + ]: 4169 : SET_FIELD(high_priority_weight, 0);
193 [ + + ]: 4169 : SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS);
194 [ + + ]: 4169 : SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT);
195 [ + + ]: 4169 : SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE);
196 : :
197 [ + - ]: 4169 : if (nvme_driver_init() == 0) {
198 [ + + ]: 4169 : if (FIELD_OK(hostnqn)) {
199 : 4163 : spdk_uuid_fmt_lower(host_id_str, sizeof(host_id_str),
200 : 4163 : &g_spdk_nvme_driver->default_extended_host_id);
201 [ - + ]: 4163 : snprintf(opts->hostnqn, sizeof(opts->hostnqn),
202 : : "nqn.2014-08.org.nvmexpress:uuid:%s", host_id_str);
203 : : }
204 : :
205 [ + + ]: 4169 : if (FIELD_OK(extended_host_id)) {
206 : 4163 : memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
207 : : sizeof(opts->extended_host_id));
208 : : }
209 : :
210 : : }
211 : :
212 [ + + ]: 4169 : SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
213 : :
214 [ + + ]: 4169 : if (FIELD_OK(src_addr)) {
215 [ - + ]: 4163 : memset(opts->src_addr, 0, sizeof(opts->src_addr));
216 : : }
217 : :
218 [ + + ]: 4169 : if (FIELD_OK(src_svcid)) {
219 [ - + ]: 4163 : memset(opts->src_svcid, 0, sizeof(opts->src_svcid));
220 : : }
221 : :
222 [ + + ]: 4169 : if (FIELD_OK(host_id)) {
223 [ - + ]: 4163 : memset(opts->host_id, 0, sizeof(opts->host_id));
224 : : }
225 : :
226 [ + + ]: 4169 : SET_FIELD(command_set, CHAR_BIT);
227 [ + + ]: 4169 : SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
228 [ + + ]: 4169 : SET_FIELD(header_digest, false);
229 [ + + ]: 4169 : SET_FIELD(data_digest, false);
230 [ + + ]: 4169 : SET_FIELD(disable_error_logging, false);
231 [ + + ]: 4169 : SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT);
232 [ + + ]: 4169 : SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE);
233 [ + + ]: 4169 : SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT);
234 [ + + ]: 4169 : SET_FIELD(disable_read_ana_log_page, false);
235 [ + + ]: 4169 : SET_FIELD(disable_read_changed_ns_list_log_page, false);
236 [ + + ]: 4169 : SET_FIELD(tls_psk, NULL);
237 [ + + ]: 4169 : SET_FIELD(dhchap_key, NULL);
238 [ + + ]: 4169 : SET_FIELD(dhchap_ctrlr_key, NULL);
239 [ + + ]: 4169 : SET_FIELD(dhchap_digests,
240 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA256) |
241 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA384) |
242 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA512));
243 [ + + ]: 4169 : SET_FIELD(dhchap_dhgroups,
244 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_NULL) |
245 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_2048) |
246 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_3072) |
247 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_4096) |
248 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_6144) |
249 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_8192));
250 : :
251 [ + + ]: 4169 : if (FIELD_OK(psk)) {
252 [ - + ]: 4163 : memset(opts->psk, 0, sizeof(opts->psk));
253 : : }
254 : :
255 : : #undef FIELD_OK
256 : : #undef SET_FIELD
257 : 4169 : }
258 : :
259 : : const struct spdk_nvme_ctrlr_opts *
260 : 2382 : spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr)
261 : : {
262 : 2382 : return &ctrlr->opts;
263 : : }
264 : :
265 : : /**
266 : : * This function will be called when the process allocates the IO qpair.
267 : : * Note: the ctrlr_lock must be held when calling this function.
268 : : */
269 : : static void
270 : 4843 : nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair)
271 : : {
272 : : struct spdk_nvme_ctrlr_process *active_proc;
273 : 4843 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
274 : :
275 : 4843 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
276 [ + + ]: 4843 : if (active_proc) {
277 : 4753 : TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq);
278 : 4753 : qpair->active_proc = active_proc;
279 : : }
280 : 4843 : }
281 : :
282 : : /**
283 : : * This function will be called when the process frees the IO qpair.
284 : : * Note: the ctrlr_lock must be held when calling this function.
285 : : */
286 : : static void
287 : 4843 : nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair)
288 : : {
289 : : struct spdk_nvme_ctrlr_process *active_proc;
290 : 4843 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
291 : : struct spdk_nvme_qpair *active_qpair, *tmp_qpair;
292 : :
293 : 4843 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
294 [ + + ]: 4843 : if (!active_proc) {
295 : 90 : return;
296 : : }
297 : :
298 [ + - ]: 5151 : TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs,
299 : : per_process_tailq, tmp_qpair) {
300 [ + + ]: 5151 : if (active_qpair == qpair) {
301 [ + + ]: 4753 : TAILQ_REMOVE(&active_proc->allocated_io_qpairs,
302 : : active_qpair, per_process_tailq);
303 : :
304 : 4753 : break;
305 : : }
306 : : }
307 : : }
308 : :
309 : : void
310 : 7723 : spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr,
311 : : struct spdk_nvme_io_qpair_opts *opts,
312 : : size_t opts_size)
313 : : {
314 [ - + ]: 7723 : assert(ctrlr);
315 : :
316 [ - + ]: 7723 : assert(opts);
317 : :
318 [ - + ]: 7723 : memset(opts, 0, opts_size);
319 : :
320 : : #define FIELD_OK(field) \
321 : : offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size
322 : :
323 [ + - ]: 7723 : if (FIELD_OK(qprio)) {
324 : 7723 : opts->qprio = SPDK_NVME_QPRIO_URGENT;
325 : : }
326 : :
327 [ + - ]: 7723 : if (FIELD_OK(io_queue_size)) {
328 : 7723 : opts->io_queue_size = ctrlr->opts.io_queue_size;
329 : : }
330 : :
331 [ + + ]: 7723 : if (FIELD_OK(io_queue_requests)) {
332 : 7717 : opts->io_queue_requests = ctrlr->opts.io_queue_requests;
333 : : }
334 : :
335 [ + + ]: 7723 : if (FIELD_OK(delay_cmd_submit)) {
336 : 7717 : opts->delay_cmd_submit = false;
337 : : }
338 : :
339 [ + + ]: 7723 : if (FIELD_OK(sq.vaddr)) {
340 : 7717 : opts->sq.vaddr = NULL;
341 : : }
342 : :
343 [ + + ]: 7723 : if (FIELD_OK(sq.paddr)) {
344 : 7717 : opts->sq.paddr = 0;
345 : : }
346 : :
347 [ + + ]: 7723 : if (FIELD_OK(sq.buffer_size)) {
348 : 7717 : opts->sq.buffer_size = 0;
349 : : }
350 : :
351 [ + + ]: 7723 : if (FIELD_OK(cq.vaddr)) {
352 : 7717 : opts->cq.vaddr = NULL;
353 : : }
354 : :
355 [ + + ]: 7723 : if (FIELD_OK(cq.paddr)) {
356 : 7717 : opts->cq.paddr = 0;
357 : : }
358 : :
359 [ + + ]: 7723 : if (FIELD_OK(cq.buffer_size)) {
360 : 7717 : opts->cq.buffer_size = 0;
361 : : }
362 : :
363 [ + + ]: 7723 : if (FIELD_OK(create_only)) {
364 : 7717 : opts->create_only = false;
365 : : }
366 : :
367 [ + + ]: 7723 : if (FIELD_OK(async_mode)) {
368 : 7717 : opts->async_mode = false;
369 : : }
370 : :
371 : : #undef FIELD_OK
372 : 7723 : }
373 : :
374 : : static struct spdk_nvme_qpair *
375 : 4886 : nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
376 : : const struct spdk_nvme_io_qpair_opts *opts)
377 : : {
378 : : int32_t qid;
379 : : struct spdk_nvme_qpair *qpair;
380 : : union spdk_nvme_cc_register cc;
381 : :
382 [ - + ]: 4886 : if (!ctrlr) {
383 : 0 : return NULL;
384 : : }
385 : :
386 : 4886 : nvme_ctrlr_lock(ctrlr);
387 : 4886 : cc.raw = ctrlr->process_init_cc.raw;
388 : :
389 [ + + ]: 4886 : if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) {
390 : 12 : nvme_ctrlr_unlock(ctrlr);
391 : 12 : return NULL;
392 : : }
393 : :
394 : : /*
395 : : * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
396 : : * default round robin arbitration method.
397 : : */
398 [ + + + + ]: 4874 : if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) {
399 [ + - - + ]: 18 : NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n");
400 : 18 : nvme_ctrlr_unlock(ctrlr);
401 : 18 : return NULL;
402 : : }
403 : :
404 : 4856 : qid = spdk_nvme_ctrlr_alloc_qid(ctrlr);
405 [ + + ]: 4856 : if (qid < 0) {
406 : 13 : nvme_ctrlr_unlock(ctrlr);
407 : 13 : return NULL;
408 : : }
409 : :
410 : 4843 : qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts);
411 [ - + ]: 4843 : if (qpair == NULL) {
412 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n");
413 : 0 : spdk_nvme_ctrlr_free_qid(ctrlr, qid);
414 : 0 : nvme_ctrlr_unlock(ctrlr);
415 : 0 : return NULL;
416 : : }
417 : :
418 : 4843 : TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
419 : :
420 : 4843 : nvme_ctrlr_proc_add_io_qpair(qpair);
421 : :
422 : 4843 : nvme_ctrlr_unlock(ctrlr);
423 : :
424 : 4843 : return qpair;
425 : : }
426 : :
427 : : int
428 : 4843 : spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
429 : : {
430 : : int rc;
431 : :
432 [ - + ]: 4843 : if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) {
433 : 0 : return -EISCONN;
434 : : }
435 : :
436 : 4843 : nvme_ctrlr_lock(ctrlr);
437 : 4843 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
438 : 4843 : nvme_ctrlr_unlock(ctrlr);
439 : :
440 [ - + ]: 4843 : if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
441 : 0 : spdk_delay_us(100);
442 : : }
443 : :
444 : 4843 : return rc;
445 : : }
446 : :
447 : : void
448 : 2213 : spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair)
449 : : {
450 : 2213 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
451 : :
452 : 2213 : nvme_ctrlr_lock(ctrlr);
453 : 2213 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
454 : 2213 : nvme_ctrlr_unlock(ctrlr);
455 : 2213 : }
456 : :
457 : : struct spdk_nvme_qpair *
458 : 4892 : spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
459 : : const struct spdk_nvme_io_qpair_opts *user_opts,
460 : : size_t opts_size)
461 : : {
462 : :
463 : 4892 : struct spdk_nvme_qpair *qpair = NULL;
464 : 1083 : struct spdk_nvme_io_qpair_opts opts;
465 : : int rc;
466 : :
467 : 4892 : nvme_ctrlr_lock(ctrlr);
468 : :
469 [ + + ]: 4892 : if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) {
470 : : /* When controller is resetting or initializing, free_io_qids is deleted or not created yet.
471 : : * We can't create IO qpair in that case */
472 : 6 : goto unlock;
473 : : }
474 : :
475 : : /*
476 : : * Get the default options, then overwrite them with the user-provided options
477 : : * up to opts_size.
478 : : *
479 : : * This allows for extensions of the opts structure without breaking
480 : : * ABI compatibility.
481 : : */
482 : 4886 : spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts));
483 [ + + ]: 4886 : if (user_opts) {
484 [ - + ]: 2859 : memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size));
485 : :
486 : : /* If user passes buffers, make sure they're big enough for the requested queue size */
487 [ - + ]: 2859 : if (opts.sq.vaddr) {
488 [ # # ]: 0 : if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) {
489 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n",
490 : : opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd)));
491 : 0 : goto unlock;
492 : : }
493 : : }
494 [ - + ]: 2859 : if (opts.cq.vaddr) {
495 [ # # ]: 0 : if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) {
496 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n",
497 : : opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl)));
498 : 0 : goto unlock;
499 : : }
500 : : }
501 : : }
502 : :
503 : 4886 : qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts);
504 : :
505 [ + + + + : 4886 : if (qpair == NULL || opts.create_only == true) {
+ + ]
506 : 2523 : goto unlock;
507 : : }
508 : :
509 : 2363 : rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair);
510 [ + + ]: 2363 : if (rc != 0) {
511 [ + - - + ]: 6 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n");
512 : 6 : nvme_ctrlr_proc_remove_io_qpair(qpair);
513 [ - + ]: 6 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
514 : 6 : spdk_bit_array_set(ctrlr->free_io_qids, qpair->id);
515 : 6 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
516 : 6 : qpair = NULL;
517 : 6 : goto unlock;
518 : : }
519 : :
520 : 3259 : unlock:
521 : 4892 : nvme_ctrlr_unlock(ctrlr);
522 : :
523 : 4892 : return qpair;
524 : : }
525 : :
526 : : int
527 : 12858 : spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair)
528 : : {
529 : : struct spdk_nvme_ctrlr *ctrlr;
530 : : enum nvme_qpair_state qpair_state;
531 : : int rc;
532 : :
533 [ - + ]: 12858 : assert(qpair != NULL);
534 [ - + ]: 12858 : assert(nvme_qpair_is_admin_queue(qpair) == false);
535 [ - + ]: 12858 : assert(qpair->ctrlr != NULL);
536 : :
537 : 12858 : ctrlr = qpair->ctrlr;
538 : 12858 : nvme_ctrlr_lock(ctrlr);
539 : 12858 : qpair_state = nvme_qpair_get_state(qpair);
540 : :
541 [ + + + + ]: 12858 : if (ctrlr->is_removed) {
542 : 12 : rc = -ENODEV;
543 : 12 : goto out;
544 : : }
545 : :
546 [ + + + + : 12846 : if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) {
- + ]
547 : 12 : rc = -EAGAIN;
548 : 12 : goto out;
549 : : }
550 : :
551 [ + + + + : 12834 : if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) {
- + ]
552 : 12 : rc = -ENXIO;
553 : 12 : goto out;
554 : : }
555 : :
556 [ + + ]: 12822 : if (qpair_state != NVME_QPAIR_DISCONNECTED) {
557 : 6 : rc = 0;
558 : 6 : goto out;
559 : : }
560 : :
561 : 12816 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
562 [ + + ]: 12816 : if (rc) {
563 : 12803 : rc = -EAGAIN;
564 : 12803 : goto out;
565 : : }
566 : :
567 : 13 : out:
568 : 12858 : nvme_ctrlr_unlock(ctrlr);
569 : 12858 : return rc;
570 : : }
571 : :
572 : : spdk_nvme_qp_failure_reason
573 : 1100572 : spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr)
574 : : {
575 : 1100572 : return ctrlr->adminq->transport_failure_reason;
576 : : }
577 : :
578 : : /*
579 : : * This internal function will attempt to take the controller
580 : : * lock before calling disconnect on a controller qpair.
581 : : * Functions already holding the controller lock should
582 : : * call nvme_transport_ctrlr_disconnect_qpair directly.
583 : : */
584 : : void
585 : 22430 : nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair)
586 : : {
587 : 22430 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
588 : :
589 [ - + ]: 22430 : assert(ctrlr != NULL);
590 : 22430 : nvme_ctrlr_lock(ctrlr);
591 : 22430 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
592 : 22430 : nvme_ctrlr_unlock(ctrlr);
593 : 22430 : }
594 : :
595 : : int
596 : 4837 : spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
597 : : {
598 : : struct spdk_nvme_ctrlr *ctrlr;
599 : :
600 [ - + ]: 4837 : if (qpair == NULL) {
601 : 0 : return 0;
602 : : }
603 : :
604 : 4837 : ctrlr = qpair->ctrlr;
605 : :
606 [ - + ]: 4837 : if (qpair->in_completion_context) {
607 : : /*
608 : : * There are many cases where it is convenient to delete an io qpair in the context
609 : : * of that qpair's completion routine. To handle this properly, set a flag here
610 : : * so that the completion routine will perform an actual delete after the context
611 : : * unwinds.
612 : : */
613 : 0 : qpair->delete_after_completion_context = 1;
614 : 0 : return 0;
615 : : }
616 : :
617 : 4837 : qpair->destroy_in_progress = 1;
618 : :
619 : 4837 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
620 : :
621 [ + + + - ]: 4837 : if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) {
622 : 2480 : spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair);
623 : : }
624 : :
625 : : /* Do not retry. */
626 : 4837 : nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING);
627 : :
628 : : /* In the multi-process case, a process may call this function on a foreign
629 : : * I/O qpair (i.e. one that this process did not create) when that qpairs process
630 : : * exits unexpectedly. In that case, we must not try to abort any reqs associated
631 : : * with that qpair, since the callbacks will also be foreign to this process.
632 : : */
633 [ + - ]: 4837 : if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) {
634 : 4837 : nvme_qpair_abort_all_queued_reqs(qpair);
635 : : }
636 : :
637 : 4837 : nvme_ctrlr_lock(ctrlr);
638 : :
639 : 4837 : nvme_ctrlr_proc_remove_io_qpair(qpair);
640 : :
641 [ + + ]: 4837 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
642 : 4837 : spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id);
643 : :
644 : 4837 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
645 : 4837 : nvme_ctrlr_unlock(ctrlr);
646 : 4837 : return 0;
647 : : }
648 : :
649 : : static void
650 : 124 : nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
651 : : struct spdk_nvme_intel_log_page_directory *log_page_directory)
652 : : {
653 [ - + ]: 124 : if (log_page_directory == NULL) {
654 : 0 : return;
655 : : }
656 : :
657 [ - + ]: 124 : assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL);
658 : :
659 : 124 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
660 : :
661 [ + + ]: 124 : if (log_page_directory->read_latency_log_len ||
662 [ + + ]: 17 : (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) {
663 : 113 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
664 : : }
665 [ + + ]: 124 : if (log_page_directory->write_latency_log_len ||
666 [ + + ]: 17 : (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) {
667 : 113 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
668 : : }
669 [ + + ]: 124 : if (log_page_directory->temperature_statistics_log_len) {
670 : 118 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
671 : : }
672 [ + + ]: 124 : if (log_page_directory->smart_log_len) {
673 : 112 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
674 : : }
675 [ + + ]: 124 : if (log_page_directory->marketing_description_log_len) {
676 : 112 : ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
677 : : }
678 : : }
679 : :
680 : : struct intel_log_pages_ctx {
681 : : struct spdk_nvme_intel_log_page_directory log_page_directory;
682 : : struct spdk_nvme_ctrlr *ctrlr;
683 : : };
684 : :
685 : : static void
686 : 112 : nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl)
687 : : {
688 : 112 : struct intel_log_pages_ctx *ctx = arg;
689 : 112 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
690 : :
691 [ + - + - ]: 112 : if (!spdk_nvme_cpl_is_error(cpl)) {
692 : 112 : nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory);
693 : : }
694 : :
695 : 112 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
696 : 112 : ctrlr->opts.admin_timeout_ms);
697 : 112 : free(ctx);
698 : 112 : }
699 : :
700 : : static int
701 : 112 : nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
702 : : {
703 : 112 : int rc = 0;
704 : : struct intel_log_pages_ctx *ctx;
705 : :
706 : 112 : ctx = calloc(1, sizeof(*ctx));
707 [ - + ]: 112 : if (!ctx) {
708 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
709 : 0 : ctrlr->opts.admin_timeout_ms);
710 : 0 : return 0;
711 : : }
712 : :
713 : 112 : ctx->ctrlr = ctrlr;
714 : :
715 : 112 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY,
716 : 112 : SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory,
717 : : sizeof(struct spdk_nvme_intel_log_page_directory),
718 : : 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx);
719 [ - + ]: 112 : if (rc != 0) {
720 : 0 : free(ctx);
721 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
722 : 0 : ctrlr->opts.admin_timeout_ms);
723 : 0 : return 0;
724 : : }
725 : :
726 : 112 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES,
727 : 112 : ctrlr->opts.admin_timeout_ms);
728 : :
729 : 112 : return 0;
730 : : }
731 : :
732 : : static int
733 : 37 : nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
734 : : {
735 : : uint32_t ana_log_page_size;
736 : :
737 : 37 : ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid *
738 : 37 : sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count *
739 : : sizeof(uint32_t);
740 : :
741 : : /* Number of active namespaces may have changed.
742 : : * Check if ANA log page fits into existing buffer.
743 : : */
744 [ + - ]: 37 : if (ana_log_page_size > ctrlr->ana_log_page_size) {
745 : : void *new_buffer;
746 : :
747 [ + + ]: 37 : if (ctrlr->ana_log_page) {
748 : 6 : new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size);
749 : : } else {
750 : 31 : new_buffer = calloc(1, ana_log_page_size);
751 : : }
752 : :
753 [ - + ]: 37 : if (!new_buffer) {
754 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n",
755 : : ana_log_page_size);
756 : 0 : return -ENXIO;
757 : : }
758 : :
759 : 37 : ctrlr->ana_log_page = new_buffer;
760 [ + + ]: 37 : if (ctrlr->copied_ana_desc) {
761 : 6 : new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size);
762 : : } else {
763 : 31 : new_buffer = calloc(1, ana_log_page_size);
764 : : }
765 : :
766 [ - + ]: 37 : if (!new_buffer) {
767 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n",
768 : : ana_log_page_size);
769 : 0 : return -ENOMEM;
770 : : }
771 : :
772 : 37 : ctrlr->copied_ana_desc = new_buffer;
773 : 37 : ctrlr->ana_log_page_size = ana_log_page_size;
774 : : }
775 : :
776 : 37 : return 0;
777 : : }
778 : :
779 : : static int
780 : 37 : nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
781 : : {
782 : : struct nvme_completion_poll_status *status;
783 : : int rc;
784 : :
785 : 37 : rc = nvme_ctrlr_alloc_ana_log_page(ctrlr);
786 [ - + ]: 37 : if (rc != 0) {
787 : 0 : return rc;
788 : : }
789 : :
790 : 37 : status = calloc(1, sizeof(*status));
791 [ - + ]: 37 : if (status == NULL) {
792 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
793 : 0 : return -ENOMEM;
794 : : }
795 : :
796 : 37 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS,
797 : 37 : SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page,
798 : : ctrlr->ana_log_page_size, 0,
799 : : nvme_completion_poll_cb, status);
800 [ - + ]: 37 : if (rc != 0) {
801 : 0 : free(status);
802 : 0 : return rc;
803 : : }
804 : :
805 [ - + ]: 37 : if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock,
806 : 37 : ctrlr->opts.admin_timeout_ms * 1000)) {
807 [ # # # # ]: 0 : if (!status->timed_out) {
808 : 0 : free(status);
809 : : }
810 : 0 : return -EIO;
811 : : }
812 : :
813 : 37 : free(status);
814 : 37 : return 0;
815 : : }
816 : :
817 : : static int
818 : 43 : nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc,
819 : : void *cb_arg)
820 : : {
821 : 43 : struct spdk_nvme_ctrlr *ctrlr = cb_arg;
822 : : struct spdk_nvme_ns *ns;
823 : : uint32_t i, nsid;
824 : :
825 [ + + ]: 110 : for (i = 0; i < desc->num_of_nsid; i++) {
826 : 67 : nsid = desc->nsid[i];
827 [ + - - + ]: 67 : if (nsid == 0 || nsid > ctrlr->cdata.nn) {
828 : 0 : continue;
829 : : }
830 : :
831 : 67 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
832 [ - + ]: 67 : assert(ns != NULL);
833 : :
834 : 67 : ns->ana_group_id = desc->ana_group_id;
835 : 67 : ns->ana_state = desc->ana_state;
836 : : }
837 : :
838 : 43 : return 0;
839 : : }
840 : :
841 : : int
842 : 37 : nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr,
843 : : spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg)
844 : : {
845 : : struct spdk_nvme_ana_group_descriptor *copied_desc;
846 : : uint8_t *orig_desc;
847 : : uint32_t i, desc_size, copy_len;
848 : 37 : int rc = 0;
849 : :
850 [ - + ]: 37 : if (ctrlr->ana_log_page == NULL) {
851 : 0 : return -EINVAL;
852 : : }
853 : :
854 : 37 : copied_desc = ctrlr->copied_ana_desc;
855 : :
856 : 37 : orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page);
857 : 37 : copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page);
858 : :
859 [ + + ]: 80 : for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) {
860 [ - + - + ]: 43 : memcpy(copied_desc, orig_desc, copy_len);
861 : :
862 : 43 : rc = cb_fn(copied_desc, cb_arg);
863 [ - + ]: 43 : if (rc != 0) {
864 : 0 : break;
865 : : }
866 : :
867 : 43 : desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) +
868 : 43 : copied_desc->num_of_nsid * sizeof(uint32_t);
869 : 43 : orig_desc += desc_size;
870 : 43 : copy_len -= desc_size;
871 : : }
872 : :
873 : 37 : return rc;
874 : : }
875 : :
876 : : static int
877 : 2379 : nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
878 : : {
879 : 2379 : int rc = 0;
880 : :
881 [ - + ]: 2379 : memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
882 : : /* Mandatory pages */
883 : 2379 : ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
884 : 2379 : ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
885 : 2379 : ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
886 [ + + ]: 2379 : if (ctrlr->cdata.lpa.celp) {
887 : 2289 : ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
888 : : }
889 : :
890 [ + + ]: 2379 : if (ctrlr->cdata.cmic.ana_reporting) {
891 : 343 : ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true;
892 [ + + + + ]: 343 : if (!ctrlr->opts.disable_read_ana_log_page) {
893 : 25 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
894 [ + - ]: 25 : if (rc == 0) {
895 : 25 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
896 : : ctrlr);
897 : : }
898 : : }
899 : : }
900 : :
901 [ + + ]: 2379 : if (ctrlr->cdata.ctratt.bits.fdps) {
902 : 28 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true;
903 : 28 : ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true;
904 : 28 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true;
905 : 28 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true;
906 : : }
907 : :
908 [ + + ]: 2379 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL &&
909 [ + + ]: 1235 : ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE &&
910 [ + - ]: 112 : !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) {
911 : 112 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES,
912 : 112 : ctrlr->opts.admin_timeout_ms);
913 : :
914 : : } else {
915 : 2267 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
916 : 2267 : ctrlr->opts.admin_timeout_ms);
917 : :
918 : : }
919 : :
920 : 2379 : return rc;
921 : : }
922 : :
923 : : static void
924 : 1235 : nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
925 : : {
926 : 1235 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
927 : 1235 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
928 : 1235 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
929 : 1235 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
930 : 1235 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
931 : 1235 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
932 : 1235 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
933 : 1235 : }
934 : :
935 : : static void
936 : 2391 : nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr)
937 : : {
938 : : uint32_t cdw11;
939 : : struct nvme_completion_poll_status *status;
940 : :
941 [ + + ]: 2391 : if (ctrlr->opts.arbitration_burst == 0) {
942 : 2379 : return;
943 : : }
944 : :
945 [ + + ]: 12 : if (ctrlr->opts.arbitration_burst > 7) {
946 [ + - - + ]: 6 : NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n");
947 : 6 : return;
948 : : }
949 : :
950 : 6 : status = calloc(1, sizeof(*status));
951 [ - + ]: 6 : if (!status) {
952 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
953 : 0 : return;
954 : : }
955 : :
956 : 6 : cdw11 = ctrlr->opts.arbitration_burst;
957 : :
958 [ + - ]: 6 : if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) {
959 : 6 : cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8;
960 : 6 : cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16;
961 : 6 : cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24;
962 : : }
963 : :
964 [ - + ]: 6 : if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION,
965 : : cdw11, 0, NULL, 0,
966 : : nvme_completion_poll_cb, status) < 0) {
967 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n");
968 : 0 : free(status);
969 : 0 : return;
970 : : }
971 : :
972 [ - + ]: 6 : if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
973 : 6 : ctrlr->opts.admin_timeout_ms * 1000)) {
974 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n");
975 : : }
976 : :
977 [ + + + - ]: 6 : if (!status->timed_out) {
978 : 6 : free(status);
979 : : }
980 : : }
981 : :
982 : : static void
983 : 2379 : nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
984 : : {
985 [ - + ]: 2379 : memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
986 : : /* Mandatory features */
987 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
988 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
989 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
990 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
991 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
992 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
993 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
994 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
995 : 2379 : ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
996 : : /* Optional features */
997 [ + + ]: 2379 : if (ctrlr->cdata.vwc.present) {
998 : 2155 : ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
999 : : }
1000 [ - + ]: 2379 : if (ctrlr->cdata.apsta.supported) {
1001 : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
1002 : : }
1003 [ - + ]: 2379 : if (ctrlr->cdata.hmpre) {
1004 : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
1005 : : }
1006 [ + + ]: 2379 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
1007 : 1235 : nvme_ctrlr_set_intel_supported_features(ctrlr);
1008 : : }
1009 : :
1010 : 2379 : nvme_ctrlr_set_arbitration_feature(ctrlr);
1011 : 2379 : }
1012 : :
1013 : : bool
1014 : 71396 : spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr)
1015 : : {
1016 [ - + ]: 71396 : return ctrlr->is_failed;
1017 : : }
1018 : :
1019 : : void
1020 : 523 : nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
1021 : : {
1022 : : /*
1023 : : * Set the flag here and leave the work failure of qpairs to
1024 : : * spdk_nvme_qpair_process_completions().
1025 : : */
1026 [ + + ]: 523 : if (hot_remove) {
1027 : 60 : ctrlr->is_removed = true;
1028 : : }
1029 : :
1030 [ - + + + ]: 523 : if (ctrlr->is_failed) {
1031 [ + + + + ]: 35 : NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n");
1032 : 35 : return;
1033 : : }
1034 : :
1035 [ - + + + ]: 488 : if (ctrlr->is_disconnecting) {
1036 [ - + - + : 8 : NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n");
- - - - ]
1037 : 8 : return;
1038 : : }
1039 : :
1040 : 480 : ctrlr->is_failed = true;
1041 : 480 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1042 : 480 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1043 [ + + + + ]: 480 : NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n");
1044 : : }
1045 : :
1046 : : /**
1047 : : * This public API function will try to take the controller lock.
1048 : : * Any private functions being called from a thread already holding
1049 : : * the ctrlr lock should call nvme_ctrlr_fail directly.
1050 : : */
1051 : : void
1052 : 27 : spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
1053 : : {
1054 : 27 : nvme_ctrlr_lock(ctrlr);
1055 : 27 : nvme_ctrlr_fail(ctrlr, false);
1056 : 27 : nvme_ctrlr_unlock(ctrlr);
1057 : 27 : }
1058 : :
1059 : : static void
1060 : 2421 : nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1061 : : {
1062 : 2421 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1063 : 2421 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1064 : :
1065 [ + - - + ]: 2421 : if (spdk_nvme_cpl_is_error(cpl)) {
1066 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1067 : 0 : ctx->shutdown_complete = true;
1068 : 0 : return;
1069 : : }
1070 : :
1071 [ - + - + ]: 2421 : if (ctrlr->opts.no_shn_notification) {
1072 : 0 : ctx->shutdown_complete = true;
1073 : 0 : return;
1074 : : }
1075 : :
1076 : : /*
1077 : : * The NVMe specification defines RTD3E to be the time between
1078 : : * setting SHN = 1 until the controller will set SHST = 10b.
1079 : : * If the device doesn't report RTD3 entry latency, or if it
1080 : : * reports RTD3 entry latency less than 10 seconds, pick
1081 : : * 10 seconds as a reasonable amount of time to
1082 : : * wait before proceeding.
1083 : : */
1084 [ - + + + : 2421 : NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e);
+ + + + ]
1085 : 2421 : ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000);
1086 : 2421 : ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000);
1087 [ - + + + : 2421 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms);
+ + + + ]
1088 : :
1089 : 2421 : ctx->shutdown_start_tsc = spdk_get_ticks();
1090 : 2421 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1091 : : }
1092 : :
1093 : : static void
1094 : 2421 : nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1095 : : {
1096 : 2421 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1097 : 2421 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1098 : : union spdk_nvme_cc_register cc;
1099 : : int rc;
1100 : :
1101 [ + - - + ]: 2421 : if (spdk_nvme_cpl_is_error(cpl)) {
1102 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1103 : 0 : ctx->shutdown_complete = true;
1104 : 0 : return;
1105 : : }
1106 : :
1107 [ - + ]: 2421 : assert(value <= UINT32_MAX);
1108 : 2421 : cc.raw = (uint32_t)value;
1109 : :
1110 [ - + - + ]: 2421 : if (ctrlr->opts.no_shn_notification) {
1111 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n");
# # # # ]
1112 [ # # ]: 0 : if (cc.bits.en == 0) {
1113 : 0 : ctx->shutdown_complete = true;
1114 : 0 : return;
1115 : : }
1116 : :
1117 : 0 : cc.bits.en = 0;
1118 : : } else {
1119 : 2421 : cc.bits.shn = SPDK_NVME_SHN_NORMAL;
1120 : : }
1121 : :
1122 : 2421 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx);
1123 [ - + ]: 2421 : if (rc != 0) {
1124 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1125 : 0 : ctx->shutdown_complete = true;
1126 : : }
1127 : : }
1128 : :
1129 : : static void
1130 : 2610 : nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr,
1131 : : struct nvme_ctrlr_detach_ctx *ctx)
1132 : : {
1133 : : int rc;
1134 : :
1135 [ + + + + ]: 2610 : if (ctrlr->is_removed) {
1136 : 57 : ctx->shutdown_complete = true;
1137 : 57 : return;
1138 : : }
1139 : :
1140 [ + + ]: 2553 : if (ctrlr->adminq == NULL ||
1141 [ + + ]: 2511 : ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) {
1142 [ - + - + : 128 : NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n");
- - - - ]
1143 : 128 : ctx->shutdown_complete = true;
1144 : 128 : return;
1145 : : }
1146 : :
1147 : 2425 : ctx->state = NVME_CTRLR_DETACH_SET_CC;
1148 : 2425 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx);
1149 [ + + ]: 2425 : if (rc != 0) {
1150 [ + + - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1151 : 4 : ctx->shutdown_complete = true;
1152 : : }
1153 : : }
1154 : :
1155 : : static void
1156 : 5314114 : nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1157 : : {
1158 : 5314114 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1159 : :
1160 [ + - - + ]: 5314114 : if (spdk_nvme_cpl_is_error(cpl)) {
1161 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n");
1162 : 0 : ctx->shutdown_complete = true;
1163 : 0 : return;
1164 : : }
1165 : :
1166 [ - + ]: 5314114 : assert(value <= UINT32_MAX);
1167 : 5314114 : ctx->csts.raw = (uint32_t)value;
1168 : 5314114 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE;
1169 : : }
1170 : :
1171 : : static int
1172 : 16833086 : nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr,
1173 : : struct nvme_ctrlr_detach_ctx *ctx)
1174 : : {
1175 : : union spdk_nvme_csts_register csts;
1176 : : uint32_t ms_waited;
1177 : :
1178 [ + + + - ]: 16833086 : switch (ctx->state) {
1179 : 6204858 : case NVME_CTRLR_DETACH_SET_CC:
1180 : : case NVME_CTRLR_DETACH_GET_CSTS:
1181 : : /* We're still waiting for the register operation to complete */
1182 : 6204858 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
1183 : 6204858 : return -EAGAIN;
1184 : :
1185 : 5314114 : case NVME_CTRLR_DETACH_CHECK_CSTS:
1186 : 5314114 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS;
1187 [ - + ]: 5314114 : if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) {
1188 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
1189 : 0 : return -EIO;
1190 : : }
1191 : 5314114 : return -EAGAIN;
1192 : :
1193 : 5314114 : case NVME_CTRLR_DETACH_GET_CSTS_DONE:
1194 : 5314114 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1195 : 5314114 : break;
1196 : :
1197 : 0 : default:
1198 : 0 : assert(0 && "Should never happen");
1199 : : return -EINVAL;
1200 : : }
1201 : :
1202 [ - + ]: 5314114 : ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz();
1203 : 5314114 : csts.raw = ctx->csts.raw;
1204 : :
1205 [ + + ]: 5314114 : if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
1206 [ - + + + : 2421 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited);
+ + + + ]
1207 : 2421 : return 0;
1208 : : }
1209 : :
1210 [ + - ]: 5311693 : if (ms_waited < ctx->shutdown_timeout_ms) {
1211 : 5311693 : return -EAGAIN;
1212 : : }
1213 : :
1214 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n",
1215 : : ctx->shutdown_timeout_ms);
1216 [ # # ]: 0 : if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) {
1217 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n");
1218 : : }
1219 : :
1220 : 0 : return 0;
1221 : : }
1222 : :
1223 : : static inline uint64_t
1224 : 4049830 : nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr)
1225 : : {
1226 : 4049830 : return ctrlr->cap.bits.to * 500;
1227 : : }
1228 : :
1229 : : static void
1230 : 2493 : nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1231 : : {
1232 : 2493 : struct spdk_nvme_ctrlr *ctrlr = ctx;
1233 : :
1234 [ + - - + ]: 2493 : if (spdk_nvme_cpl_is_error(cpl)) {
1235 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n");
1236 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1237 : 0 : return;
1238 : : }
1239 : :
1240 : 2493 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
1241 : : nvme_ctrlr_get_ready_timeout(ctrlr));
1242 : : }
1243 : :
1244 : : static int
1245 : 2535 : nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
1246 : : {
1247 : : union spdk_nvme_cc_register cc;
1248 : : int rc;
1249 : :
1250 : 2535 : rc = nvme_transport_ctrlr_enable(ctrlr);
1251 [ - + ]: 2535 : if (rc != 0) {
1252 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n");
1253 : 0 : return rc;
1254 : : }
1255 : :
1256 : 2535 : cc.raw = ctrlr->process_init_cc.raw;
1257 [ - + ]: 2535 : if (cc.bits.en != 0) {
1258 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n");
1259 : 0 : return -EINVAL;
1260 : : }
1261 : :
1262 : 2535 : cc.bits.en = 1;
1263 : 2535 : cc.bits.css = 0;
1264 : 2535 : cc.bits.shn = 0;
1265 : 2535 : cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
1266 : 2535 : cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
1267 : :
1268 : : /* Page size is 2 ^ (12 + mps). */
1269 : 2535 : cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12;
1270 : :
1271 : : /*
1272 : : * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS.
1273 : : * A controller that does not have any bit set in CAP.CSS is not spec compliant.
1274 : : * Try to support such a controller regardless.
1275 : : */
1276 [ + + ]: 2535 : if (ctrlr->cap.bits.css == 0) {
1277 [ - + - + : 126 : NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n");
- - - - ]
1278 : 126 : ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM;
1279 : : }
1280 : :
1281 : : /*
1282 : : * If the user did not explicitly request a command set, or supplied a value larger than
1283 : : * what can be saved in CC.CSS, use the most reasonable default.
1284 : : */
1285 [ + + ]: 2535 : if (ctrlr->opts.command_set >= CHAR_BIT) {
1286 [ + + ]: 2283 : if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) {
1287 : 929 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS;
1288 [ + - ]: 1354 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) {
1289 : 1354 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1290 [ # # ]: 0 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) {
1291 : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NOIO;
1292 : : } else {
1293 : : /* Invalid supported bits detected, falling back to NVM. */
1294 : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1295 : : }
1296 : : }
1297 : :
1298 : : /* Verify that the selected command set is supported by the controller. */
1299 [ - + - + ]: 2535 : if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) {
1300 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n",
# # # # ]
1301 : : ctrlr->opts.command_set, ctrlr->cap.bits.css);
1302 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n");
# # # # ]
1303 : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1304 : : }
1305 : :
1306 : 2535 : cc.bits.css = ctrlr->opts.command_set;
1307 : :
1308 [ + + + + ]: 2535 : switch (ctrlr->opts.arb_mechanism) {
1309 : 2469 : case SPDK_NVME_CC_AMS_RR:
1310 : 2469 : break;
1311 : 24 : case SPDK_NVME_CC_AMS_WRR:
1312 [ + + ]: 24 : if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) {
1313 : 12 : break;
1314 : : }
1315 : 12 : return -EINVAL;
1316 : 24 : case SPDK_NVME_CC_AMS_VS:
1317 [ + + ]: 24 : if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) {
1318 : 12 : break;
1319 : : }
1320 : 12 : return -EINVAL;
1321 : 18 : default:
1322 : 18 : return -EINVAL;
1323 : : }
1324 : :
1325 : 2493 : cc.bits.ams = ctrlr->opts.arb_mechanism;
1326 : 2493 : ctrlr->process_init_cc.raw = cc.raw;
1327 : :
1328 [ - + ]: 2493 : if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) {
1329 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
1330 : 0 : return -EIO;
1331 : : }
1332 : :
1333 : 2493 : return 0;
1334 : : }
1335 : :
1336 : : static const char *
1337 : 306 : nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
1338 : : {
1339 [ - + + + : 306 : switch (state) {
+ + + + +
- - - - +
- + + + +
- + + + +
+ + + + -
- - + + +
+ + + + +
+ - + - -
+ + - + -
+ + + -
- ]
1340 : 0 : case NVME_CTRLR_STATE_INIT_DELAY:
1341 : 0 : return "delay init";
1342 : 10 : case NVME_CTRLR_STATE_CONNECT_ADMINQ:
1343 : 10 : return "connect adminq";
1344 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
1345 : 10 : return "wait for connect adminq";
1346 : 10 : case NVME_CTRLR_STATE_READ_VS:
1347 : 10 : return "read vs";
1348 : 10 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
1349 : 10 : return "read vs wait for vs";
1350 : 10 : case NVME_CTRLR_STATE_READ_CAP:
1351 : 10 : return "read cap";
1352 : 10 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
1353 : 10 : return "read cap wait for cap";
1354 : 10 : case NVME_CTRLR_STATE_CHECK_EN:
1355 : 10 : return "check en";
1356 : 10 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
1357 : 10 : return "check en wait for cc";
1358 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
1359 : 0 : return "disable and wait for CSTS.RDY = 1";
1360 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1361 : 0 : return "disable and wait for CSTS.RDY = 1 reg";
1362 : 0 : case NVME_CTRLR_STATE_SET_EN_0:
1363 : 0 : return "set CC.EN = 0";
1364 : 0 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
1365 : 0 : return "set CC.EN = 0 wait for cc";
1366 : 10 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
1367 : 10 : return "disable and wait for CSTS.RDY = 0";
1368 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
1369 : 0 : return "disable and wait for CSTS.RDY = 0 reg";
1370 : 10 : case NVME_CTRLR_STATE_DISABLED:
1371 : 10 : return "controller is disabled";
1372 : 10 : case NVME_CTRLR_STATE_ENABLE:
1373 : 10 : return "enable controller by writing CC.EN = 1";
1374 : 10 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
1375 : 10 : return "enable controller by writing CC.EN = 1 reg";
1376 : 10 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
1377 : 10 : return "wait for CSTS.RDY = 1";
1378 : 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1379 : 0 : return "wait for CSTS.RDY = 1 reg";
1380 : 10 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
1381 : 10 : return "reset admin queue";
1382 : 10 : case NVME_CTRLR_STATE_IDENTIFY:
1383 : 10 : return "identify controller";
1384 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
1385 : 10 : return "wait for identify controller";
1386 : 10 : case NVME_CTRLR_STATE_CONFIGURE_AER:
1387 : 10 : return "configure AER";
1388 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
1389 : 10 : return "wait for configure aer";
1390 : 10 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
1391 : 10 : return "set keep alive timeout";
1392 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
1393 : 10 : return "wait for set keep alive timeout";
1394 : 6 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
1395 : 6 : return "identify controller iocs specific";
1396 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
1397 : 0 : return "wait for identify controller iocs specific";
1398 : 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
1399 : 0 : return "get zns cmd and effects log page";
1400 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
1401 : 0 : return "wait for get zns cmd and effects log page";
1402 : 6 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
1403 : 6 : return "set number of queues";
1404 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
1405 : 6 : return "wait for set number of queues";
1406 : 6 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
1407 : 6 : return "identify active ns";
1408 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
1409 : 6 : return "wait for identify active ns";
1410 : 6 : case NVME_CTRLR_STATE_IDENTIFY_NS:
1411 : 6 : return "identify ns";
1412 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
1413 : 6 : return "wait for identify ns";
1414 : 6 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
1415 : 6 : return "identify namespace id descriptors";
1416 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
1417 : 6 : return "wait for identify namespace id descriptors";
1418 : 6 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
1419 : 6 : return "identify ns iocs specific";
1420 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
1421 : 0 : return "wait for identify ns iocs specific";
1422 : 6 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
1423 : 6 : return "set supported log pages";
1424 : 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
1425 : 0 : return "set supported INTEL log pages";
1426 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
1427 : 0 : return "wait for supported INTEL log pages";
1428 : 6 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
1429 : 6 : return "set supported features";
1430 : 6 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
1431 : 6 : return "set doorbell buffer config";
1432 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
1433 : 0 : return "wait for doorbell buffer config";
1434 : 6 : case NVME_CTRLR_STATE_SET_HOST_ID:
1435 : 6 : return "set host ID";
1436 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
1437 : 0 : return "wait for set host ID";
1438 : 6 : case NVME_CTRLR_STATE_TRANSPORT_READY:
1439 : 6 : return "transport ready";
1440 : 10 : case NVME_CTRLR_STATE_READY:
1441 : 10 : return "ready";
1442 : 6 : case NVME_CTRLR_STATE_ERROR:
1443 : 6 : return "error";
1444 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
1445 : 0 : return "disconnected";
1446 : : }
1447 : 0 : return "unknown";
1448 : : };
1449 : :
1450 : : static void
1451 : 162334 : _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1452 : : uint64_t timeout_in_ms, bool quiet)
1453 : : {
1454 : : uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
1455 : :
1456 : 162334 : ctrlr->state = state;
1457 [ + + ]: 162334 : if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) {
1458 [ - + ]: 65098 : if (!quiet) {
1459 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n",
# # # # ]
1460 : : nvme_ctrlr_state_string(ctrlr->state));
1461 : : }
1462 : 65098 : return;
1463 : : }
1464 : :
1465 [ + + ]: 97236 : if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
1466 : 28689 : goto inf;
1467 : : }
1468 : :
1469 : 68547 : ticks_per_ms = spdk_get_ticks_hz() / 1000;
1470 [ - + - + ]: 68547 : if (timeout_in_ms > UINT64_MAX / ticks_per_ms) {
1471 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr,
1472 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1473 : 0 : goto inf;
1474 : : }
1475 : :
1476 : 68547 : now_ticks = spdk_get_ticks();
1477 : 68547 : timeout_in_ticks = timeout_in_ms * ticks_per_ms;
1478 [ + + ]: 68547 : if (timeout_in_ticks > UINT64_MAX - now_ticks) {
1479 [ + - - + ]: 6 : NVME_CTRLR_ERRLOG(ctrlr,
1480 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1481 : 6 : goto inf;
1482 : : }
1483 : :
1484 : 68541 : ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
1485 [ + - ]: 68541 : if (!quiet) {
1486 [ - + + + : 68541 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n",
+ + + + ]
1487 : : nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
1488 : : }
1489 : 68541 : return;
1490 : 28695 : inf:
1491 [ + - ]: 28695 : if (!quiet) {
1492 [ - + + + : 28695 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n",
+ + + + ]
1493 : : nvme_ctrlr_state_string(ctrlr->state));
1494 : : }
1495 : 28695 : ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
1496 : : }
1497 : :
1498 : : static void
1499 : 97236 : nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1500 : : uint64_t timeout_in_ms)
1501 : : {
1502 : 97236 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false);
1503 : 97236 : }
1504 : :
1505 : : static void
1506 : 65098 : nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1507 : : uint64_t timeout_in_ms)
1508 : : {
1509 : 65098 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true);
1510 : 65098 : }
1511 : :
1512 : : static void
1513 : 3083 : nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1514 : : {
1515 : 3083 : spdk_free(ctrlr->cdata_zns);
1516 : 3083 : ctrlr->cdata_zns = NULL;
1517 : 3083 : }
1518 : :
1519 : : static void
1520 : 3083 : nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1521 : : {
1522 : 3083 : nvme_ctrlr_free_zns_specific_data(ctrlr);
1523 : 3083 : }
1524 : :
1525 : : static void
1526 : 3089 : nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr)
1527 : : {
1528 [ + + ]: 3089 : if (ctrlr->shadow_doorbell) {
1529 : 682 : spdk_free(ctrlr->shadow_doorbell);
1530 : 682 : ctrlr->shadow_doorbell = NULL;
1531 : : }
1532 : :
1533 [ + + ]: 3089 : if (ctrlr->eventidx) {
1534 : 682 : spdk_free(ctrlr->eventidx);
1535 : 682 : ctrlr->eventidx = NULL;
1536 : : }
1537 : 3089 : }
1538 : :
1539 : : static void
1540 : 686 : nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl)
1541 : : {
1542 : 686 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1543 : :
1544 [ + - - + ]: 686 : if (spdk_nvme_cpl_is_error(cpl)) {
1545 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n");
1546 : : } else {
1547 [ - + - + : 686 : NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n");
- - - - ]
1548 : : }
1549 : 686 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1550 : 686 : ctrlr->opts.admin_timeout_ms);
1551 : 686 : }
1552 : :
1553 : : static int
1554 : 2373 : nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr)
1555 : : {
1556 : 2373 : int rc = 0;
1557 : 533 : uint64_t prp1, prp2, len;
1558 : :
1559 [ + + ]: 2373 : if (!ctrlr->cdata.oacs.doorbell_buffer_config) {
1560 : 1687 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1561 : 1687 : ctrlr->opts.admin_timeout_ms);
1562 : 1687 : return 0;
1563 : : }
1564 : :
1565 [ - + ]: 686 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
1566 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1567 : 0 : ctrlr->opts.admin_timeout_ms);
1568 : 0 : return 0;
1569 : : }
1570 : :
1571 : : /* only 1 page size for doorbell buffer */
1572 : 686 : ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1573 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1574 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1575 [ - + ]: 686 : if (ctrlr->shadow_doorbell == NULL) {
1576 : 0 : rc = -ENOMEM;
1577 : 0 : goto error;
1578 : : }
1579 : :
1580 : 686 : len = ctrlr->page_size;
1581 : 686 : prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len);
1582 [ + - - + ]: 686 : if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1583 : 0 : rc = -EFAULT;
1584 : 0 : goto error;
1585 : : }
1586 : :
1587 : 686 : ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1588 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1589 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1590 [ - + ]: 686 : if (ctrlr->eventidx == NULL) {
1591 : 0 : rc = -ENOMEM;
1592 : 0 : goto error;
1593 : : }
1594 : :
1595 : 686 : len = ctrlr->page_size;
1596 : 686 : prp2 = spdk_vtophys(ctrlr->eventidx, &len);
1597 [ + - - + ]: 686 : if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1598 : 0 : rc = -EFAULT;
1599 : 0 : goto error;
1600 : : }
1601 : :
1602 : 686 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG,
1603 : 686 : ctrlr->opts.admin_timeout_ms);
1604 : :
1605 : 686 : rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2,
1606 : : nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr);
1607 [ - + ]: 686 : if (rc != 0) {
1608 : 0 : goto error;
1609 : : }
1610 : :
1611 : 686 : return 0;
1612 : :
1613 : 0 : error:
1614 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1615 : 0 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1616 : 0 : return rc;
1617 : : }
1618 : :
1619 : : void
1620 : 5536 : nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr)
1621 : : {
1622 : : struct nvme_request *req, *tmp;
1623 : 5536 : struct spdk_nvme_cpl cpl = {};
1624 : :
1625 : 5536 : cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION;
1626 : 5536 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
1627 : :
1628 [ - + ]: 5536 : STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) {
1629 [ # # ]: 0 : STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq);
1630 : 0 : ctrlr->outstanding_aborts++;
1631 : :
1632 : 0 : nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl);
1633 : : }
1634 : 5536 : }
1635 : :
1636 : : static int
1637 : 479 : nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1638 : : {
1639 [ + + + + : 479 : if (ctrlr->is_resetting || ctrlr->is_removed) {
- + - + ]
1640 : : /*
1641 : : * Controller is already resetting or has been removed. Return
1642 : : * immediately since there is no need to kick off another
1643 : : * reset in these cases.
1644 : : */
1645 [ + + + - ]: 6 : return ctrlr->is_resetting ? -EBUSY : -ENXIO;
1646 : : }
1647 : :
1648 : 473 : ctrlr->is_resetting = true;
1649 : 473 : ctrlr->is_failed = false;
1650 : 473 : ctrlr->is_disconnecting = true;
1651 : 473 : ctrlr->prepare_for_reset = true;
1652 : :
1653 [ + + + + ]: 473 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n");
1654 : :
1655 : : /* Disable keep-alive, it'll be re-enabled as part of the init process */
1656 : 473 : ctrlr->keep_alive_interval_ticks = 0;
1657 : :
1658 : : /* Abort all of the queued abort requests */
1659 : 473 : nvme_ctrlr_abort_queued_aborts(ctrlr);
1660 : :
1661 : 473 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
1662 : :
1663 : 473 : ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1664 : 473 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1665 : :
1666 : 473 : return 0;
1667 : : }
1668 : :
1669 : : static void
1670 : 473 : nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr)
1671 : : {
1672 [ - + - + ]: 473 : assert(ctrlr->is_failed == false);
1673 : 473 : ctrlr->is_disconnecting = false;
1674 : :
1675 : : /* Doorbell buffer config is invalid during reset */
1676 : 473 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1677 : :
1678 : : /* I/O Command Set Specific Identify Controller data is invalidated during reset */
1679 : 473 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
1680 : :
1681 : 473 : spdk_bit_array_free(&ctrlr->free_io_qids);
1682 : :
1683 : : /* Set the state back to DISCONNECTED to cause a full hardware reset. */
1684 : 473 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE);
1685 : 473 : }
1686 : :
1687 : : int
1688 : 416 : spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1689 : : {
1690 : : int rc;
1691 : :
1692 : 416 : nvme_ctrlr_lock(ctrlr);
1693 : 416 : rc = nvme_ctrlr_disconnect(ctrlr);
1694 : 416 : nvme_ctrlr_unlock(ctrlr);
1695 : :
1696 : 416 : return rc;
1697 : : }
1698 : :
1699 : : void
1700 : 473 : spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr)
1701 : : {
1702 : 473 : nvme_ctrlr_lock(ctrlr);
1703 : :
1704 : 473 : ctrlr->prepare_for_reset = false;
1705 : :
1706 : : /* Set the state back to INIT to cause a full hardware reset. */
1707 : 473 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
1708 : :
1709 : : /* Return without releasing ctrlr_lock. ctrlr_lock will be released when
1710 : : * spdk_nvme_ctrlr_reset_poll_async() returns 0.
1711 : : */
1712 : 473 : }
1713 : :
1714 : : int
1715 : 29 : nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
1716 : : {
1717 : : bool async;
1718 : : int rc;
1719 : :
1720 [ + - + - ]: 58 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc ||
1721 [ - + ]: 58 : spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) {
1722 : 0 : assert(false);
1723 : : return -EINVAL;
1724 : : }
1725 : :
1726 : : /* Force a synchronous connect. */
1727 : 29 : async = qpair->async;
1728 : 29 : qpair->async = false;
1729 : 29 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
1730 : 29 : qpair->async = async;
1731 : :
1732 [ - + ]: 29 : if (rc != 0) {
1733 : 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1734 : : }
1735 : :
1736 : 29 : return rc;
1737 : : }
1738 : :
1739 : : /**
1740 : : * This function will be called when the controller is being reinitialized.
1741 : : * Note: the ctrlr_lock must be held when calling this function.
1742 : : */
1743 : : int
1744 : 105049 : spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr)
1745 : : {
1746 : : struct spdk_nvme_ns *ns, *tmp_ns;
1747 : : struct spdk_nvme_qpair *qpair;
1748 : 105049 : int rc = 0, rc_tmp = 0;
1749 : :
1750 [ + + ]: 105049 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1751 [ + + + - ]: 341 : NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n");
1752 : 341 : rc = -1;
1753 : : }
1754 [ + + + + ]: 105049 : if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) {
1755 : 104576 : return -EAGAIN;
1756 : : }
1757 : :
1758 : : /*
1759 : : * For non-fabrics controllers, the memory locations of the transport qpair
1760 : : * don't change when the controller is reset. They simply need to be
1761 : : * re-enabled with admin commands to the controller. For fabric
1762 : : * controllers we need to disconnect and reconnect the qpair on its
1763 : : * own thread outside of the context of the reset.
1764 : : */
1765 [ + + + + ]: 473 : if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
1766 : : /* Reinitialize qpairs */
1767 [ + + ]: 121 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1768 : : /* Always clear the qid bit here, even for a foreign qpair. We need
1769 : : * to make sure another process doesn't get the chance to grab that
1770 : : * qid.
1771 : : */
1772 [ - + ]: 29 : assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id));
1773 : 29 : spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id);
1774 [ + + ]: 29 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) {
1775 : : /*
1776 : : * We cannot reinitialize a foreign qpair. The qpair's owning
1777 : : * process will take care of it. Set failure reason to FAILURE_RESET
1778 : : * to ensure that happens.
1779 : : */
1780 : 23 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET;
1781 : 23 : continue;
1782 : : }
1783 : 6 : rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair);
1784 [ - + ]: 6 : if (rc_tmp != 0) {
1785 : 0 : rc = rc_tmp;
1786 : : }
1787 : : }
1788 : : }
1789 : :
1790 : : /*
1791 : : * Take this opportunity to remove inactive namespaces. During a reset namespace
1792 : : * handles can be invalidated.
1793 : : */
1794 [ + + + - ]: 1017 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
1795 [ + + + + ]: 544 : if (!ns->active) {
1796 : 7 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
1797 : 7 : spdk_free(ns);
1798 : : }
1799 : : }
1800 : :
1801 [ + + ]: 473 : if (rc) {
1802 : 341 : nvme_ctrlr_fail(ctrlr, false);
1803 : : }
1804 : 473 : ctrlr->is_resetting = false;
1805 : :
1806 : 473 : nvme_ctrlr_unlock(ctrlr);
1807 : :
1808 [ + + ]: 473 : if (!ctrlr->cdata.oaes.ns_attribute_notices) {
1809 : : /*
1810 : : * If controller doesn't support ns_attribute_notices and
1811 : : * namespace attributes change (e.g. number of namespaces)
1812 : : * we need to update system handling device reset.
1813 : : */
1814 : 18 : nvme_io_msg_ctrlr_update(ctrlr);
1815 : : }
1816 : :
1817 : 473 : return rc;
1818 : : }
1819 : :
1820 : : /*
1821 : : * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset
1822 : : * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair.
1823 : : * The following two functions are added to do a Controller Level Reset. They have
1824 : : * to be called under the nvme controller's lock.
1825 : : */
1826 : : void
1827 : 92 : nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
1828 : : {
1829 [ - + - + ]: 92 : assert(ctrlr->is_disconnecting == true);
1830 : :
1831 : 92 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
1832 : 92 : }
1833 : :
1834 : : int
1835 : 1250 : nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr)
1836 : : {
1837 : 1250 : int rc = 0;
1838 : :
1839 [ - + ]: 1250 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1840 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n");
1841 : 0 : rc = -1;
1842 : : }
1843 : :
1844 [ + + + - ]: 1250 : if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) {
1845 : 1158 : return -EAGAIN;
1846 : : }
1847 : :
1848 : 92 : return rc;
1849 : : }
1850 : :
1851 : : static void
1852 : 57 : nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr)
1853 : : {
1854 : : struct spdk_nvme_qpair *qpair;
1855 : :
1856 [ + + ]: 93 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1857 : 36 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1858 : : }
1859 : 57 : }
1860 : :
1861 : : int
1862 : 63 : spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
1863 : : {
1864 : : int rc;
1865 : :
1866 : 63 : nvme_ctrlr_lock(ctrlr);
1867 : :
1868 : 63 : rc = nvme_ctrlr_disconnect(ctrlr);
1869 [ + + ]: 63 : if (rc == 0) {
1870 : 57 : nvme_ctrlr_fail_io_qpairs(ctrlr);
1871 : : }
1872 : :
1873 : 63 : nvme_ctrlr_unlock(ctrlr);
1874 : :
1875 [ + + ]: 63 : if (rc != 0) {
1876 [ + - ]: 6 : if (rc == -EBUSY) {
1877 : 6 : rc = 0;
1878 : : }
1879 : 6 : return rc;
1880 : : }
1881 : :
1882 : : while (1) {
1883 : 387 : rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr);
1884 [ + + ]: 387 : if (rc == -ENXIO) {
1885 : 57 : break;
1886 : : }
1887 : : }
1888 : :
1889 : 57 : spdk_nvme_ctrlr_reconnect_async(ctrlr);
1890 : :
1891 : : while (true) {
1892 : 11973 : rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr);
1893 [ + + ]: 11973 : if (rc != -EAGAIN) {
1894 : 57 : break;
1895 : : }
1896 : : }
1897 : :
1898 : 57 : return rc;
1899 : : }
1900 : :
1901 : : int
1902 : 0 : spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr)
1903 : : {
1904 : : union spdk_nvme_cap_register cap;
1905 : 0 : int rc = 0;
1906 : :
1907 : 0 : cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
1908 [ # # ]: 0 : if (cap.bits.nssrs == 0) {
1909 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n");
1910 : 0 : return -ENOTSUP;
1911 : : }
1912 : :
1913 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n");
1914 : 0 : nvme_ctrlr_lock(ctrlr);
1915 : 0 : ctrlr->is_resetting = true;
1916 : 0 : rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE);
1917 : 0 : ctrlr->is_resetting = false;
1918 : :
1919 : 0 : nvme_ctrlr_unlock(ctrlr);
1920 : : /*
1921 : : * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause
1922 : : * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup.
1923 : : */
1924 : 0 : return rc;
1925 : : }
1926 : :
1927 : : int
1928 : 41 : spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid)
1929 : : {
1930 : 41 : int rc = 0;
1931 : :
1932 : 41 : nvme_ctrlr_lock(ctrlr);
1933 : :
1934 [ + + + + ]: 41 : if (ctrlr->is_failed == false) {
1935 : 6 : rc = -EPERM;
1936 : 6 : goto out;
1937 : : }
1938 : :
1939 [ + + ]: 35 : if (trid->trtype != ctrlr->trid.trtype) {
1940 : 6 : rc = -EINVAL;
1941 : 6 : goto out;
1942 : : }
1943 : :
1944 [ + + - + : 29 : if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) {
+ + ]
1945 : 6 : rc = -EINVAL;
1946 : 6 : goto out;
1947 : : }
1948 : :
1949 : 23 : ctrlr->trid = *trid;
1950 : :
1951 : 41 : out:
1952 : 41 : nvme_ctrlr_unlock(ctrlr);
1953 : 41 : return rc;
1954 : : }
1955 : :
1956 : : void
1957 : 1465 : spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr,
1958 : : spdk_nvme_remove_cb remove_cb, void *remove_ctx)
1959 : : {
1960 [ - + ]: 1465 : if (!spdk_process_is_primary()) {
1961 : 0 : return;
1962 : : }
1963 : :
1964 : 1465 : nvme_ctrlr_lock(ctrlr);
1965 : 1465 : ctrlr->remove_cb = remove_cb;
1966 : 1465 : ctrlr->cb_ctx = remove_ctx;
1967 : 1465 : nvme_ctrlr_unlock(ctrlr);
1968 : : }
1969 : :
1970 : : static void
1971 : 2505 : nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
1972 : : {
1973 : 2505 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1974 : :
1975 [ + - - + ]: 2505 : if (spdk_nvme_cpl_is_error(cpl)) {
1976 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n");
1977 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1978 : 0 : return;
1979 : : }
1980 : :
1981 : : /*
1982 : : * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
1983 : : * controller supports.
1984 : : */
1985 : 2505 : ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr);
1986 [ - + + + : 2505 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + + + ]
1987 [ + + ]: 2505 : if (ctrlr->cdata.mdts > 0) {
1988 [ - + + + : 2165 : ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size,
- + ]
1989 : : ctrlr->min_page_size * (1 << ctrlr->cdata.mdts));
1990 [ - + + + : 2165 : NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + + + ]
1991 : : }
1992 : :
1993 [ - + + + : 2505 : NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid);
+ + + + ]
1994 [ + + ]: 2505 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
1995 : 814 : ctrlr->cntlid = ctrlr->cdata.cntlid;
1996 : : } else {
1997 : : /*
1998 : : * Fabrics controllers should already have CNTLID from the Connect command.
1999 : : *
2000 : : * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data,
2001 : : * trust the one from Connect.
2002 : : */
2003 [ + + ]: 1691 : if (ctrlr->cntlid != ctrlr->cdata.cntlid) {
2004 [ - + + + : 35 : NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n",
+ - - + ]
2005 : : ctrlr->cdata.cntlid, ctrlr->cntlid);
2006 : : }
2007 : : }
2008 : :
2009 [ + + + - ]: 2505 : if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
2010 [ - + ]: 2282 : assert(ctrlr->cdata.sgls.supported != 0x3);
2011 : 2282 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
2012 [ + + ]: 2282 : if (ctrlr->cdata.sgls.supported == 0x2) {
2013 : 36 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT;
2014 : : }
2015 : :
2016 : 2282 : ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr);
2017 [ - + + + : 2282 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges);
+ + + + ]
2018 : : }
2019 : :
2020 [ + + + - ]: 2505 : if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
2021 : 1 : ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED;
2022 : : }
2023 : :
2024 [ + + + - ]: 2505 : if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
2025 : 44 : ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
2026 : : }
2027 : :
2028 [ + + ]: 2505 : if (ctrlr->cdata.oacs.directives) {
2029 : 681 : ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED;
2030 : : }
2031 : :
2032 [ - + + + : 2505 : NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n",
+ + + + ]
2033 : : ctrlr->cdata.fuses.compare_and_write);
2034 [ + + ]: 2505 : if (ctrlr->cdata.fuses.compare_and_write) {
2035 : 1280 : ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED;
2036 : : }
2037 : :
2038 : 2505 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2039 : 2505 : ctrlr->opts.admin_timeout_ms);
2040 : : }
2041 : :
2042 : : static int
2043 : 2505 : nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
2044 : : {
2045 : : int rc;
2046 : :
2047 : 2505 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
2048 : 2505 : ctrlr->opts.admin_timeout_ms);
2049 : :
2050 : 2505 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0,
2051 : 2505 : &ctrlr->cdata, sizeof(ctrlr->cdata),
2052 : : nvme_ctrlr_identify_done, ctrlr);
2053 [ - + ]: 2505 : if (rc != 0) {
2054 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2055 : 0 : return rc;
2056 : : }
2057 : :
2058 : 2505 : return 0;
2059 : : }
2060 : :
2061 : : static void
2062 : 997 : nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl)
2063 : : {
2064 : : struct spdk_nvme_cmds_and_effect_log_page *log_page;
2065 : 997 : struct spdk_nvme_ctrlr *ctrlr = arg;
2066 : :
2067 [ + - - + ]: 997 : if (spdk_nvme_cpl_is_error(cpl)) {
2068 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n");
2069 : 0 : spdk_free(ctrlr->tmp_ptr);
2070 : 0 : ctrlr->tmp_ptr = NULL;
2071 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2072 : 0 : return;
2073 : : }
2074 : :
2075 : 997 : log_page = ctrlr->tmp_ptr;
2076 : :
2077 [ + - ]: 997 : if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) {
2078 : 997 : ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED;
2079 : : }
2080 : 997 : spdk_free(ctrlr->tmp_ptr);
2081 : 997 : ctrlr->tmp_ptr = NULL;
2082 : :
2083 : 997 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms);
2084 : : }
2085 : :
2086 : : static int
2087 : 997 : nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr)
2088 : : {
2089 : : int rc;
2090 : :
2091 [ - + ]: 997 : assert(!ctrlr->tmp_ptr);
2092 : 997 : ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL,
2093 : : SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2094 [ - + ]: 997 : if (!ctrlr->tmp_ptr) {
2095 : 0 : rc = -ENOMEM;
2096 : 0 : goto error;
2097 : : }
2098 : :
2099 : 997 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG,
2100 : 997 : ctrlr->opts.admin_timeout_ms);
2101 : :
2102 : 997 : rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG,
2103 : : 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page),
2104 : : 0, 0, 0, SPDK_NVME_CSI_ZNS << 24,
2105 : : nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr);
2106 [ - + ]: 997 : if (rc != 0) {
2107 : 0 : goto error;
2108 : : }
2109 : :
2110 : 997 : return 0;
2111 : :
2112 : 0 : error:
2113 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2114 : 0 : spdk_free(ctrlr->tmp_ptr);
2115 : 0 : ctrlr->tmp_ptr = NULL;
2116 : 0 : return rc;
2117 : : }
2118 : :
2119 : : static void
2120 : 997 : nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl)
2121 : : {
2122 : 997 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2123 : :
2124 [ + - - + ]: 997 : if (spdk_nvme_cpl_is_error(cpl)) {
2125 : : /* no need to print an error, the controller simply does not support ZNS */
2126 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2127 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2128 : 0 : ctrlr->opts.admin_timeout_ms);
2129 : 0 : return;
2130 : : }
2131 : :
2132 : : /* A zero zasl value means use mdts */
2133 [ - + ]: 997 : if (ctrlr->cdata_zns->zasl) {
2134 [ # # ]: 0 : uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl);
2135 : 0 : ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append);
2136 : : } else {
2137 : 997 : ctrlr->max_zone_append_size = ctrlr->max_xfer_size;
2138 : : }
2139 : :
2140 : 997 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG,
2141 : 997 : ctrlr->opts.admin_timeout_ms);
2142 : : }
2143 : :
2144 : : /**
2145 : : * This function will try to fetch the I/O Command Specific Controller data structure for
2146 : : * each I/O Command Set supported by SPDK.
2147 : : *
2148 : : * If an I/O Command Set is not supported by the controller, "Invalid Field in Command"
2149 : : * will be returned. Since we are fetching in a exploratively way, getting an error back
2150 : : * from the controller should not be treated as fatal.
2151 : : *
2152 : : * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set).
2153 : : *
2154 : : * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific
2155 : : * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set).
2156 : : */
2157 : : static int
2158 : 2397 : nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2159 : : {
2160 : : int rc;
2161 : :
2162 [ + + ]: 2397 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2163 : 1400 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2164 : 1400 : ctrlr->opts.admin_timeout_ms);
2165 : 1400 : return 0;
2166 : : }
2167 : :
2168 : : /*
2169 : : * Since SPDK currently only needs to fetch a single Command Set, keep the code here,
2170 : : * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates,
2171 : : * which would require additional functions and complexity for no good reason.
2172 : : */
2173 [ - + ]: 997 : assert(!ctrlr->cdata_zns);
2174 : 997 : ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2175 : : SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2176 [ - + ]: 997 : if (!ctrlr->cdata_zns) {
2177 : 0 : rc = -ENOMEM;
2178 : 0 : goto error;
2179 : : }
2180 : :
2181 : 997 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC,
2182 : 997 : ctrlr->opts.admin_timeout_ms);
2183 : :
2184 : 997 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS,
2185 : 997 : ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns),
2186 : : nvme_ctrlr_identify_zns_specific_done, ctrlr);
2187 [ - + ]: 997 : if (rc != 0) {
2188 : 0 : goto error;
2189 : : }
2190 : :
2191 : 997 : return 0;
2192 : :
2193 : 0 : error:
2194 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2195 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2196 : 0 : return rc;
2197 : : }
2198 : :
2199 : : enum nvme_active_ns_state {
2200 : : NVME_ACTIVE_NS_STATE_IDLE,
2201 : : NVME_ACTIVE_NS_STATE_PROCESSING,
2202 : : NVME_ACTIVE_NS_STATE_DONE,
2203 : : NVME_ACTIVE_NS_STATE_ERROR
2204 : : };
2205 : :
2206 : : typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *);
2207 : :
2208 : : struct nvme_active_ns_ctx {
2209 : : struct spdk_nvme_ctrlr *ctrlr;
2210 : : uint32_t page_count;
2211 : : uint32_t next_nsid;
2212 : : uint32_t *new_ns_list;
2213 : : nvme_active_ns_ctx_deleter deleter;
2214 : :
2215 : : enum nvme_active_ns_state state;
2216 : : };
2217 : :
2218 : : static struct nvme_active_ns_ctx *
2219 : 2649 : nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter)
2220 : : {
2221 : : struct nvme_active_ns_ctx *ctx;
2222 : 2649 : uint32_t *new_ns_list = NULL;
2223 : :
2224 : 2649 : ctx = calloc(1, sizeof(*ctx));
2225 [ - + ]: 2649 : if (!ctx) {
2226 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n");
2227 : 0 : return NULL;
2228 : : }
2229 : :
2230 : 2649 : new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size,
2231 : : NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE);
2232 [ - + ]: 2649 : if (!new_ns_list) {
2233 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n");
2234 : 0 : free(ctx);
2235 : 0 : return NULL;
2236 : : }
2237 : :
2238 : 2649 : ctx->page_count = 1;
2239 : 2649 : ctx->new_ns_list = new_ns_list;
2240 : 2649 : ctx->ctrlr = ctrlr;
2241 : 2649 : ctx->deleter = deleter;
2242 : :
2243 : 2649 : return ctx;
2244 : : }
2245 : :
2246 : : static void
2247 : 2649 : nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx)
2248 : : {
2249 : 2649 : spdk_free(ctx->new_ns_list);
2250 : 2649 : free(ctx);
2251 : 2649 : }
2252 : :
2253 : : static int
2254 : 112309 : nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2255 : : {
2256 : 92494 : struct spdk_nvme_ns tmp, *ns;
2257 : :
2258 [ - + ]: 112309 : assert(ctrlr != NULL);
2259 : :
2260 : 112309 : tmp.id = nsid;
2261 : 112309 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
2262 [ - + ]: 112309 : if (ns == NULL) {
2263 : 0 : return -EINVAL;
2264 : : }
2265 : :
2266 : 112309 : nvme_ns_destruct(ns);
2267 : 112309 : ns->active = false;
2268 : :
2269 : 112309 : return 0;
2270 : : }
2271 : :
2272 : : static int
2273 : 76000 : nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2274 : : {
2275 : : struct spdk_nvme_ns *ns;
2276 : :
2277 [ + - - + ]: 76000 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
2278 : 0 : return -EINVAL;
2279 : : }
2280 : :
2281 : : /* Namespaces are constructed on demand, so simply request it. */
2282 : 76000 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2283 [ - + ]: 76000 : if (ns == NULL) {
2284 : 0 : return -ENOMEM;
2285 : : }
2286 : :
2287 : 76000 : ns->active = true;
2288 : :
2289 : 76000 : return 0;
2290 : : }
2291 : :
2292 : : static void
2293 : 2643 : nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list,
2294 : : size_t max_entries)
2295 : : {
2296 : 2643 : uint32_t active_ns_count = 0;
2297 : : size_t i;
2298 : : uint32_t nsid;
2299 : : struct spdk_nvme_ns *ns, *tmp_ns;
2300 : : int rc;
2301 : :
2302 : : /* First, remove namespaces that no longer exist */
2303 [ + + + - ]: 95019 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
2304 : 92376 : nsid = new_ns_list[0];
2305 : 92376 : active_ns_count = 0;
2306 [ + + ]: 21285093 : while (nsid != 0) {
2307 [ + + ]: 21220748 : if (nsid == ns->id) {
2308 : 28034 : break;
2309 : : }
2310 : :
2311 : 21192720 : nsid = new_ns_list[active_ns_count++];
2312 : : }
2313 : :
2314 [ + + ]: 92376 : if (nsid != ns->id) {
2315 : : /* Did not find this namespace id in the new list. */
2316 [ - + - + : 64342 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id);
- - - - ]
2317 : 64342 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
2318 : : }
2319 : : }
2320 : :
2321 : : /* Next, add new namespaces */
2322 : 2643 : active_ns_count = 0;
2323 [ + - ]: 78643 : for (i = 0; i < max_entries; i++) {
2324 : 78643 : nsid = new_ns_list[active_ns_count];
2325 : :
2326 [ + + ]: 78643 : if (nsid == 0) {
2327 : 2643 : break;
2328 : : }
2329 : :
2330 : : /* If the namespace already exists, this will not construct it a second time. */
2331 : 76000 : rc = nvme_ctrlr_construct_namespace(ctrlr, nsid);
2332 [ - + ]: 76000 : if (rc != 0) {
2333 : : /* We can't easily handle a failure here. But just move on. */
2334 : 0 : assert(false);
2335 : : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n");
2336 : : continue;
2337 : : }
2338 : :
2339 : 76000 : active_ns_count++;
2340 : : }
2341 : :
2342 : 2643 : ctrlr->active_ns_count = active_ns_count;
2343 : 2643 : }
2344 : :
2345 : : static void
2346 : 2554 : nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2347 : : {
2348 : 2554 : struct nvme_active_ns_ctx *ctx = arg;
2349 : 2554 : uint32_t *new_ns_list = NULL;
2350 : :
2351 [ + + - + ]: 2554 : if (spdk_nvme_cpl_is_error(cpl)) {
2352 : 6 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2353 : 6 : goto out;
2354 : : }
2355 : :
2356 : 2548 : ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1];
2357 [ + + ]: 2548 : if (ctx->next_nsid == 0) {
2358 : 2518 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2359 : 2518 : goto out;
2360 : : }
2361 : :
2362 : 30 : ctx->page_count++;
2363 : 30 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2364 : 30 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2365 : 30 : ctx->ctrlr->page_size);
2366 [ - + ]: 30 : if (!new_ns_list) {
2367 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2368 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2369 : 0 : goto out;
2370 : : }
2371 : :
2372 : 30 : ctx->new_ns_list = new_ns_list;
2373 : 30 : nvme_ctrlr_identify_active_ns_async(ctx);
2374 : 30 : return;
2375 : :
2376 : 2524 : out:
2377 [ + + ]: 2524 : if (ctx->deleter) {
2378 : 2332 : ctx->deleter(ctx);
2379 : : }
2380 : : }
2381 : :
2382 : : static void
2383 : 2679 : nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx)
2384 : : {
2385 : 2679 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2386 : : uint32_t i;
2387 : : int rc;
2388 : :
2389 [ + + ]: 2679 : if (ctrlr->cdata.nn == 0) {
2390 : 96 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2391 : 96 : goto out;
2392 : : }
2393 : :
2394 [ - + ]: 2583 : assert(ctx->new_ns_list != NULL);
2395 : :
2396 : : /*
2397 : : * If controller doesn't support active ns list CNS 0x02 dummy up
2398 : : * an active ns list, i.e. all namespaces report as active
2399 : : */
2400 [ + + - + ]: 2583 : if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) {
2401 : : uint32_t *new_ns_list;
2402 : :
2403 : : /*
2404 : : * Active NS list must always end with zero element.
2405 : : * So, we allocate for cdata.nn+1.
2406 : : */
2407 : 29 : ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1,
2408 : : sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0]));
2409 : 29 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2410 : 29 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2411 : 29 : ctx->ctrlr->page_size);
2412 [ - + ]: 29 : if (!new_ns_list) {
2413 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2414 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2415 : 0 : goto out;
2416 : : }
2417 : :
2418 : 29 : ctx->new_ns_list = new_ns_list;
2419 : 29 : ctx->new_ns_list[ctrlr->cdata.nn] = 0;
2420 [ + + ]: 24556 : for (i = 0; i < ctrlr->cdata.nn; i++) {
2421 : 24527 : ctx->new_ns_list[i] = i + 1;
2422 : : }
2423 : :
2424 : 29 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2425 : 29 : goto out;
2426 : : }
2427 : :
2428 : 2554 : ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING;
2429 : 2554 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0,
2430 : 2554 : &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list),
2431 : : nvme_ctrlr_identify_active_ns_async_done, ctx);
2432 [ - + ]: 2554 : if (rc != 0) {
2433 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2434 : 0 : goto out;
2435 : : }
2436 : :
2437 : 2554 : return;
2438 : :
2439 : 125 : out:
2440 [ + + ]: 125 : if (ctx->deleter) {
2441 : 95 : ctx->deleter(ctx);
2442 : : }
2443 : : }
2444 : :
2445 : : static void
2446 : 2427 : _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx)
2447 : : {
2448 : 2427 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2449 : : struct spdk_nvme_ns *ns;
2450 : :
2451 [ - + ]: 2427 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2452 : 0 : nvme_active_ns_ctx_destroy(ctx);
2453 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2454 : 0 : return;
2455 : : }
2456 : :
2457 [ - + ]: 2427 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2458 : :
2459 [ + + ]: 2592 : RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) {
2460 : 165 : nvme_ns_free_iocs_specific_data(ns);
2461 : : }
2462 : :
2463 : 2427 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2464 : 2427 : nvme_active_ns_ctx_destroy(ctx);
2465 : 2427 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms);
2466 : : }
2467 : :
2468 : : static void
2469 : 2427 : _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2470 : : {
2471 : : struct nvme_active_ns_ctx *ctx;
2472 : :
2473 : 2427 : ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter);
2474 [ - + ]: 2427 : if (!ctx) {
2475 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2476 : 0 : return;
2477 : : }
2478 : :
2479 : 2427 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS,
2480 : 2427 : ctrlr->opts.admin_timeout_ms);
2481 : 2427 : nvme_ctrlr_identify_active_ns_async(ctx);
2482 : : }
2483 : :
2484 : : int
2485 : 222 : nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2486 : : {
2487 : : struct nvme_active_ns_ctx *ctx;
2488 : : int rc;
2489 : :
2490 : 222 : ctx = nvme_active_ns_ctx_create(ctrlr, NULL);
2491 [ - + ]: 222 : if (!ctx) {
2492 : 0 : return -ENOMEM;
2493 : : }
2494 : :
2495 : 222 : nvme_ctrlr_identify_active_ns_async(ctx);
2496 [ + + ]: 153771 : while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) {
2497 : 153549 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
2498 [ - + ]: 153549 : if (rc < 0) {
2499 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2500 : 0 : break;
2501 : : }
2502 : : }
2503 : :
2504 [ + + ]: 222 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2505 : 6 : nvme_active_ns_ctx_destroy(ctx);
2506 : 6 : return -ENXIO;
2507 : : }
2508 : :
2509 [ - + ]: 216 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2510 : 216 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2511 : 216 : nvme_active_ns_ctx_destroy(ctx);
2512 : :
2513 : 216 : return 0;
2514 : : }
2515 : :
2516 : : static void
2517 : 2112 : nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2518 : : {
2519 : 2112 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2520 : 2112 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2521 : : uint32_t nsid;
2522 : : int rc;
2523 : :
2524 [ + - - + ]: 2112 : if (spdk_nvme_cpl_is_error(cpl)) {
2525 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2526 : 0 : return;
2527 : : }
2528 : :
2529 : 2112 : nvme_ns_set_identify_data(ns);
2530 : :
2531 : : /* move on to the next active NS */
2532 : 2112 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2533 : 2112 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2534 [ + + ]: 2112 : if (ns == NULL) {
2535 : 1846 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2536 : 1846 : ctrlr->opts.admin_timeout_ms);
2537 : 1846 : return;
2538 : : }
2539 : 266 : ns->ctrlr = ctrlr;
2540 : 266 : ns->id = nsid;
2541 : :
2542 : 266 : rc = nvme_ctrlr_identify_ns_async(ns);
2543 [ - + ]: 266 : if (rc) {
2544 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2545 : : }
2546 : : }
2547 : :
2548 : : static int
2549 : 2112 : nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns)
2550 : : {
2551 : 2112 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2552 : : struct spdk_nvme_ns_data *nsdata;
2553 : :
2554 : 2112 : nsdata = &ns->nsdata;
2555 : :
2556 : 2112 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS,
2557 : 2112 : ctrlr->opts.admin_timeout_ms);
2558 : 2112 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0,
2559 : : nsdata, sizeof(*nsdata),
2560 : : nvme_ctrlr_identify_ns_async_done, ns);
2561 : : }
2562 : :
2563 : : static int
2564 : 2367 : nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2565 : : {
2566 : : uint32_t nsid;
2567 : : struct spdk_nvme_ns *ns;
2568 : : int rc;
2569 : :
2570 : 2367 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2571 : 2367 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2572 [ + + ]: 2367 : if (ns == NULL) {
2573 : : /* No active NS, move on to the next state */
2574 : 521 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2575 : 521 : ctrlr->opts.admin_timeout_ms);
2576 : 521 : return 0;
2577 : : }
2578 : :
2579 : 1846 : ns->ctrlr = ctrlr;
2580 : 1846 : ns->id = nsid;
2581 : :
2582 : 1846 : rc = nvme_ctrlr_identify_ns_async(ns);
2583 [ - + ]: 1846 : if (rc) {
2584 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2585 : : }
2586 : :
2587 : 1846 : return rc;
2588 : : }
2589 : :
2590 : : static int
2591 : 1023 : nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
2592 : : {
2593 : : uint32_t nsid;
2594 : : struct spdk_nvme_ns *ns;
2595 : : int rc;
2596 : :
2597 [ + + ]: 1023 : if (!prev_nsid) {
2598 : 1009 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2599 : : } else {
2600 : : /* move on to the next active NS */
2601 : 14 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid);
2602 : : }
2603 : :
2604 : 1023 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2605 [ + + ]: 1023 : if (ns == NULL) {
2606 : : /* No first/next active NS, move on to the next state */
2607 : 8 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2608 : 8 : ctrlr->opts.admin_timeout_ms);
2609 : 8 : return 0;
2610 : : }
2611 : :
2612 : : /* loop until we find a ns which has (supported) iocs specific data */
2613 [ + + ]: 1195 : while (!nvme_ns_has_supported_iocs_specific_data(ns)) {
2614 : 1181 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2615 : 1181 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2616 [ + + ]: 1181 : if (ns == NULL) {
2617 : : /* no namespace with (supported) iocs specific data found */
2618 : 1001 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2619 : 1001 : ctrlr->opts.admin_timeout_ms);
2620 : 1001 : return 0;
2621 : : }
2622 : : }
2623 : :
2624 : 14 : rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns);
2625 [ + + ]: 14 : if (rc) {
2626 : 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2627 : : }
2628 : :
2629 : 14 : return rc;
2630 : : }
2631 : :
2632 : : static void
2633 : 2 : nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2634 : : {
2635 : 2 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2636 : 2 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2637 : :
2638 [ + - - + ]: 2 : if (spdk_nvme_cpl_is_error(cpl)) {
2639 : 0 : nvme_ns_free_zns_specific_data(ns);
2640 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2641 : 0 : return;
2642 : : }
2643 : :
2644 : 2 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2645 : : }
2646 : :
2647 : : static int
2648 : 14 : nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns)
2649 : : {
2650 : 14 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2651 : : int rc;
2652 : :
2653 [ + - ]: 14 : switch (ns->csi) {
2654 : 14 : case SPDK_NVME_CSI_ZNS:
2655 : 14 : break;
2656 : 0 : default:
2657 : : /*
2658 : : * This switch must handle all cases for which
2659 : : * nvme_ns_has_supported_iocs_specific_data() returns true,
2660 : : * other cases should never happen.
2661 : : */
2662 : 0 : assert(0);
2663 : : }
2664 : :
2665 [ - + ]: 14 : assert(!ns->nsdata_zns);
2666 : 14 : ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2667 : : SPDK_MALLOC_SHARE);
2668 [ - + ]: 14 : if (!ns->nsdata_zns) {
2669 : 0 : return -ENOMEM;
2670 : : }
2671 : :
2672 : 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2673 : 14 : ctrlr->opts.admin_timeout_ms);
2674 : 14 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
2675 : 14 : ns->nsdata_zns, sizeof(*ns->nsdata_zns),
2676 : : nvme_ctrlr_identify_ns_zns_specific_async_done, ns);
2677 [ + + ]: 14 : if (rc) {
2678 : 6 : nvme_ns_free_zns_specific_data(ns);
2679 : : }
2680 : :
2681 : 14 : return rc;
2682 : : }
2683 : :
2684 : : static int
2685 : 2367 : nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2686 : : {
2687 [ + + ]: 2367 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2688 : : /* Multi IOCS not supported/enabled, move on to the next state */
2689 : 1370 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2690 : 1370 : ctrlr->opts.admin_timeout_ms);
2691 : 1370 : return 0;
2692 : : }
2693 : :
2694 : 997 : return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0);
2695 : : }
2696 : :
2697 : : static void
2698 : 1919 : nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2699 : : {
2700 : 1919 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2701 : 1919 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2702 : : uint32_t nsid;
2703 : : int rc;
2704 : :
2705 [ + + - + ]: 1919 : if (spdk_nvme_cpl_is_error(cpl)) {
2706 : : /*
2707 : : * Many controllers claim to be compatible with NVMe 1.3, however,
2708 : : * they do not implement NS ID Desc List. Therefore, instead of setting
2709 : : * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion
2710 : : * error and move on to the next state.
2711 : : *
2712 : : * The proper way is to create a new quirk for controllers that violate
2713 : : * the NVMe 1.3 spec by not supporting NS ID Desc List.
2714 : : * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since
2715 : : * it is too generic and was added in order to handle controllers that
2716 : : * violate the NVMe 1.1 spec by not supporting ACTIVE LIST).
2717 : : */
2718 : 24 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2719 : 24 : ctrlr->opts.admin_timeout_ms);
2720 : 24 : return;
2721 : : }
2722 : :
2723 : 1895 : nvme_ns_set_id_desc_list_data(ns);
2724 : :
2725 : : /* move on to the next active NS */
2726 : 1895 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2727 : 1895 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2728 [ + + ]: 1895 : if (ns == NULL) {
2729 : 1695 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2730 : 1695 : ctrlr->opts.admin_timeout_ms);
2731 : 1695 : return;
2732 : : }
2733 : :
2734 : 200 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2735 [ - + ]: 200 : if (rc) {
2736 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2737 : : }
2738 : : }
2739 : :
2740 : : static int
2741 : 1919 : nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns)
2742 : : {
2743 : 1919 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2744 : :
2745 [ - + ]: 1919 : memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list));
2746 : :
2747 : 1919 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS,
2748 : 1919 : ctrlr->opts.admin_timeout_ms);
2749 : 2162 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST,
2750 : 1919 : 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list),
2751 : : nvme_ctrlr_identify_id_desc_async_done, ns);
2752 : : }
2753 : :
2754 : : static int
2755 : 2367 : nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2756 : : {
2757 : : uint32_t nsid;
2758 : : struct spdk_nvme_ns *ns;
2759 : : int rc;
2760 : :
2761 [ + + ]: 2367 : if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) &&
2762 [ - + ]: 177 : !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) ||
2763 [ - + ]: 2190 : (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2764 [ - + - + : 177 : NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n");
- - - - ]
2765 : : /* NS ID Desc List not supported, move on to the next state */
2766 : 177 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2767 : 177 : ctrlr->opts.admin_timeout_ms);
2768 : 177 : return 0;
2769 : : }
2770 : :
2771 : 2190 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2772 : 2190 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2773 [ + + ]: 2190 : if (ns == NULL) {
2774 : : /* No active NS, move on to the next state */
2775 : 471 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2776 : 471 : ctrlr->opts.admin_timeout_ms);
2777 : 471 : return 0;
2778 : : }
2779 : :
2780 : 1719 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2781 [ - + ]: 1719 : if (rc) {
2782 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2783 : : }
2784 : :
2785 : 1719 : return rc;
2786 : : }
2787 : :
2788 : : static void
2789 : 2397 : nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr)
2790 : : {
2791 [ + + ]: 2397 : if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
2792 [ - + ]: 1464 : if (ctrlr->cdata.nvmf_specific.ioccsz < 4) {
2793 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n",
2794 : : ctrlr->cdata.nvmf_specific.ioccsz);
2795 : 0 : ctrlr->cdata.nvmf_specific.ioccsz = 4;
2796 : 0 : assert(0);
2797 : : }
2798 : 1464 : ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd);
2799 : 1464 : ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff;
2800 : : }
2801 : 2397 : }
2802 : :
2803 : : static void
2804 : 2397 : nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl)
2805 : : {
2806 : : uint32_t cq_allocated, sq_allocated, min_allocated, i;
2807 : 2397 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2808 : :
2809 [ + - - + ]: 2397 : if (spdk_nvme_cpl_is_error(cpl)) {
2810 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n");
2811 : 0 : ctrlr->opts.num_io_queues = 0;
2812 : : } else {
2813 : : /*
2814 : : * Data in cdw0 is 0-based.
2815 : : * Lower 16-bits indicate number of submission queues allocated.
2816 : : * Upper 16-bits indicate number of completion queues allocated.
2817 : : */
2818 : 2397 : sq_allocated = (cpl->cdw0 & 0xFFFF) + 1;
2819 : 2397 : cq_allocated = (cpl->cdw0 >> 16) + 1;
2820 : :
2821 : : /*
2822 : : * For 1:1 queue mapping, set number of allocated queues to be minimum of
2823 : : * submission and completion queues.
2824 : : */
2825 : 2397 : min_allocated = spdk_min(sq_allocated, cq_allocated);
2826 : :
2827 : : /* Set number of queues to be minimum of requested and actually allocated. */
2828 : 2397 : ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues);
2829 : : }
2830 : :
2831 : 2397 : ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
2832 [ - + ]: 2397 : if (ctrlr->free_io_qids == NULL) {
2833 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2834 : 0 : return;
2835 : : }
2836 : :
2837 : : /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */
2838 [ + + ]: 249787 : for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
2839 : 247390 : spdk_nvme_ctrlr_free_qid(ctrlr, i);
2840 : : }
2841 : :
2842 : 2397 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS,
2843 : 2397 : ctrlr->opts.admin_timeout_ms);
2844 : : }
2845 : :
2846 : : static int
2847 : 2397 : nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr)
2848 : : {
2849 : : int rc;
2850 : :
2851 [ - + ]: 2397 : if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
2852 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n",
2853 : : ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
2854 : 0 : ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
2855 [ + + ]: 2397 : } else if (ctrlr->opts.num_io_queues < 1) {
2856 [ + - - + ]: 78 : NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n");
2857 : 78 : ctrlr->opts.num_io_queues = 1;
2858 : : }
2859 : :
2860 : 2397 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES,
2861 : 2397 : ctrlr->opts.admin_timeout_ms);
2862 : :
2863 : 2397 : rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
2864 : : nvme_ctrlr_set_num_queues_done, ctrlr);
2865 [ - + ]: 2397 : if (rc != 0) {
2866 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2867 : 0 : return rc;
2868 : : }
2869 : :
2870 : 2397 : return 0;
2871 : : }
2872 : :
2873 : : static void
2874 : 1619 : nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl)
2875 : : {
2876 : : uint32_t keep_alive_interval_us;
2877 : 1619 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2878 : :
2879 [ + + - + ]: 1619 : if (spdk_nvme_cpl_is_error(cpl)) {
2880 [ + - ]: 12 : if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) &&
2881 [ + + ]: 12 : (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) {
2882 [ - + - + : 6 : NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n");
- - - - ]
2883 : : } else {
2884 [ + - - + ]: 6 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n",
2885 : : cpl->status.sc, cpl->status.sct);
2886 : 6 : ctrlr->opts.keep_alive_timeout_ms = 0;
2887 : 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2888 : 6 : return;
2889 : : }
2890 : : } else {
2891 [ + + ]: 1607 : if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) {
2892 [ - + + + : 41 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n",
+ - - + ]
2893 : : cpl->cdw0);
2894 : : }
2895 : :
2896 : 1607 : ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0;
2897 : : }
2898 : :
2899 [ + + ]: 1613 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2900 : 35 : ctrlr->keep_alive_interval_ticks = 0;
2901 : : } else {
2902 : 1578 : keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2;
2903 : :
2904 [ - + + + : 1578 : NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us);
+ + + - ]
2905 : :
2906 : 1578 : ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) /
2907 : : UINT64_C(1000000);
2908 : :
2909 : : /* Schedule the first Keep Alive to be sent as soon as possible. */
2910 : 1578 : ctrlr->next_keep_alive_tick = spdk_get_ticks();
2911 : : }
2912 : :
2913 [ + + ]: 1613 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2914 : 126 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2915 : : } else {
2916 : 1487 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2917 : 1487 : ctrlr->opts.admin_timeout_ms);
2918 : : }
2919 : : }
2920 : :
2921 : : static int
2922 : 2541 : nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr)
2923 : : {
2924 : : int rc;
2925 : :
2926 [ + + ]: 2541 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2927 [ - + ]: 200 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2928 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2929 : : } else {
2930 : 200 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2931 : 200 : ctrlr->opts.admin_timeout_ms);
2932 : : }
2933 : 200 : return 0;
2934 : : }
2935 : :
2936 : : /* Note: Discovery controller identify data does not populate KAS according to spec. */
2937 [ + + + + ]: 2341 : if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) {
2938 [ - + - + : 722 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n");
- - - - ]
2939 : 722 : ctrlr->opts.keep_alive_timeout_ms = 0;
2940 : 722 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2941 : 722 : ctrlr->opts.admin_timeout_ms);
2942 : 722 : return 0;
2943 : : }
2944 : :
2945 : 1619 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT,
2946 : 1619 : ctrlr->opts.admin_timeout_ms);
2947 : :
2948 : : /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */
2949 : 1619 : rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0,
2950 : : nvme_ctrlr_set_keep_alive_timeout_done, ctrlr);
2951 [ - + ]: 1619 : if (rc != 0) {
2952 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc);
2953 : 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
2954 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2955 : 0 : return rc;
2956 : : }
2957 : :
2958 : 1619 : return 0;
2959 : : }
2960 : :
2961 : : static void
2962 : 0 : nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl)
2963 : : {
2964 : 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2965 : :
2966 [ # # # # ]: 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2967 : : /*
2968 : : * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature
2969 : : * is optional.
2970 : : */
2971 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n",
2972 : : cpl->status.sc, cpl->status.sct);
2973 : : } else {
2974 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n");
# # # # ]
2975 : : }
2976 : :
2977 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
2978 : 0 : }
2979 : :
2980 : : static int
2981 : 2367 : nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr)
2982 : : {
2983 : : uint8_t *host_id;
2984 : : uint32_t host_id_size;
2985 : : int rc;
2986 : :
2987 [ + + ]: 2367 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
2988 : : /*
2989 : : * NVMe-oF sends the host ID during Connect and doesn't allow
2990 : : * Set Features - Host Identifier after Connect, so we don't need to do anything here.
2991 : : */
2992 [ - + + + : 1559 : NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n");
+ + + + ]
2993 : 1559 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
2994 : 1559 : return 0;
2995 : : }
2996 : :
2997 [ - + ]: 808 : if (ctrlr->cdata.ctratt.bits.host_id_exhid_supported) {
2998 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n");
# # # # ]
2999 : 0 : host_id = ctrlr->opts.extended_host_id;
3000 : 0 : host_id_size = sizeof(ctrlr->opts.extended_host_id);
3001 : : } else {
3002 [ - + - + : 808 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n");
- - - - ]
3003 : 808 : host_id = ctrlr->opts.host_id;
3004 : 808 : host_id_size = sizeof(ctrlr->opts.host_id);
3005 : : }
3006 : :
3007 : : /* If the user specified an all-zeroes host identifier, don't send the command. */
3008 [ + - ]: 808 : if (spdk_mem_all_zero(host_id, host_id_size)) {
3009 [ - + - + : 808 : NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n");
- - - - ]
3010 : 808 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
3011 : 808 : return 0;
3012 : : }
3013 : :
3014 [ # # # # ]: 0 : SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size);
3015 : :
3016 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID,
3017 : 0 : ctrlr->opts.admin_timeout_ms);
3018 : :
3019 : 0 : rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr);
3020 [ # # ]: 0 : if (rc != 0) {
3021 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc);
3022 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3023 : 0 : return rc;
3024 : : }
3025 : :
3026 : 0 : return 0;
3027 : : }
3028 : :
3029 : : void
3030 : 120 : nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr)
3031 : : {
3032 : : uint32_t nsid;
3033 : : struct spdk_nvme_ns *ns;
3034 : :
3035 [ + + ]: 150 : for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
3036 [ + + ]: 350 : nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) {
3037 : 238 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
3038 : 238 : nvme_ns_construct(ns, nsid, ctrlr);
3039 : : }
3040 : 120 : }
3041 : :
3042 : : static int
3043 : 120 : nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr)
3044 : : {
3045 : : struct nvme_completion_poll_status *status;
3046 : 120 : int rc = -ENOMEM;
3047 : 120 : char *buffer = NULL;
3048 : : uint32_t nsid;
3049 : 120 : size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t));
3050 : :
3051 [ - + ]: 120 : if (ctrlr->opts.disable_read_changed_ns_list_log_page) {
3052 : 0 : return 0;
3053 : : }
3054 : :
3055 : 120 : buffer = spdk_dma_zmalloc(buf_size, 4096, NULL);
3056 [ - + ]: 120 : if (!buffer) {
3057 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting "
3058 : : "changed ns log.\n");
3059 : 0 : return rc;
3060 : : }
3061 : :
3062 : 120 : status = calloc(1, sizeof(*status));
3063 [ - + ]: 120 : if (!status) {
3064 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
3065 : 0 : goto free_buffer;
3066 : : }
3067 : :
3068 : 120 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr,
3069 : : SPDK_NVME_LOG_CHANGED_NS_LIST,
3070 : : SPDK_NVME_GLOBAL_NS_TAG,
3071 : : buffer, buf_size, 0,
3072 : : nvme_completion_poll_cb, status);
3073 : :
3074 [ - + ]: 120 : if (rc) {
3075 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc);
3076 : 0 : free(status);
3077 : 0 : goto free_buffer;
3078 : : }
3079 : :
3080 : 120 : rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status,
3081 : 120 : ctrlr->opts.admin_timeout_ms * 1000);
3082 [ + + + - ]: 120 : if (!status->timed_out) {
3083 : 120 : free(status);
3084 : : }
3085 : :
3086 [ - + ]: 120 : if (rc) {
3087 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc);
3088 : 0 : goto free_buffer;
3089 : : }
3090 : :
3091 : : /* only check the case of overflow. */
3092 : 120 : nsid = from_le32(buffer);
3093 [ + - ]: 120 : if (nsid == 0xffffffffu) {
3094 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n");
3095 : : }
3096 : :
3097 : 120 : free_buffer:
3098 : 120 : spdk_dma_free(buffer);
3099 : 120 : return rc;
3100 : : }
3101 : :
3102 : : static void
3103 : 299 : nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr,
3104 : : const struct spdk_nvme_cpl *cpl)
3105 : : {
3106 : : union spdk_nvme_async_event_completion event;
3107 : : struct spdk_nvme_ctrlr_process *active_proc;
3108 : : int rc;
3109 : :
3110 : 299 : event.raw = cpl->cdw0;
3111 : :
3112 [ + + ]: 299 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3113 [ + + ]: 240 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) {
3114 : 120 : nvme_ctrlr_clear_changed_ns_log(ctrlr);
3115 : :
3116 : 120 : rc = nvme_ctrlr_identify_active_ns(ctrlr);
3117 [ - + ]: 120 : if (rc) {
3118 : 0 : return;
3119 : : }
3120 : 120 : nvme_ctrlr_update_namespaces(ctrlr);
3121 : 120 : nvme_io_msg_ctrlr_update(ctrlr);
3122 : : }
3123 : :
3124 [ + + ]: 299 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3125 [ + + ]: 240 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) {
3126 [ + + + + ]: 106 : if (!ctrlr->opts.disable_read_ana_log_page) {
3127 : 6 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
3128 [ - + ]: 6 : if (rc) {
3129 : 0 : return;
3130 : : }
3131 : 6 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
3132 : : ctrlr);
3133 : : }
3134 : : }
3135 : :
3136 : 299 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3137 [ + - + + ]: 299 : if (active_proc && active_proc->aer_cb_fn) {
3138 : 178 : active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl);
3139 : : }
3140 : : }
3141 : :
3142 : : static void
3143 : 849 : nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr,
3144 : : const struct spdk_nvme_cpl *cpl)
3145 : : {
3146 : : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event;
3147 : : struct spdk_nvme_ctrlr_process *proc;
3148 : :
3149 : : /* Add async event to each process objects event list */
3150 [ + + ]: 1733 : TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) {
3151 : : /* Must be shared memory so other processes can access */
3152 : 884 : nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3153 [ - + ]: 884 : if (!nvme_event) {
3154 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n");
3155 : 0 : return;
3156 : : }
3157 : 884 : nvme_event->cpl = *cpl;
3158 : :
3159 : 884 : STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link);
3160 : : }
3161 : : }
3162 : :
3163 : : static void
3164 : 33999397 : nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr)
3165 : : {
3166 : : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event, *nvme_event_tmp;
3167 : : struct spdk_nvme_ctrlr_process *active_proc;
3168 : :
3169 : 33999397 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3170 : :
3171 [ + + ]: 33999701 : STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) {
3172 [ + - + + : 299 : STAILQ_REMOVE(&active_proc->async_events, nvme_event,
- - - - ]
3173 : : spdk_nvme_ctrlr_aer_completion_list, link);
3174 : 299 : nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl);
3175 : 299 : spdk_free(nvme_event);
3176 : :
3177 : : }
3178 : 33999397 : }
3179 : :
3180 : : static void
3181 : 10143 : nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
3182 : : {
3183 : 10143 : struct nvme_async_event_request *aer = arg;
3184 : 10143 : struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
3185 : :
3186 [ + - ]: 10143 : if (cpl->status.sct == SPDK_NVME_SCT_GENERIC &&
3187 [ + + ]: 10143 : cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
3188 : : /*
3189 : : * This is simulated when controller is being shut down, to
3190 : : * effectively abort outstanding asynchronous event requests
3191 : : * and make sure all memory is freed. Do not repost the
3192 : : * request in this case.
3193 : : */
3194 : 9294 : return;
3195 : : }
3196 : :
3197 [ - + ]: 849 : if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
3198 [ # # ]: 0 : cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) {
3199 : : /*
3200 : : * SPDK will only send as many AERs as the device says it supports,
3201 : : * so this status code indicates an out-of-spec device. Do not repost
3202 : : * the request in this case.
3203 : : */
3204 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n"
3205 : : "handling. Do not repost this AER.\n");
3206 : 0 : return;
3207 : : }
3208 : :
3209 : : /* Add the events to the list */
3210 : 849 : nvme_ctrlr_queue_async_event(ctrlr, cpl);
3211 : :
3212 : : /* If the ctrlr was removed or in the destruct state, we should not send aer again */
3213 [ + + + + : 849 : if (ctrlr->is_removed || ctrlr->is_destructed) {
- + + + ]
3214 : 230 : return;
3215 : : }
3216 : :
3217 : : /*
3218 : : * Repost another asynchronous event request to replace the one
3219 : : * that just completed.
3220 : : */
3221 [ - + ]: 619 : if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
3222 : : /*
3223 : : * We can't do anything to recover from a failure here,
3224 : : * so just print a warning message and leave the AER unsubmitted.
3225 : : */
3226 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n");
3227 : : }
3228 : : }
3229 : :
3230 : : static int
3231 : 10357 : nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
3232 : : struct nvme_async_event_request *aer)
3233 : : {
3234 : : struct nvme_request *req;
3235 : :
3236 : 10357 : aer->ctrlr = ctrlr;
3237 : 10357 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer);
3238 : 10357 : aer->req = req;
3239 [ - + ]: 10357 : if (req == NULL) {
3240 : 0 : return -1;
3241 : : }
3242 : :
3243 : 10357 : req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
3244 : 10357 : return nvme_ctrlr_submit_admin_request(ctrlr, req);
3245 : : }
3246 : :
3247 : : static void
3248 : 2523 : nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl)
3249 : : {
3250 : : struct nvme_async_event_request *aer;
3251 : : int rc;
3252 : : uint32_t i;
3253 : 2523 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3254 : :
3255 [ + - - + ]: 2523 : if (spdk_nvme_cpl_is_error(cpl)) {
3256 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n");
3257 : 0 : ctrlr->num_aers = 0;
3258 : : } else {
3259 : : /* aerl is a zero-based value, so we need to add 1 here. */
3260 [ + - ]: 2523 : ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
3261 : : }
3262 : :
3263 [ + + ]: 12261 : for (i = 0; i < ctrlr->num_aers; i++) {
3264 : 9738 : aer = &ctrlr->aer[i];
3265 : 9738 : rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
3266 [ - + ]: 9738 : if (rc) {
3267 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n");
3268 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3269 : 0 : return;
3270 : : }
3271 : : }
3272 : 2523 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms);
3273 : : }
3274 : :
3275 : : static int
3276 : 2523 : nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
3277 : : {
3278 : : union spdk_nvme_feat_async_event_configuration config;
3279 : : int rc;
3280 : :
3281 : 2523 : config.raw = 0;
3282 : :
3283 [ + + ]: 2523 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3284 : 126 : config.bits.discovery_log_change_notice = 1;
3285 : : } else {
3286 : 2397 : config.bits.crit_warn.bits.available_spare = 1;
3287 : 2397 : config.bits.crit_warn.bits.temperature = 1;
3288 : 2397 : config.bits.crit_warn.bits.device_reliability = 1;
3289 : 2397 : config.bits.crit_warn.bits.read_only = 1;
3290 : 2397 : config.bits.crit_warn.bits.volatile_memory_backup = 1;
3291 : :
3292 [ + + ]: 2397 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) {
3293 [ + + ]: 2302 : if (ctrlr->cdata.oaes.ns_attribute_notices) {
3294 : 2177 : config.bits.ns_attr_notice = 1;
3295 : : }
3296 [ + + ]: 2302 : if (ctrlr->cdata.oaes.fw_activation_notices) {
3297 : 123 : config.bits.fw_activation_notice = 1;
3298 : : }
3299 [ + + ]: 2302 : if (ctrlr->cdata.oaes.ana_change_notices) {
3300 : 331 : config.bits.ana_change_notice = 1;
3301 : : }
3302 : : }
3303 [ + + + + ]: 2397 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) {
3304 : 23 : config.bits.telemetry_log_notice = 1;
3305 : : }
3306 : : }
3307 : :
3308 : 2523 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER,
3309 : 2523 : ctrlr->opts.admin_timeout_ms);
3310 : :
3311 : 2523 : rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config,
3312 : : nvme_ctrlr_configure_aer_done,
3313 : : ctrlr);
3314 [ - + ]: 2523 : if (rc != 0) {
3315 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3316 : 0 : return rc;
3317 : : }
3318 : :
3319 : 2523 : return 0;
3320 : : }
3321 : :
3322 : : struct spdk_nvme_ctrlr_process *
3323 : 103602889 : nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid)
3324 : : {
3325 : : struct spdk_nvme_ctrlr_process *active_proc;
3326 : :
3327 [ + + ]: 187753254 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3328 [ + + ]: 187750296 : if (active_proc->pid == pid) {
3329 : 103599931 : return active_proc;
3330 : : }
3331 : : }
3332 : :
3333 : 2950 : return NULL;
3334 : : }
3335 : :
3336 : : struct spdk_nvme_ctrlr_process *
3337 : 103600013 : nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr)
3338 : : {
3339 : 103600013 : return nvme_ctrlr_get_process(ctrlr, getpid());
3340 : : }
3341 : :
3342 : : /**
3343 : : * This function will be called when a process is using the controller.
3344 : : * 1. For the primary process, it is called when constructing the controller.
3345 : : * 2. For the secondary process, it is called at probing the controller.
3346 : : * Note: will check whether the process is already added for the same process.
3347 : : */
3348 : : int
3349 : 2637 : nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
3350 : : {
3351 : : struct spdk_nvme_ctrlr_process *ctrlr_proc;
3352 : 2637 : pid_t pid = getpid();
3353 : :
3354 : : /* Check whether the process is already added or not */
3355 [ + + ]: 2637 : if (nvme_ctrlr_get_process(ctrlr, pid)) {
3356 : 41 : return 0;
3357 : : }
3358 : :
3359 : : /* Initialize the per process properties for this ctrlr */
3360 : 2596 : ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process),
3361 : : 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3362 [ - + ]: 2596 : if (ctrlr_proc == NULL) {
3363 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n");
3364 : :
3365 : 0 : return -1;
3366 : : }
3367 : :
3368 : 2596 : ctrlr_proc->is_primary = spdk_process_is_primary();
3369 : 2596 : ctrlr_proc->pid = pid;
3370 : 2596 : STAILQ_INIT(&ctrlr_proc->active_reqs);
3371 : 2596 : ctrlr_proc->devhandle = devhandle;
3372 : 2596 : ctrlr_proc->ref = 0;
3373 : 2596 : TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs);
3374 : 2596 : STAILQ_INIT(&ctrlr_proc->async_events);
3375 : :
3376 : 2596 : TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq);
3377 : :
3378 : 2596 : return 0;
3379 : : }
3380 : :
3381 : : /**
3382 : : * This function will be called when the process detaches the controller.
3383 : : * Note: the ctrlr_lock must be held when calling this function.
3384 : : */
3385 : : static void
3386 : 231 : nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr,
3387 : : struct spdk_nvme_ctrlr_process *proc)
3388 : : {
3389 : : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3390 : :
3391 [ - + ]: 231 : assert(STAILQ_EMPTY(&proc->active_reqs));
3392 : :
3393 [ + + ]: 251 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3394 : 20 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3395 : : }
3396 : :
3397 [ + + ]: 231 : TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq);
3398 : :
3399 [ + - ]: 231 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
3400 : 231 : spdk_pci_device_detach(proc->devhandle);
3401 : : }
3402 : :
3403 : 231 : spdk_free(proc);
3404 : 231 : }
3405 : :
3406 : : /**
3407 : : * This function will be called when the process exited unexpectedly
3408 : : * in order to free any incomplete nvme request, allocated IO qpairs
3409 : : * and allocated memory.
3410 : : * Note: the ctrlr_lock must be held when calling this function.
3411 : : */
3412 : : static void
3413 : 9 : nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc)
3414 : : {
3415 : : struct nvme_request *req, *tmp_req;
3416 : : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3417 : : struct spdk_nvme_ctrlr_aer_completion_list *event;
3418 : :
3419 [ - + ]: 9 : STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
3420 [ # # # # : 0 : STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
# # # # ]
3421 : :
3422 [ # # ]: 0 : assert(req->pid == proc->pid);
3423 : 0 : nvme_cleanup_user_req(req);
3424 : 0 : nvme_free_request(req);
3425 : : }
3426 : :
3427 : : /* Remove async event from each process objects event list */
3428 [ - + ]: 9 : while (!STAILQ_EMPTY(&proc->async_events)) {
3429 : 0 : event = STAILQ_FIRST(&proc->async_events);
3430 [ # # ]: 0 : STAILQ_REMOVE_HEAD(&proc->async_events, link);
3431 : 0 : spdk_free(event);
3432 : : }
3433 : :
3434 [ - + ]: 9 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3435 [ # # ]: 0 : TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq);
3436 : :
3437 : : /*
3438 : : * The process may have been killed while some qpairs were in their
3439 : : * completion context. Clear that flag here to allow these IO
3440 : : * qpairs to be deleted.
3441 : : */
3442 : 0 : qpair->in_completion_context = 0;
3443 : :
3444 : 0 : qpair->no_deletion_notification_needed = 1;
3445 : :
3446 : 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3447 : : }
3448 : :
3449 : 9 : spdk_free(proc);
3450 : 9 : }
3451 : :
3452 : : /**
3453 : : * This function will be called when destructing the controller.
3454 : : * 1. There is no more admin request on this controller.
3455 : : * 2. Clean up any left resource allocation when its associated process is gone.
3456 : : */
3457 : : void
3458 : 2639 : nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr)
3459 : : {
3460 : : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3461 : :
3462 : : /* Free all the processes' properties and make sure no pending admin IOs */
3463 [ + + ]: 4991 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3464 [ - + ]: 2352 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3465 : :
3466 [ - + ]: 2352 : assert(STAILQ_EMPTY(&active_proc->active_reqs));
3467 : :
3468 : 2352 : spdk_free(active_proc);
3469 : : }
3470 : 2639 : }
3471 : :
3472 : : /**
3473 : : * This function will be called when any other process attaches or
3474 : : * detaches the controller in order to cleanup those unexpectedly
3475 : : * terminated processes.
3476 : : * Note: the ctrlr_lock must be held when calling this function.
3477 : : */
3478 : : static int
3479 : 7270 : nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr)
3480 : : {
3481 : : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3482 : 7270 : int active_proc_count = 0;
3483 : :
3484 [ + + ]: 15443 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3485 [ + + + - ]: 8173 : if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) {
3486 [ + - - + ]: 9 : NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid);
3487 : :
3488 [ + - ]: 9 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3489 : :
3490 : 9 : nvme_ctrlr_cleanup_process(active_proc);
3491 : : } else {
3492 : 8164 : active_proc_count++;
3493 : : }
3494 : : }
3495 : :
3496 : 7270 : return active_proc_count;
3497 : : }
3498 : :
3499 : : void
3500 : 2432 : nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr)
3501 : : {
3502 : : struct spdk_nvme_ctrlr_process *active_proc;
3503 : :
3504 : 2432 : nvme_ctrlr_lock(ctrlr);
3505 : :
3506 : 2432 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3507 : :
3508 : 2432 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3509 [ + - ]: 2432 : if (active_proc) {
3510 : 2432 : active_proc->ref++;
3511 : : }
3512 : :
3513 : 2432 : nvme_ctrlr_unlock(ctrlr);
3514 : 2432 : }
3515 : :
3516 : : void
3517 : 2419 : nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr)
3518 : : {
3519 : : struct spdk_nvme_ctrlr_process *active_proc;
3520 : : int proc_count;
3521 : :
3522 : 2419 : nvme_ctrlr_lock(ctrlr);
3523 : :
3524 : 2419 : proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr);
3525 : :
3526 : 2419 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3527 [ + - ]: 2419 : if (active_proc) {
3528 : 2419 : active_proc->ref--;
3529 [ - + ]: 2419 : assert(active_proc->ref >= 0);
3530 : :
3531 : : /*
3532 : : * The last active process will be removed at the end of
3533 : : * the destruction of the controller.
3534 : : */
3535 [ + - + + ]: 2419 : if (active_proc->ref == 0 && proc_count != 1) {
3536 : 225 : nvme_ctrlr_remove_process(ctrlr, active_proc);
3537 : : }
3538 : : }
3539 : :
3540 : 2419 : nvme_ctrlr_unlock(ctrlr);
3541 : 2419 : }
3542 : :
3543 : : int
3544 : 2419 : nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr)
3545 : : {
3546 : : struct spdk_nvme_ctrlr_process *active_proc;
3547 : 2419 : int ref = 0;
3548 : :
3549 : 2419 : nvme_ctrlr_lock(ctrlr);
3550 : :
3551 : 2419 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3552 : :
3553 [ + + ]: 5133 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3554 : 2714 : ref += active_proc->ref;
3555 : : }
3556 : :
3557 : 2419 : nvme_ctrlr_unlock(ctrlr);
3558 : :
3559 : 2419 : return ref;
3560 : : }
3561 : :
3562 : : /**
3563 : : * Get the PCI device handle which is only visible to its associated process.
3564 : : */
3565 : : struct spdk_pci_device *
3566 : 864 : nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr)
3567 : : {
3568 : : struct spdk_nvme_ctrlr_process *active_proc;
3569 : 864 : struct spdk_pci_device *devhandle = NULL;
3570 : :
3571 : 864 : nvme_ctrlr_lock(ctrlr);
3572 : :
3573 : 864 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3574 [ + - ]: 864 : if (active_proc) {
3575 : 864 : devhandle = active_proc->devhandle;
3576 : : }
3577 : :
3578 : 864 : nvme_ctrlr_unlock(ctrlr);
3579 : :
3580 : 864 : return devhandle;
3581 : : }
3582 : :
3583 : : static void
3584 : 2535 : nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3585 : : {
3586 : 2535 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3587 : :
3588 [ + - - + ]: 2535 : if (spdk_nvme_cpl_is_error(cpl)) {
3589 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n");
3590 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3591 : 0 : return;
3592 : : }
3593 : :
3594 [ - + ]: 2535 : assert(value <= UINT32_MAX);
3595 : 2535 : ctrlr->vs.raw = (uint32_t)value;
3596 : 2535 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE);
3597 : : }
3598 : :
3599 : : static void
3600 : 2535 : nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3601 : : {
3602 : 2535 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3603 : :
3604 [ + - - + ]: 2535 : if (spdk_nvme_cpl_is_error(cpl)) {
3605 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n");
3606 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3607 : 0 : return;
3608 : : }
3609 : :
3610 : 2535 : ctrlr->cap.raw = value;
3611 : 2535 : nvme_ctrlr_init_cap(ctrlr);
3612 : 2535 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
3613 : : }
3614 : :
3615 : : static void
3616 : 2627 : nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3617 : : {
3618 : 2627 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3619 : : enum nvme_ctrlr_state state;
3620 : :
3621 [ + - - + ]: 2627 : if (spdk_nvme_cpl_is_error(cpl)) {
3622 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3623 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3624 : 0 : return;
3625 : : }
3626 : :
3627 [ - + ]: 2627 : assert(value <= UINT32_MAX);
3628 : 2627 : ctrlr->process_init_cc.raw = (uint32_t)value;
3629 : :
3630 [ + + ]: 2627 : if (ctrlr->process_init_cc.bits.en) {
3631 [ - + - + : 698 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n");
- - - - ]
3632 : 698 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1;
3633 : : } else {
3634 : 1929 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0;
3635 : : }
3636 : :
3637 : 2627 : nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr));
3638 : : }
3639 : :
3640 : : static void
3641 : 698 : nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3642 : : {
3643 : 698 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3644 : :
3645 [ + - - + ]: 698 : if (spdk_nvme_cpl_is_error(cpl)) {
3646 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n");
3647 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3648 : 0 : return;
3649 : : }
3650 : :
3651 : : /*
3652 : : * Wait 2.5 seconds before accessing PCI registers.
3653 : : * Not using sleep() to avoid blocking other controller's initialization.
3654 : : */
3655 [ - + ]: 698 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
3656 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n");
# # # # ]
3657 : 0 : ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000);
3658 : : }
3659 : :
3660 : 698 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3661 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3662 : : }
3663 : :
3664 : : static void
3665 : 698 : nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3666 : : {
3667 : 698 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3668 : : union spdk_nvme_cc_register cc;
3669 : : int rc;
3670 : :
3671 [ + - - + ]: 698 : if (spdk_nvme_cpl_is_error(cpl)) {
3672 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3673 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3674 : 0 : return;
3675 : : }
3676 : :
3677 [ - + ]: 698 : assert(value <= UINT32_MAX);
3678 : 698 : cc.raw = (uint32_t)value;
3679 : 698 : cc.bits.en = 0;
3680 : 698 : ctrlr->process_init_cc.raw = cc.raw;
3681 : :
3682 : 698 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC,
3683 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3684 : :
3685 : 698 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr);
3686 [ - + ]: 698 : if (rc != 0) {
3687 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
3688 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3689 : : }
3690 : : }
3691 : :
3692 : : static void
3693 : 698 : nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3694 : : {
3695 : 698 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3696 : : union spdk_nvme_csts_register csts;
3697 : :
3698 [ + - - + ]: 698 : if (spdk_nvme_cpl_is_error(cpl)) {
3699 : : /* While a device is resetting, it may be unable to service MMIO reads
3700 : : * temporarily. Allow for this case.
3701 : : */
3702 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # ]
3703 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # ]
3704 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3705 : : NVME_TIMEOUT_KEEP_EXISTING);
3706 : : } else {
3707 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3708 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3709 : : }
3710 : :
3711 : 0 : return;
3712 : : }
3713 : :
3714 [ - + ]: 698 : assert(value <= UINT32_MAX);
3715 : 698 : csts.raw = (uint32_t)value;
3716 [ - + - - ]: 698 : if (csts.bits.rdy == 1 || csts.bits.cfs == 1) {
3717 : 698 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0,
3718 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3719 : : } else {
3720 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
# # # # ]
3721 : 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3722 : : NVME_TIMEOUT_KEEP_EXISTING);
3723 : : }
3724 : : }
3725 : :
3726 : : static void
3727 : 3415 : nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3728 : : {
3729 : 3415 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3730 : : union spdk_nvme_csts_register csts;
3731 : :
3732 [ + - - + ]: 3415 : if (spdk_nvme_cpl_is_error(cpl)) {
3733 : : /* While a device is resetting, it may be unable to service MMIO reads
3734 : : * temporarily. Allow for this case.
3735 : : */
3736 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # ]
3737 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # ]
3738 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3739 : : NVME_TIMEOUT_KEEP_EXISTING);
3740 : : } else {
3741 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3742 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3743 : : }
3744 : :
3745 : 0 : return;
3746 : : }
3747 : :
3748 [ - + ]: 3415 : assert(value <= UINT32_MAX);
3749 : 3415 : csts.raw = (uint32_t)value;
3750 [ + + ]: 3415 : if (csts.bits.rdy == 0) {
3751 [ - + + + : 2627 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n");
+ + + + ]
3752 : 2627 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED,
3753 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3754 : : } else {
3755 : 788 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3756 : : NVME_TIMEOUT_KEEP_EXISTING);
3757 : : }
3758 : : }
3759 : :
3760 : : static void
3761 : 31330 : nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value,
3762 : : const struct spdk_nvme_cpl *cpl)
3763 : : {
3764 : 31330 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3765 : : union spdk_nvme_csts_register csts;
3766 : :
3767 [ + - - + ]: 31330 : if (spdk_nvme_cpl_is_error(cpl)) {
3768 : : /* While a device is resetting, it may be unable to service MMIO reads
3769 : : * temporarily. Allow for this case.
3770 : : */
3771 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # ]
3772 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # ]
3773 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3774 : : NVME_TIMEOUT_KEEP_EXISTING);
3775 : : } else {
3776 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3777 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3778 : : }
3779 : :
3780 : 0 : return;
3781 : : }
3782 : :
3783 [ - + ]: 31330 : assert(value <= UINT32_MAX);
3784 : 31330 : csts.raw = value;
3785 [ + + ]: 31330 : if (csts.bits.rdy == 1) {
3786 [ - + + + : 2463 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
+ + + + ]
3787 : : /*
3788 : : * The controller has been enabled.
3789 : : * Perform the rest of initialization serially.
3790 : : */
3791 : 2463 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
3792 : 2463 : ctrlr->opts.admin_timeout_ms);
3793 : : } else {
3794 : 28867 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3795 : : NVME_TIMEOUT_KEEP_EXISTING);
3796 : : }
3797 : : }
3798 : :
3799 : : /**
3800 : : * This function will be called repeatedly during initialization until the controller is ready.
3801 : : */
3802 : : int
3803 : 118166706 : nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
3804 : : {
3805 : : uint32_t ready_timeout_in_ms;
3806 : : uint64_t ticks;
3807 : 118166706 : int rc = 0;
3808 : :
3809 : 118166706 : ticks = spdk_get_ticks();
3810 : :
3811 : : /*
3812 : : * May need to avoid accessing any register on the target controller
3813 : : * for a while. Return early without touching the FSM.
3814 : : * Check sleep_timeout_tsc > 0 for unit test.
3815 : : */
3816 [ + + ]: 118166706 : if ((ctrlr->sleep_timeout_tsc > 0) &&
3817 [ + + ]: 114126811 : (ticks <= ctrlr->sleep_timeout_tsc)) {
3818 : 114126717 : return 0;
3819 : : }
3820 : 4039989 : ctrlr->sleep_timeout_tsc = 0;
3821 : :
3822 : 4039989 : ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr);
3823 : :
3824 : : /*
3825 : : * Check if the current initialization step is done or has timed out.
3826 : : */
3827 [ + - + + : 4039989 : switch (ctrlr->state) {
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + +
- ]
3828 : 728 : case NVME_CTRLR_STATE_INIT_DELAY:
3829 : 728 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms);
3830 [ + + ]: 728 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) {
3831 : : /*
3832 : : * Controller may need some delay before it's enabled.
3833 : : *
3834 : : * This is a workaround for an issue where the PCIe-attached NVMe controller
3835 : : * is not ready after VFIO reset. We delay the initialization rather than the
3836 : : * enabling itself, because this is required only for the very first enabling
3837 : : * - directly after a VFIO reset.
3838 : : */
3839 [ - + - + : 94 : NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n");
- - - - ]
3840 : 94 : ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000);
3841 : : }
3842 : 728 : break;
3843 : :
3844 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
3845 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
3846 : 0 : break;
3847 : :
3848 : 2924 : case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */
3849 : 2924 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq);
3850 [ + - ]: 2924 : if (rc == 0) {
3851 : 2924 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ,
3852 : : NVME_TIMEOUT_INFINITE);
3853 : : } else {
3854 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3855 : : }
3856 : 2924 : break;
3857 : :
3858 : 1616627 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
3859 : 1616627 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3860 : :
3861 : 1616627 : switch (nvme_qpair_get_state(ctrlr->adminq)) {
3862 : 1042391 : case NVME_QPAIR_CONNECTING:
3863 : 1042391 : break;
3864 : 1778 : case NVME_QPAIR_CONNECTED:
3865 : 1778 : nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED);
3866 : : /* Fall through */
3867 : 2535 : case NVME_QPAIR_ENABLED:
3868 : 2535 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS,
3869 : : NVME_TIMEOUT_INFINITE);
3870 : : /* Abort any queued requests that were sent while the adminq was connecting
3871 : : * to avoid stalling the init process during a reset, as requests don't get
3872 : : * resubmitted while the controller is resetting and subsequent commands
3873 : : * would get queued too.
3874 : : */
3875 : 2535 : nvme_qpair_abort_queued_reqs(ctrlr->adminq);
3876 : 2535 : break;
3877 : 571312 : case NVME_QPAIR_DISCONNECTING:
3878 [ - + ]: 571312 : assert(ctrlr->adminq->async == true);
3879 : 571312 : break;
3880 : 389 : case NVME_QPAIR_DISCONNECTED:
3881 : : /* fallthrough */
3882 : : default:
3883 : 389 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3884 : 389 : break;
3885 : : }
3886 : :
3887 : 1616627 : break;
3888 : :
3889 : 2535 : case NVME_CTRLR_STATE_READ_VS:
3890 : 2535 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE);
3891 : 2535 : rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr);
3892 : 2535 : break;
3893 : :
3894 : 2535 : case NVME_CTRLR_STATE_READ_CAP:
3895 : 2535 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE);
3896 : 2535 : rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr);
3897 : 2535 : break;
3898 : :
3899 : 2627 : case NVME_CTRLR_STATE_CHECK_EN:
3900 : : /* Begin the hardware initialization by making sure the controller is disabled. */
3901 : 2627 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms);
3902 : 2627 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr);
3903 : 2627 : break;
3904 : :
3905 : 698 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
3906 : : /*
3907 : : * Controller is currently enabled. We need to disable it to cause a reset.
3908 : : *
3909 : : * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
3910 : : * Wait for the ready bit to be 1 before disabling the controller.
3911 : : */
3912 : 698 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3913 : : NVME_TIMEOUT_KEEP_EXISTING);
3914 : 698 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr);
3915 : 698 : break;
3916 : :
3917 : 698 : case NVME_CTRLR_STATE_SET_EN_0:
3918 [ - + - + : 698 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n");
- - - - ]
3919 : 698 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms);
3920 : 698 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr);
3921 : 698 : break;
3922 : :
3923 : 3415 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
3924 : 3415 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS,
3925 : : NVME_TIMEOUT_KEEP_EXISTING);
3926 : 3415 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr);
3927 : 3415 : break;
3928 : :
3929 : 2621 : case NVME_CTRLR_STATE_DISABLED:
3930 [ + + + + ]: 2621 : if (ctrlr->is_disconnecting) {
3931 [ - + - + : 86 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n");
- - - - ]
3932 : : } else {
3933 : 2535 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
3934 : :
3935 : : /*
3936 : : * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting
3937 : : * set to 1 if it is too soon after CSTS.RDY is reported as 0.
3938 : : */
3939 : 2535 : spdk_delay_us(100);
3940 : : }
3941 : 2621 : break;
3942 : :
3943 : 2535 : case NVME_CTRLR_STATE_ENABLE:
3944 [ - + + + : 2535 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n");
+ + + + ]
3945 : 2535 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms);
3946 : 2535 : rc = nvme_ctrlr_enable(ctrlr);
3947 [ + + ]: 2535 : if (rc) {
3948 [ + - - + ]: 42 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc);
3949 : : }
3950 : 2535 : return rc;
3951 : :
3952 : 31330 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
3953 : 31330 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3954 : : NVME_TIMEOUT_KEEP_EXISTING);
3955 : 31330 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1,
3956 : : ctrlr);
3957 : 31330 : break;
3958 : :
3959 : 2463 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
3960 : 2463 : nvme_transport_qpair_reset(ctrlr->adminq);
3961 : 2463 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE);
3962 : 2463 : break;
3963 : :
3964 : 2505 : case NVME_CTRLR_STATE_IDENTIFY:
3965 : 2505 : rc = nvme_ctrlr_identify(ctrlr);
3966 : 2505 : break;
3967 : :
3968 : 2523 : case NVME_CTRLR_STATE_CONFIGURE_AER:
3969 : 2523 : rc = nvme_ctrlr_configure_aer(ctrlr);
3970 : 2523 : break;
3971 : :
3972 : 2541 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
3973 : 2541 : rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
3974 : 2541 : break;
3975 : :
3976 : 2397 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
3977 : 2397 : rc = nvme_ctrlr_identify_iocs_specific(ctrlr);
3978 : 2397 : break;
3979 : :
3980 : 997 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
3981 : 997 : rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr);
3982 : 997 : break;
3983 : :
3984 : 2397 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
3985 : 2397 : nvme_ctrlr_update_nvmf_ioccsz(ctrlr);
3986 : 2397 : rc = nvme_ctrlr_set_num_queues(ctrlr);
3987 : 2397 : break;
3988 : :
3989 : 2427 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
3990 : 2427 : _nvme_ctrlr_identify_active_ns(ctrlr);
3991 : 2427 : break;
3992 : :
3993 : 2367 : case NVME_CTRLR_STATE_IDENTIFY_NS:
3994 : 2367 : rc = nvme_ctrlr_identify_namespaces(ctrlr);
3995 : 2367 : break;
3996 : :
3997 : 2367 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
3998 : 2367 : rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr);
3999 : 2367 : break;
4000 : :
4001 : 2367 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
4002 : 2367 : rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr);
4003 : 2367 : break;
4004 : :
4005 : 2373 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
4006 : 2373 : rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
4007 : 2373 : break;
4008 : :
4009 : 112 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
4010 : 112 : rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr);
4011 : 112 : break;
4012 : :
4013 : 2367 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
4014 : 2367 : nvme_ctrlr_set_supported_features(ctrlr);
4015 : 2367 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
4016 : 2367 : ctrlr->opts.admin_timeout_ms);
4017 : 2367 : break;
4018 : :
4019 : 2367 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
4020 : 2367 : rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
4021 : 2367 : break;
4022 : :
4023 : 2367 : case NVME_CTRLR_STATE_SET_HOST_ID:
4024 : 2367 : rc = nvme_ctrlr_set_host_id(ctrlr);
4025 : 2367 : break;
4026 : :
4027 : 2385 : case NVME_CTRLR_STATE_TRANSPORT_READY:
4028 : 2385 : rc = nvme_transport_ctrlr_ready(ctrlr);
4029 [ + + ]: 2385 : if (rc) {
4030 [ + - - + ]: 6 : NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc);
4031 : 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4032 : : } else {
4033 : 2379 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
4034 : : }
4035 : 2385 : break;
4036 : :
4037 : 41 : case NVME_CTRLR_STATE_READY:
4038 [ - + + + : 41 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n");
+ + + - ]
4039 : 41 : return 0;
4040 : :
4041 : 396 : case NVME_CTRLR_STATE_ERROR:
4042 [ + + + - ]: 396 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n");
4043 : 396 : return -1;
4044 : :
4045 : 2332957 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
4046 : : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
4047 : : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
4048 : : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
4049 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4050 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
4051 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
4052 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4053 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
4054 : : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
4055 : : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
4056 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
4057 : : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
4058 : : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
4059 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
4060 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
4061 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
4062 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
4063 : : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
4064 : : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
4065 : : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
4066 : : /*
4067 : : * nvme_ctrlr_process_init() may be called from the completion context
4068 : : * for the admin qpair. Avoid recursive calls for this case.
4069 : : */
4070 [ + + ]: 2332957 : if (!ctrlr->adminq->in_completion_context) {
4071 : 2332871 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4072 : : }
4073 : 2332957 : break;
4074 : :
4075 : 0 : default:
4076 : 0 : assert(0);
4077 : : return -1;
4078 : : }
4079 : :
4080 [ + + ]: 4037017 : if (rc) {
4081 [ + - - + ]: 6 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n",
4082 : : rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4083 : : }
4084 : :
4085 : : /* Note: we use the ticks captured when we entered this function.
4086 : : * This covers environments where the SPDK process gets swapped out after
4087 : : * we tried to advance the state but before we check the timeout here.
4088 : : * It is not normal for this to happen, but harmless to handle it in this
4089 : : * way.
4090 : : */
4091 [ + + ]: 4037017 : if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
4092 [ - + ]: 2299490 : ticks > ctrlr->state_timeout_tsc) {
4093 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n",
4094 : : ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4095 : 0 : return -1;
4096 : : }
4097 : :
4098 : 4037017 : return rc;
4099 : : }
4100 : :
4101 : : int
4102 : 2625 : nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx)
4103 : : {
4104 : 673 : pthread_mutexattr_t attr;
4105 : 2625 : int rc = 0;
4106 : :
4107 [ - + - + ]: 2625 : if (pthread_mutexattr_init(&attr)) {
4108 : 0 : return -1;
4109 : : }
4110 [ + + + - : 5250 : if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
+ - ]
4111 : : #ifndef __FreeBSD__
4112 [ + + + - ]: 5250 : pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) ||
4113 [ - + - + ]: 5250 : pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) ||
4114 : : #endif
4115 [ - + ]: 2625 : pthread_mutex_init(mtx, &attr)) {
4116 : 0 : rc = -1;
4117 : : }
4118 [ - + ]: 2625 : pthread_mutexattr_destroy(&attr);
4119 : 2625 : return rc;
4120 : : }
4121 : :
4122 : : int
4123 : 2625 : nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
4124 : : {
4125 : : int rc;
4126 : :
4127 [ + + ]: 2625 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
4128 : 728 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE);
4129 : : } else {
4130 : 1897 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
4131 : : }
4132 : :
4133 [ - + ]: 2625 : if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) {
4134 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n",
4135 : : ctrlr->opts.admin_queue_size);
4136 : 0 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES;
4137 : : }
4138 : :
4139 [ - + ]: 2625 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE &&
4140 [ # # ]: 0 : (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) {
4141 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr,
4142 : : "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n",
4143 : : ctrlr->opts.admin_queue_size);
4144 : 0 : ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size,
4145 : : SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE);
4146 : : }
4147 : :
4148 [ + + ]: 2625 : if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) {
4149 [ + - - + ]: 150 : NVME_CTRLR_ERRLOG(ctrlr,
4150 : : "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n",
4151 : : ctrlr->opts.admin_queue_size);
4152 : 150 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES;
4153 : : }
4154 : :
4155 : 2625 : ctrlr->flags = 0;
4156 : 2625 : ctrlr->free_io_qids = NULL;
4157 : 2625 : ctrlr->is_resetting = false;
4158 : 2625 : ctrlr->is_failed = false;
4159 : 2625 : ctrlr->is_destructed = false;
4160 : :
4161 : 2625 : TAILQ_INIT(&ctrlr->active_io_qpairs);
4162 : 2625 : STAILQ_INIT(&ctrlr->queued_aborts);
4163 : 2625 : ctrlr->outstanding_aborts = 0;
4164 : :
4165 : 2625 : ctrlr->ana_log_page = NULL;
4166 : 2625 : ctrlr->ana_log_page_size = 0;
4167 : :
4168 : 2625 : rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock);
4169 [ - + ]: 2625 : if (rc != 0) {
4170 : 0 : return rc;
4171 : : }
4172 : :
4173 : 2625 : TAILQ_INIT(&ctrlr->active_procs);
4174 : 2625 : STAILQ_INIT(&ctrlr->register_operations);
4175 : :
4176 : 2625 : RB_INIT(&ctrlr->ns);
4177 : :
4178 : 2625 : return rc;
4179 : : }
4180 : :
4181 : : static void
4182 : 2535 : nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr)
4183 : : {
4184 [ + + ]: 2535 : if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
4185 : 153 : ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
4186 : : }
4187 : :
4188 [ - + ]: 2535 : ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin);
4189 : :
4190 : : /* For now, always select page_size == min_page_size. */
4191 : 2535 : ctrlr->page_size = ctrlr->min_page_size;
4192 : :
4193 : 2535 : ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES);
4194 : 2535 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES);
4195 [ + + ]: 2535 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE &&
4196 [ + + ]: 101 : ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) {
4197 : : /* If the user specifically set an IO queue size different than the
4198 : : * default, use that value. Otherwise overwrite with the quirked value.
4199 : : * This allows this quirk to be overridden when necessary.
4200 : : * However, cap.mqes still needs to be respected.
4201 : : */
4202 : 89 : ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK;
4203 : : }
4204 : 2535 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u);
4205 : :
4206 : 2535 : ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size);
4207 : 2535 : }
4208 : :
4209 : : void
4210 : 2621 : nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr)
4211 : : {
4212 : : int rc;
4213 : :
4214 [ - + ]: 2621 : if (ctrlr->lock_depth > 0) {
4215 : 0 : SPDK_ERRLOG("lock currently held (depth=%d)!\n", ctrlr->lock_depth);
4216 : 0 : assert(false);
4217 : : }
4218 : :
4219 [ - + ]: 2621 : rc = pthread_mutex_destroy(&ctrlr->ctrlr_lock);
4220 [ - + ]: 2621 : if (rc) {
4221 : 0 : SPDK_ERRLOG("could not destroy ctrlr_lock: %s\n", spdk_strerror(rc));
4222 : 0 : assert(false);
4223 : : }
4224 : :
4225 : 2621 : nvme_ctrlr_free_processes(ctrlr);
4226 : 2621 : }
4227 : :
4228 : : void
4229 : 2610 : nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr,
4230 : : struct nvme_ctrlr_detach_ctx *ctx)
4231 : : {
4232 : : struct spdk_nvme_qpair *qpair, *tmp;
4233 : :
4234 [ - + + + : 2610 : NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n");
+ + + + ]
4235 : :
4236 : 2610 : ctrlr->prepare_for_reset = false;
4237 : 2610 : ctrlr->is_destructed = true;
4238 : :
4239 : 2610 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4240 : :
4241 : 2610 : nvme_ctrlr_abort_queued_aborts(ctrlr);
4242 : 2610 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
4243 : :
4244 [ + + ]: 2774 : TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) {
4245 : 164 : spdk_nvme_ctrlr_free_io_qpair(qpair);
4246 : : }
4247 : :
4248 : 2610 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
4249 : 2610 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
4250 : :
4251 : 2610 : nvme_ctrlr_shutdown_async(ctrlr, ctx);
4252 : 2610 : }
4253 : :
4254 : : int
4255 : 16833275 : nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr,
4256 : : struct nvme_ctrlr_detach_ctx *ctx)
4257 : : {
4258 : : struct spdk_nvme_ns *ns, *tmp_ns;
4259 : 16833275 : int rc = 0;
4260 : :
4261 [ + + + + ]: 16833275 : if (!ctx->shutdown_complete) {
4262 : 16833086 : rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx);
4263 [ + + ]: 16833086 : if (rc == -EAGAIN) {
4264 : 16830665 : return -EAGAIN;
4265 : : }
4266 : : /* Destruct ctrlr forcefully for any other error. */
4267 : : }
4268 : :
4269 [ + + ]: 2610 : if (ctx->cb_fn) {
4270 : 2194 : ctx->cb_fn(ctrlr);
4271 : : }
4272 : :
4273 : 2610 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
4274 : :
4275 [ + + + - ]: 50577 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
4276 : 47967 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
4277 : 47967 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
4278 : 47967 : spdk_free(ns);
4279 : : }
4280 : :
4281 : 2610 : ctrlr->active_ns_count = 0;
4282 : :
4283 : 2610 : spdk_bit_array_free(&ctrlr->free_io_qids);
4284 : :
4285 : 2610 : free(ctrlr->ana_log_page);
4286 : 2610 : free(ctrlr->copied_ana_desc);
4287 : 2610 : ctrlr->ana_log_page = NULL;
4288 : 2610 : ctrlr->copied_ana_desc = NULL;
4289 : 2610 : ctrlr->ana_log_page_size = 0;
4290 : :
4291 : 2610 : nvme_transport_ctrlr_destruct(ctrlr);
4292 : :
4293 : 2610 : return rc;
4294 : : }
4295 : :
4296 : : void
4297 : 416 : nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
4298 : : {
4299 : 416 : struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr };
4300 : : int rc;
4301 : :
4302 : 416 : nvme_ctrlr_destruct_async(ctrlr, &ctx);
4303 : :
4304 : : while (1) {
4305 : 1193 : rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx);
4306 [ + + ]: 1193 : if (rc != -EAGAIN) {
4307 : 416 : break;
4308 : : }
4309 : 777 : nvme_delay(1000);
4310 : : }
4311 : 416 : }
4312 : :
4313 : : int
4314 : 1468418 : nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
4315 : : struct nvme_request *req)
4316 : : {
4317 : 1468418 : return nvme_qpair_submit_request(ctrlr->adminq, req);
4318 : : }
4319 : :
4320 : : static void
4321 : 1422 : nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl)
4322 : : {
4323 : : /* Do nothing */
4324 : 1422 : }
4325 : :
4326 : : /*
4327 : : * Check if we need to send a Keep Alive command.
4328 : : * Caller must hold ctrlr->ctrlr_lock.
4329 : : */
4330 : : static int
4331 : 4766086 : nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr)
4332 : : {
4333 : : uint64_t now;
4334 : : struct nvme_request *req;
4335 : : struct spdk_nvme_cmd *cmd;
4336 : 4766086 : int rc = 0;
4337 : :
4338 : 4766086 : now = spdk_get_ticks();
4339 [ + + ]: 4766086 : if (now < ctrlr->next_keep_alive_tick) {
4340 : 4738094 : return rc;
4341 : : }
4342 : :
4343 : 27992 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL);
4344 [ + + ]: 27992 : if (req == NULL) {
4345 : 26567 : return rc;
4346 : : }
4347 : :
4348 : 1425 : cmd = &req->cmd;
4349 : 1425 : cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE;
4350 : :
4351 : 1425 : rc = nvme_ctrlr_submit_admin_request(ctrlr, req);
4352 [ + + ]: 1425 : if (rc != 0) {
4353 [ + + + - ]: 3 : NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n");
4354 : 3 : rc = -ENXIO;
4355 : : }
4356 : :
4357 : 1425 : ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks;
4358 : 1425 : return rc;
4359 : : }
4360 : :
4361 : : int32_t
4362 : 33999376 : spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
4363 : : {
4364 : : int32_t num_completions;
4365 : : int32_t rc;
4366 : : struct spdk_nvme_ctrlr_process *active_proc;
4367 : :
4368 : 33999376 : nvme_ctrlr_lock(ctrlr);
4369 : :
4370 [ + + ]: 33999376 : if (ctrlr->keep_alive_interval_ticks) {
4371 : 4766086 : rc = nvme_ctrlr_keep_alive(ctrlr);
4372 [ + + ]: 4766086 : if (rc) {
4373 : 3 : nvme_ctrlr_unlock(ctrlr);
4374 : 3 : return rc;
4375 : : }
4376 : : }
4377 : :
4378 : 33999373 : rc = nvme_io_msg_process(ctrlr);
4379 [ - + ]: 33999373 : if (rc < 0) {
4380 : 0 : nvme_ctrlr_unlock(ctrlr);
4381 : 0 : return rc;
4382 : : }
4383 : 33999373 : num_completions = rc;
4384 : :
4385 : 33999373 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4386 : :
4387 : : /* Each process has an async list, complete the ones for this process object */
4388 : 33999373 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4389 [ + + ]: 33999373 : if (active_proc) {
4390 : 33999367 : nvme_ctrlr_complete_queued_async_events(ctrlr);
4391 : : }
4392 : :
4393 [ + + + + : 33999373 : if (rc == -ENXIO && ctrlr->is_disconnecting) {
+ + ]
4394 : 473 : nvme_ctrlr_disconnect_done(ctrlr);
4395 : : }
4396 : :
4397 : 33999373 : nvme_ctrlr_unlock(ctrlr);
4398 : :
4399 [ + + ]: 33999373 : if (rc < 0) {
4400 : 1192 : num_completions = rc;
4401 : : } else {
4402 : 33998187 : num_completions += rc;
4403 : : }
4404 : :
4405 : 33999373 : return num_completions;
4406 : : }
4407 : :
4408 : : const struct spdk_nvme_ctrlr_data *
4409 : 2390940 : spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
4410 : : {
4411 : 2390940 : return &ctrlr->cdata;
4412 : : }
4413 : :
4414 : 34492 : union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr)
4415 : : {
4416 : 20213 : union spdk_nvme_csts_register csts;
4417 : :
4418 [ - + ]: 34492 : if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
4419 : 0 : csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4420 : : }
4421 : 34492 : return csts;
4422 : : }
4423 : :
4424 : 0 : union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr)
4425 : : {
4426 : 0 : union spdk_nvme_cc_register cc;
4427 : :
4428 [ # # ]: 0 : if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
4429 : 0 : cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4430 : : }
4431 : 0 : return cc;
4432 : : }
4433 : :
4434 : 88 : union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
4435 : : {
4436 : 88 : return ctrlr->cap;
4437 : : }
4438 : :
4439 : 1078 : union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
4440 : : {
4441 : 1078 : return ctrlr->vs;
4442 : : }
4443 : :
4444 : 8 : union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr)
4445 : : {
4446 : 0 : union spdk_nvme_cmbsz_register cmbsz;
4447 : :
4448 [ - + ]: 8 : if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) {
4449 : 0 : cmbsz.raw = 0;
4450 : : }
4451 : :
4452 : 8 : return cmbsz;
4453 : : }
4454 : :
4455 : 8 : union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr)
4456 : : {
4457 : 0 : union spdk_nvme_pmrcap_register pmrcap;
4458 : :
4459 [ - + ]: 8 : if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) {
4460 : 0 : pmrcap.raw = 0;
4461 : : }
4462 : :
4463 : 8 : return pmrcap;
4464 : : }
4465 : :
4466 : 0 : union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr)
4467 : : {
4468 : 0 : union spdk_nvme_bpinfo_register bpinfo;
4469 : :
4470 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
4471 : 0 : bpinfo.raw = 0;
4472 : : }
4473 : :
4474 : 0 : return bpinfo;
4475 : : }
4476 : :
4477 : : uint64_t
4478 : 8 : spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr)
4479 : : {
4480 : 8 : return ctrlr->pmr_size;
4481 : : }
4482 : :
4483 : : uint32_t
4484 : 30 : spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
4485 : : {
4486 : 30 : return ctrlr->cdata.nn;
4487 : : }
4488 : :
4489 : : bool
4490 : 55918 : spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4491 : : {
4492 : 46545 : struct spdk_nvme_ns tmp, *ns;
4493 : :
4494 : 55918 : tmp.id = nsid;
4495 : 55918 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4496 : :
4497 [ + + ]: 55918 : if (ns != NULL) {
4498 [ - + ]: 55359 : return ns->active;
4499 : : }
4500 : :
4501 : 559 : return false;
4502 : : }
4503 : :
4504 : : uint32_t
4505 : 10570 : spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr)
4506 : : {
4507 : : struct spdk_nvme_ns *ns;
4508 : :
4509 : 10570 : ns = RB_MIN(nvme_ns_tree, &ctrlr->ns);
4510 [ + + ]: 10570 : if (ns == NULL) {
4511 : 1314 : return 0;
4512 : : }
4513 : :
4514 [ + + ]: 36856 : while (ns != NULL) {
4515 [ + + + + ]: 36833 : if (ns->active) {
4516 : 9233 : return ns->id;
4517 : : }
4518 : :
4519 : 27600 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4520 : : }
4521 : :
4522 : 23 : return 0;
4523 : : }
4524 : :
4525 : : uint32_t
4526 : 37677 : spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
4527 : : {
4528 : 25291 : struct spdk_nvme_ns tmp, *ns;
4529 : :
4530 : 37677 : tmp.id = prev_nsid;
4531 : 37677 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4532 [ + + ]: 37677 : if (ns == NULL) {
4533 : 30 : return 0;
4534 : : }
4535 : :
4536 : 37647 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4537 [ + + ]: 46841 : while (ns != NULL) {
4538 [ + + + + ]: 37701 : if (ns->active) {
4539 : 28507 : return ns->id;
4540 : : }
4541 : :
4542 : 9194 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4543 : : }
4544 : :
4545 : 9140 : return 0;
4546 : : }
4547 : :
4548 : : struct spdk_nvme_ns *
4549 : 89206 : spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4550 : : {
4551 : 66027 : struct spdk_nvme_ns tmp;
4552 : : struct spdk_nvme_ns *ns;
4553 : :
4554 [ + + - + ]: 89206 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
4555 : 5542 : return NULL;
4556 : : }
4557 : :
4558 : 83664 : nvme_ctrlr_lock(ctrlr);
4559 : :
4560 : 83664 : tmp.id = nsid;
4561 : 83664 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4562 : :
4563 [ + + ]: 83664 : if (ns == NULL) {
4564 : 47978 : ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
4565 [ - + ]: 47978 : if (ns == NULL) {
4566 : 0 : nvme_ctrlr_unlock(ctrlr);
4567 : 0 : return NULL;
4568 : : }
4569 : :
4570 [ - + + + : 47978 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid);
+ + + + ]
4571 : 47978 : ns->id = nsid;
4572 : 47978 : RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns);
4573 : : }
4574 : :
4575 : 83664 : nvme_ctrlr_unlock(ctrlr);
4576 : :
4577 : 83664 : return ns;
4578 : : }
4579 : :
4580 : : struct spdk_pci_device *
4581 : 146 : spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr)
4582 : : {
4583 [ - + ]: 146 : if (ctrlr == NULL) {
4584 : 0 : return NULL;
4585 : : }
4586 : :
4587 [ - + ]: 146 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
4588 : 0 : return NULL;
4589 : : }
4590 : :
4591 : 146 : return nvme_ctrlr_proc_get_devhandle(ctrlr);
4592 : : }
4593 : :
4594 : : uint32_t
4595 : 1296 : spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr)
4596 : : {
4597 : 1296 : return ctrlr->max_xfer_size;
4598 : : }
4599 : :
4600 : : uint16_t
4601 : 1175 : spdk_nvme_ctrlr_get_max_sges(const struct spdk_nvme_ctrlr *ctrlr)
4602 : : {
4603 [ + - ]: 1175 : if (ctrlr->flags & SPDK_NVME_CTRLR_SGL_SUPPORTED) {
4604 : 1175 : return ctrlr->max_sges;
4605 : : } else {
4606 : 0 : return UINT16_MAX;
4607 : : }
4608 : : }
4609 : :
4610 : : void
4611 : 1590 : spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
4612 : : spdk_nvme_aer_cb aer_cb_fn,
4613 : : void *aer_cb_arg)
4614 : : {
4615 : : struct spdk_nvme_ctrlr_process *active_proc;
4616 : :
4617 : 1590 : nvme_ctrlr_lock(ctrlr);
4618 : :
4619 : 1590 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4620 [ + - ]: 1590 : if (active_proc) {
4621 : 1590 : active_proc->aer_cb_fn = aer_cb_fn;
4622 : 1590 : active_proc->aer_cb_arg = aer_cb_arg;
4623 : : }
4624 : :
4625 : 1590 : nvme_ctrlr_unlock(ctrlr);
4626 : 1590 : }
4627 : :
4628 : : void
4629 : 0 : spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr)
4630 : : {
4631 : 0 : ctrlr->opts.disable_read_changed_ns_list_log_page = true;
4632 : 0 : }
4633 : :
4634 : : void
4635 : 34 : spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr,
4636 : : uint64_t timeout_io_us, uint64_t timeout_admin_us,
4637 : : spdk_nvme_timeout_cb cb_fn, void *cb_arg)
4638 : : {
4639 : : struct spdk_nvme_ctrlr_process *active_proc;
4640 : :
4641 : 34 : nvme_ctrlr_lock(ctrlr);
4642 : :
4643 : 34 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4644 [ + - ]: 34 : if (active_proc) {
4645 : 34 : active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL;
4646 : 34 : active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL;
4647 : 34 : active_proc->timeout_cb_fn = cb_fn;
4648 : 34 : active_proc->timeout_cb_arg = cb_arg;
4649 : : }
4650 : :
4651 : 34 : ctrlr->timeout_enabled = true;
4652 : :
4653 : 34 : nvme_ctrlr_unlock(ctrlr);
4654 : 34 : }
4655 : :
4656 : : bool
4657 : 385 : spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
4658 : : {
4659 : : /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
4660 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
4661 [ - + ]: 385 : return ctrlr->log_page_supported[log_page];
4662 : : }
4663 : :
4664 : : bool
4665 : 24 : spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
4666 : : {
4667 : : /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
4668 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
4669 [ - + ]: 24 : return ctrlr->feature_supported[feature_code];
4670 : : }
4671 : :
4672 : : int
4673 : 6 : spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4674 : : struct spdk_nvme_ctrlr_list *payload)
4675 : : {
4676 : : struct nvme_completion_poll_status *status;
4677 : : struct spdk_nvme_ns *ns;
4678 : : int res;
4679 : :
4680 [ - + ]: 6 : if (nsid == 0) {
4681 : 0 : return -EINVAL;
4682 : : }
4683 : :
4684 : 6 : status = calloc(1, sizeof(*status));
4685 [ - + ]: 6 : if (!status) {
4686 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4687 : 0 : return -ENOMEM;
4688 : : }
4689 : :
4690 : 6 : res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
4691 : : nvme_completion_poll_cb, status);
4692 [ - + ]: 6 : if (res) {
4693 : 0 : free(status);
4694 : 0 : return res;
4695 : : }
4696 [ - + ]: 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4697 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n");
4698 [ # # # # ]: 0 : if (!status->timed_out) {
4699 : 0 : free(status);
4700 : : }
4701 : 0 : return -ENXIO;
4702 : : }
4703 : 6 : free(status);
4704 : :
4705 : 6 : res = nvme_ctrlr_identify_active_ns(ctrlr);
4706 [ - + ]: 6 : if (res) {
4707 : 0 : return res;
4708 : : }
4709 : :
4710 : 6 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
4711 [ - + ]: 6 : if (ns == NULL) {
4712 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n");
4713 : 0 : return -ENXIO;
4714 : : }
4715 : :
4716 : 6 : return nvme_ns_construct(ns, nsid, ctrlr);
4717 : : }
4718 : :
4719 : : int
4720 : 6 : spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4721 : : struct spdk_nvme_ctrlr_list *payload)
4722 : : {
4723 : : struct nvme_completion_poll_status *status;
4724 : : int res;
4725 : :
4726 [ - + ]: 6 : if (nsid == 0) {
4727 : 0 : return -EINVAL;
4728 : : }
4729 : :
4730 : 6 : status = calloc(1, sizeof(*status));
4731 [ - + ]: 6 : if (!status) {
4732 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4733 : 0 : return -ENOMEM;
4734 : : }
4735 : :
4736 : 6 : res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
4737 : : nvme_completion_poll_cb, status);
4738 [ - + ]: 6 : if (res) {
4739 : 0 : free(status);
4740 : 0 : return res;
4741 : : }
4742 [ - + ]: 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4743 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n");
4744 [ # # # # ]: 0 : if (!status->timed_out) {
4745 : 0 : free(status);
4746 : : }
4747 : 0 : return -ENXIO;
4748 : : }
4749 : 6 : free(status);
4750 : :
4751 : 6 : return nvme_ctrlr_identify_active_ns(ctrlr);
4752 : : }
4753 : :
4754 : : uint32_t
4755 : 6 : spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
4756 : : {
4757 : : struct nvme_completion_poll_status *status;
4758 : : int res;
4759 : : uint32_t nsid;
4760 : :
4761 : 6 : status = calloc(1, sizeof(*status));
4762 [ - + ]: 6 : if (!status) {
4763 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4764 : 0 : return 0;
4765 : : }
4766 : :
4767 : 6 : res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status);
4768 [ - + ]: 6 : if (res) {
4769 : 0 : free(status);
4770 : 0 : return 0;
4771 : : }
4772 [ - + ]: 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4773 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n");
4774 [ # # # # ]: 0 : if (!status->timed_out) {
4775 : 0 : free(status);
4776 : : }
4777 : 0 : return 0;
4778 : : }
4779 : :
4780 : 6 : nsid = status->cpl.cdw0;
4781 : 6 : free(status);
4782 : :
4783 [ - + ]: 6 : assert(nsid > 0);
4784 : :
4785 : : /* Return the namespace ID that was created */
4786 : 6 : return nsid;
4787 : : }
4788 : :
4789 : : int
4790 : 6 : spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4791 : : {
4792 : : struct nvme_completion_poll_status *status;
4793 : : int res;
4794 : :
4795 [ - + ]: 6 : if (nsid == 0) {
4796 : 0 : return -EINVAL;
4797 : : }
4798 : :
4799 : 6 : status = calloc(1, sizeof(*status));
4800 [ - + ]: 6 : if (!status) {
4801 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4802 : 0 : return -ENOMEM;
4803 : : }
4804 : :
4805 : 6 : res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status);
4806 [ - + ]: 6 : if (res) {
4807 : 0 : free(status);
4808 : 0 : return res;
4809 : : }
4810 [ - + ]: 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4811 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n");
4812 [ # # # # ]: 0 : if (!status->timed_out) {
4813 : 0 : free(status);
4814 : : }
4815 : 0 : return -ENXIO;
4816 : : }
4817 : 6 : free(status);
4818 : :
4819 : 6 : return nvme_ctrlr_identify_active_ns(ctrlr);
4820 : : }
4821 : :
4822 : : int
4823 : 0 : spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4824 : : struct spdk_nvme_format *format)
4825 : : {
4826 : : struct nvme_completion_poll_status *status;
4827 : : int res;
4828 : :
4829 : 0 : status = calloc(1, sizeof(*status));
4830 [ # # ]: 0 : if (!status) {
4831 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4832 : 0 : return -ENOMEM;
4833 : : }
4834 : :
4835 : 0 : res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
4836 : : status);
4837 [ # # ]: 0 : if (res) {
4838 : 0 : free(status);
4839 : 0 : return res;
4840 : : }
4841 [ # # ]: 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4842 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n");
4843 [ # # # # ]: 0 : if (!status->timed_out) {
4844 : 0 : free(status);
4845 : : }
4846 : 0 : return -ENXIO;
4847 : : }
4848 : 0 : free(status);
4849 : :
4850 : 0 : return spdk_nvme_ctrlr_reset(ctrlr);
4851 : : }
4852 : :
4853 : : int
4854 : 48 : spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
4855 : : int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status)
4856 : : {
4857 : 40 : struct spdk_nvme_fw_commit fw_commit;
4858 : : struct nvme_completion_poll_status *status;
4859 : : int res;
4860 : : unsigned int size_remaining;
4861 : : unsigned int offset;
4862 : : unsigned int transfer;
4863 : : uint8_t *p;
4864 : :
4865 [ - + ]: 48 : if (!completion_status) {
4866 : 0 : return -EINVAL;
4867 : : }
4868 [ - + ]: 48 : memset(completion_status, 0, sizeof(struct spdk_nvme_status));
4869 [ + + ]: 48 : if (size % 4) {
4870 [ + - - + ]: 6 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n");
4871 : 6 : return -1;
4872 : : }
4873 : :
4874 : : /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG
4875 : : * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG
4876 : : */
4877 [ - + - - ]: 42 : if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) &&
4878 : : (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) {
4879 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n");
4880 : 0 : return -1;
4881 : : }
4882 : :
4883 : 42 : status = calloc(1, sizeof(*status));
4884 [ - + ]: 42 : if (!status) {
4885 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4886 : 0 : return -ENOMEM;
4887 : : }
4888 : :
4889 : : /* Firmware download */
4890 : 42 : size_remaining = size;
4891 : 42 : offset = 0;
4892 : 42 : p = payload;
4893 : :
4894 [ + + ]: 60 : while (size_remaining > 0) {
4895 : 42 : transfer = spdk_min(size_remaining, ctrlr->min_page_size);
4896 : :
4897 [ - + ]: 42 : memset(status, 0, sizeof(*status));
4898 : 42 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
4899 : : nvme_completion_poll_cb,
4900 : : status);
4901 [ + + ]: 42 : if (res) {
4902 : 12 : free(status);
4903 : 12 : return res;
4904 : : }
4905 : :
4906 [ + + ]: 30 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4907 [ + - - + ]: 12 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n");
4908 [ + + + + ]: 12 : if (!status->timed_out) {
4909 : 6 : free(status);
4910 : : }
4911 : 12 : return -ENXIO;
4912 : : }
4913 : 18 : p += transfer;
4914 : 18 : offset += transfer;
4915 : 18 : size_remaining -= transfer;
4916 : : }
4917 : :
4918 : : /* Firmware commit */
4919 [ - + ]: 18 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
4920 : 18 : fw_commit.fs = slot;
4921 : 18 : fw_commit.ca = commit_action;
4922 : :
4923 [ - + ]: 18 : memset(status, 0, sizeof(*status));
4924 : 18 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
4925 : : status);
4926 [ + + ]: 18 : if (res) {
4927 : 6 : free(status);
4928 : 6 : return res;
4929 : : }
4930 : :
4931 : 12 : res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock);
4932 : :
4933 : 12 : memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status));
4934 : :
4935 [ + + + - ]: 12 : if (!status->timed_out) {
4936 : 12 : free(status);
4937 : : }
4938 : :
4939 [ + + ]: 12 : if (res) {
4940 [ - + ]: 6 : if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC ||
4941 [ # # ]: 0 : completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) {
4942 [ - + ]: 6 : if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
4943 [ # # ]: 0 : completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) {
4944 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr,
4945 : : "firmware activation requires conventional reset to be performed. !\n");
4946 : : } else {
4947 [ + - - + ]: 6 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
4948 : : }
4949 : 6 : return -ENXIO;
4950 : : }
4951 : : }
4952 : :
4953 : 6 : return spdk_nvme_ctrlr_reset(ctrlr);
4954 : : }
4955 : :
4956 : : int
4957 : 0 : spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr)
4958 : : {
4959 : : int rc, size;
4960 : : union spdk_nvme_cmbsz_register cmbsz;
4961 : :
4962 : 0 : cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
4963 : :
4964 [ # # # # ]: 0 : if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) {
4965 : 0 : return -ENOTSUP;
4966 : : }
4967 : :
4968 [ # # ]: 0 : size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4));
4969 : :
4970 : 0 : nvme_ctrlr_lock(ctrlr);
4971 : 0 : rc = nvme_transport_ctrlr_reserve_cmb(ctrlr);
4972 : 0 : nvme_ctrlr_unlock(ctrlr);
4973 : :
4974 [ # # ]: 0 : if (rc < 0) {
4975 : 0 : return rc;
4976 : : }
4977 : :
4978 : 0 : return size;
4979 : : }
4980 : :
4981 : : void *
4982 : 17 : spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
4983 : : {
4984 : : void *buf;
4985 : :
4986 : 17 : nvme_ctrlr_lock(ctrlr);
4987 : 17 : buf = nvme_transport_ctrlr_map_cmb(ctrlr, size);
4988 : 17 : nvme_ctrlr_unlock(ctrlr);
4989 : :
4990 : 17 : return buf;
4991 : : }
4992 : :
4993 : : void
4994 : 2 : spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
4995 : : {
4996 : 2 : nvme_ctrlr_lock(ctrlr);
4997 : 2 : nvme_transport_ctrlr_unmap_cmb(ctrlr);
4998 : 2 : nvme_ctrlr_unlock(ctrlr);
4999 : 2 : }
5000 : :
5001 : : int
5002 : 44 : spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
5003 : : {
5004 : : int rc;
5005 : :
5006 : 44 : nvme_ctrlr_lock(ctrlr);
5007 : 44 : rc = nvme_transport_ctrlr_enable_pmr(ctrlr);
5008 : 44 : nvme_ctrlr_unlock(ctrlr);
5009 : :
5010 : 44 : return rc;
5011 : : }
5012 : :
5013 : : int
5014 : 44 : spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
5015 : : {
5016 : : int rc;
5017 : :
5018 : 44 : nvme_ctrlr_lock(ctrlr);
5019 : 44 : rc = nvme_transport_ctrlr_disable_pmr(ctrlr);
5020 : 44 : nvme_ctrlr_unlock(ctrlr);
5021 : :
5022 : 44 : return rc;
5023 : : }
5024 : :
5025 : : void *
5026 : 44 : spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5027 : : {
5028 : : void *buf;
5029 : :
5030 : 44 : nvme_ctrlr_lock(ctrlr);
5031 : 44 : buf = nvme_transport_ctrlr_map_pmr(ctrlr, size);
5032 : 44 : nvme_ctrlr_unlock(ctrlr);
5033 : :
5034 : 44 : return buf;
5035 : : }
5036 : :
5037 : : int
5038 : 44 : spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
5039 : : {
5040 : : int rc;
5041 : :
5042 : 44 : nvme_ctrlr_lock(ctrlr);
5043 : 44 : rc = nvme_transport_ctrlr_unmap_pmr(ctrlr);
5044 : 44 : nvme_ctrlr_unlock(ctrlr);
5045 : :
5046 : 44 : return rc;
5047 : : }
5048 : :
5049 : : int
5050 : 0 : spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload,
5051 : : uint32_t bprsz, uint32_t bprof, uint32_t bpid)
5052 : : {
5053 : 0 : union spdk_nvme_bprsel_register bprsel;
5054 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5055 : 0 : uint64_t bpmbl, bpmb_size;
5056 : :
5057 [ # # ]: 0 : if (ctrlr->cap.bits.bps == 0) {
5058 : 0 : return -ENOTSUP;
5059 : : }
5060 : :
5061 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5062 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5063 : 0 : return -EIO;
5064 : : }
5065 : :
5066 [ # # ]: 0 : if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) {
5067 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n");
5068 : 0 : return -EALREADY;
5069 : : }
5070 : :
5071 : 0 : nvme_ctrlr_lock(ctrlr);
5072 : :
5073 : 0 : bpmb_size = bprsz * 4096;
5074 : 0 : bpmbl = spdk_vtophys(payload, &bpmb_size);
5075 [ # # ]: 0 : if (bpmbl == SPDK_VTOPHYS_ERROR) {
5076 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n");
5077 : 0 : nvme_ctrlr_unlock(ctrlr);
5078 : 0 : return -EFAULT;
5079 : : }
5080 : :
5081 [ # # ]: 0 : if (bpmb_size != bprsz * 4096) {
5082 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n");
5083 : 0 : nvme_ctrlr_unlock(ctrlr);
5084 : 0 : return -EFAULT;
5085 : : }
5086 : :
5087 [ # # ]: 0 : if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) {
5088 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n");
5089 : 0 : nvme_ctrlr_unlock(ctrlr);
5090 : 0 : return -EIO;
5091 : : }
5092 : :
5093 : 0 : bprsel.bits.bpid = bpid;
5094 : 0 : bprsel.bits.bprof = bprof;
5095 : 0 : bprsel.bits.bprsz = bprsz;
5096 : :
5097 [ # # ]: 0 : if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) {
5098 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n");
5099 : 0 : nvme_ctrlr_unlock(ctrlr);
5100 : 0 : return -EIO;
5101 : : }
5102 : :
5103 : 0 : nvme_ctrlr_unlock(ctrlr);
5104 : 0 : return 0;
5105 : : }
5106 : :
5107 : : int
5108 : 0 : spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr)
5109 : : {
5110 : 0 : int rc = 0;
5111 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5112 : :
5113 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5114 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5115 : 0 : return -EIO;
5116 : : }
5117 : :
5118 [ # # # # : 0 : switch (bpinfo.bits.brs) {
# ]
5119 : 0 : case SPDK_NVME_BRS_NO_READ:
5120 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n");
5121 : 0 : rc = -EINVAL;
5122 : 0 : break;
5123 : 0 : case SPDK_NVME_BRS_READ_IN_PROGRESS:
5124 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n");
# # # # ]
5125 : 0 : rc = -EAGAIN;
5126 : 0 : break;
5127 : 0 : case SPDK_NVME_BRS_READ_ERROR:
5128 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n");
5129 : 0 : rc = -EIO;
5130 : 0 : break;
5131 : 0 : case SPDK_NVME_BRS_READ_SUCCESS:
5132 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n");
# # # # ]
5133 : 0 : break;
5134 : 0 : default:
5135 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n");
5136 : 0 : rc = -EINVAL;
5137 : : }
5138 : :
5139 : 0 : return rc;
5140 : : }
5141 : :
5142 : : static void
5143 : 0 : nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl)
5144 : : {
5145 : : int res;
5146 : 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
5147 : 0 : struct spdk_nvme_fw_commit fw_commit;
5148 : 0 : struct spdk_nvme_cpl err_cpl =
5149 : : {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }};
5150 : :
5151 [ # # # # ]: 0 : if (spdk_nvme_cpl_is_error(cpl)) {
5152 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n");
5153 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5154 : 0 : return;
5155 : : }
5156 : :
5157 [ # # ]: 0 : if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) {
5158 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset);
# # # # ]
5159 : 0 : ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size;
5160 : 0 : ctrlr->fw_offset += ctrlr->fw_transfer_size;
5161 : 0 : ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size;
5162 : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5163 : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5164 : : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5165 [ # # ]: 0 : if (res) {
5166 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n");
5167 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5168 : 0 : return;
5169 : : }
5170 : :
5171 [ # # ]: 0 : if (ctrlr->fw_transfer_size < ctrlr->min_page_size) {
5172 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED;
5173 : : }
5174 [ # # ]: 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) {
5175 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n");
# # # # ]
5176 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5177 : 0 : fw_commit.bpid = ctrlr->bpid;
5178 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION;
5179 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5180 : : nvme_write_boot_partition_cb, ctrlr);
5181 [ # # ]: 0 : if (res) {
5182 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5183 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5184 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5185 : 0 : return;
5186 : : }
5187 : :
5188 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE;
5189 [ # # ]: 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) {
5190 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n");
# # # # ]
5191 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5192 : 0 : fw_commit.bpid = ctrlr->bpid;
5193 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION;
5194 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5195 : : nvme_write_boot_partition_cb, ctrlr);
5196 [ # # ]: 0 : if (res) {
5197 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5198 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5199 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5200 : 0 : return;
5201 : : }
5202 : :
5203 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE;
5204 [ # # ]: 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) {
5205 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n");
# # # # ]
5206 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5207 : : } else {
5208 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n");
5209 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5210 : 0 : return;
5211 : : }
5212 : : }
5213 : :
5214 : : int
5215 : 0 : spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr,
5216 : : void *payload, uint32_t size, uint32_t bpid,
5217 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
5218 : : {
5219 : : int res;
5220 : :
5221 [ # # ]: 0 : if (ctrlr->cap.bits.bps == 0) {
5222 : 0 : return -ENOTSUP;
5223 : : }
5224 : :
5225 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING;
5226 : 0 : ctrlr->bpid = bpid;
5227 : 0 : ctrlr->bp_write_cb_fn = cb_fn;
5228 : 0 : ctrlr->bp_write_cb_arg = cb_arg;
5229 : 0 : ctrlr->fw_offset = 0;
5230 : 0 : ctrlr->fw_size_remaining = size;
5231 : 0 : ctrlr->fw_payload = payload;
5232 : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5233 : :
5234 : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5235 : : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5236 : :
5237 : 0 : return res;
5238 : : }
5239 : :
5240 : : bool
5241 : 7178 : spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr)
5242 : : {
5243 [ - + ]: 7178 : assert(ctrlr);
5244 : :
5245 [ - + ]: 7178 : return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN,
5246 : : strlen(SPDK_NVMF_DISCOVERY_NQN));
5247 : : }
5248 : :
5249 : : bool
5250 : 3333 : spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr)
5251 : : {
5252 [ - + ]: 3333 : assert(ctrlr);
5253 : :
5254 : 3333 : return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype);
5255 : : }
5256 : :
5257 : : int
5258 : 64 : spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5259 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5260 : : {
5261 : : struct nvme_completion_poll_status *status;
5262 : : int res;
5263 : :
5264 : 64 : status = calloc(1, sizeof(*status));
5265 [ - + ]: 64 : if (!status) {
5266 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5267 : 0 : return -ENOMEM;
5268 : : }
5269 : :
5270 : 64 : res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size,
5271 : : nvme_completion_poll_cb, status);
5272 [ - + ]: 64 : if (res) {
5273 : 0 : free(status);
5274 : 0 : return res;
5275 : : }
5276 [ - + ]: 64 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5277 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n");
5278 [ # # # # ]: 0 : if (!status->timed_out) {
5279 : 0 : free(status);
5280 : : }
5281 : 0 : return -ENXIO;
5282 : : }
5283 : 64 : free(status);
5284 : :
5285 : 64 : return 0;
5286 : : }
5287 : :
5288 : : int
5289 : 0 : spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5290 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5291 : : {
5292 : : struct nvme_completion_poll_status *status;
5293 : : int res;
5294 : :
5295 : 0 : status = calloc(1, sizeof(*status));
5296 [ # # ]: 0 : if (!status) {
5297 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5298 : 0 : return -ENOMEM;
5299 : : }
5300 : :
5301 : 0 : res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size,
5302 : : nvme_completion_poll_cb,
5303 : : status);
5304 [ # # ]: 0 : if (res) {
5305 : 0 : free(status);
5306 : 0 : return res;
5307 : : }
5308 [ # # ]: 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5309 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n");
5310 [ # # # # ]: 0 : if (!status->timed_out) {
5311 : 0 : free(status);
5312 : : }
5313 : 0 : return -ENXIO;
5314 : : }
5315 : :
5316 : 0 : free(status);
5317 : :
5318 : 0 : return 0;
5319 : : }
5320 : :
5321 : : uint64_t
5322 : 7497 : spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr)
5323 : : {
5324 : 7497 : return ctrlr->flags;
5325 : : }
5326 : :
5327 : : const struct spdk_nvme_transport_id *
5328 : 2130 : spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr)
5329 : : {
5330 : 2130 : return &ctrlr->trid;
5331 : : }
5332 : :
5333 : : int32_t
5334 : 4856 : spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr)
5335 : : {
5336 : : uint32_t qid;
5337 : :
5338 [ - + ]: 4856 : assert(ctrlr->free_io_qids);
5339 : 4856 : nvme_ctrlr_lock(ctrlr);
5340 : 4856 : qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
5341 [ + + ]: 4856 : if (qid > ctrlr->opts.num_io_queues) {
5342 [ + - - + ]: 13 : NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n");
5343 : 13 : nvme_ctrlr_unlock(ctrlr);
5344 : 13 : return -1;
5345 : : }
5346 : :
5347 : 4843 : spdk_bit_array_clear(ctrlr->free_io_qids, qid);
5348 : 4843 : nvme_ctrlr_unlock(ctrlr);
5349 : 4843 : return qid;
5350 : : }
5351 : :
5352 : : void
5353 : 252227 : spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid)
5354 : : {
5355 [ - + ]: 252227 : assert(qid <= ctrlr->opts.num_io_queues);
5356 : :
5357 : 252227 : nvme_ctrlr_lock(ctrlr);
5358 : :
5359 [ + + ]: 252227 : if (spdk_likely(ctrlr->free_io_qids)) {
5360 : 252191 : spdk_bit_array_set(ctrlr->free_io_qids, qid);
5361 : : }
5362 : :
5363 : 252227 : nvme_ctrlr_unlock(ctrlr);
5364 : 252227 : }
5365 : :
5366 : : int
5367 : 9997 : spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
5368 : : struct spdk_memory_domain **domains, int array_size)
5369 : : {
5370 : 9997 : return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size);
5371 : : }
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