Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (C) 2015 Intel Corporation. All rights reserved.
3 : : * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.
4 : : * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 : : */
6 : :
7 : : #include "spdk/stdinc.h"
8 : :
9 : : #include "nvme_internal.h"
10 : : #include "nvme_io_msg.h"
11 : :
12 : : #include "spdk/env.h"
13 : : #include "spdk/string.h"
14 : : #include "spdk/endian.h"
15 : :
16 : : struct nvme_active_ns_ctx;
17 : :
18 : : static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
19 : : struct nvme_async_event_request *aer);
20 : : static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx);
21 : : static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns);
22 : : static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns);
23 : : static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns);
24 : : static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr);
25 : : static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
26 : : uint64_t timeout_in_ms);
27 : :
28 : : static int
29 : 2888201 : nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2)
30 : : {
31 [ + + + - : 2888201 : if (ns1->id < ns2->id) {
+ - + - +
+ ]
32 : 989843 : return -1;
33 [ + + + - : 1898358 : } else if (ns1->id > ns2->id) {
+ - + - +
+ ]
34 : 1657909 : return 1;
35 : : } else {
36 : 240449 : return 0;
37 : : }
38 : 483207 : }
39 : :
40 [ + + + + : 3744509 : RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp);
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41 : :
42 : : #define CTRLR_STRING(ctrlr) \
43 : : ((ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP || ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA) ? \
44 : : ctrlr->trid.subnqn : ctrlr->trid.traddr)
45 : :
46 : : #define NVME_CTRLR_ERRLOG(ctrlr, format, ...) \
47 : : SPDK_ERRLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
48 : :
49 : : #define NVME_CTRLR_WARNLOG(ctrlr, format, ...) \
50 : : SPDK_WARNLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
51 : :
52 : : #define NVME_CTRLR_NOTICELOG(ctrlr, format, ...) \
53 : : SPDK_NOTICELOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
54 : :
55 : : #define NVME_CTRLR_INFOLOG(ctrlr, format, ...) \
56 : : SPDK_INFOLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
57 : :
58 : : #ifdef DEBUG
59 : : #define NVME_CTRLR_DEBUGLOG(ctrlr, format, ...) \
60 : : SPDK_DEBUGLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
61 : : #else
62 : : #define NVME_CTRLR_DEBUGLOG(ctrlr, ...) do { } while (0)
63 : : #endif
64 : :
65 : : #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \
66 : : nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \
67 : : offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg)
68 : :
69 : : #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \
70 : : nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \
71 : : offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg)
72 : :
73 : : #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \
74 : : nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg)
75 : :
76 : : #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \
77 : : nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg)
78 : :
79 : : #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \
80 : : nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg)
81 : :
82 : : #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \
83 : : nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg)
84 : :
85 : : #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \
86 : : nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg)
87 : :
88 : : static int
89 : 0 : nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
90 : : {
91 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
92 [ # # ]: 0 : &cc->raw);
93 : : }
94 : :
95 : : static int
96 : 32403 : nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
97 : : {
98 : 32403 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
99 [ + - ]: 32 : &csts->raw);
100 : : }
101 : :
102 : : int
103 : 692 : nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
104 : : {
105 : 692 : return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
106 [ + - ]: 9 : &cap->raw);
107 : : }
108 : :
109 : : int
110 : 6 : nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
111 : : {
112 : 6 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
113 [ + - ]: 1 : &vs->raw);
114 : : }
115 : :
116 : : int
117 : 8 : nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz)
118 : : {
119 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
120 [ # # ]: 0 : &cmbsz->raw);
121 : : }
122 : :
123 : : int
124 : 8 : nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap)
125 : : {
126 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
127 [ # # ]: 0 : &pmrcap->raw);
128 : : }
129 : :
130 : : int
131 : 0 : nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo)
132 : : {
133 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw),
134 [ # # ]: 0 : &bpinfo->raw);
135 : : }
136 : :
137 : : int
138 : 0 : nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel)
139 : : {
140 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw),
141 [ # # # # ]: 0 : bprsel->raw);
142 : : }
143 : :
144 : : int
145 : 0 : nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value)
146 : : {
147 : 0 : return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl),
148 : 0 : bpmbl_value);
149 : : }
150 : :
151 : : static int
152 : 0 : nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
153 : : {
154 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr),
155 : 0 : nssr_value);
156 : : }
157 : :
158 : : bool
159 : 5638 : nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr)
160 : : {
161 [ + + + - : 6880 : return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS &&
+ - + - +
+ ]
162 [ + + + - : 1242 : ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS;
+ - ]
163 : : }
164 : :
165 : : /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please
166 : : * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c
167 : : */
168 : : void
169 : 3733 : spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size)
170 : : {
171 : 782 : char host_id_str[SPDK_UUID_STRING_LEN];
172 : :
173 [ + + # # ]: 3733 : assert(opts);
174 : :
175 [ + - + - ]: 3733 : opts->opts_size = opts_size;
176 : :
177 : : #define FIELD_OK(field) \
178 : : offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size
179 : :
180 : : #define SET_FIELD(field, value) \
181 : : if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \
182 : : opts->field = value; \
183 : : } \
184 : :
185 [ + + + - : 3733 : SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES);
+ - ]
186 [ + + + - : 3733 : SET_FIELD(use_cmb_sqs, false);
+ - ]
187 [ + + + - : 3733 : SET_FIELD(no_shn_notification, false);
+ - ]
188 [ + + + - : 3733 : SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR);
+ - ]
189 [ + + + - : 3733 : SET_FIELD(arbitration_burst, 0);
+ - ]
190 [ + + + - : 3733 : SET_FIELD(low_priority_weight, 0);
+ - ]
191 [ + + + - : 3733 : SET_FIELD(medium_priority_weight, 0);
+ - ]
192 [ + + + - : 3733 : SET_FIELD(high_priority_weight, 0);
+ - ]
193 [ + + + - : 3733 : SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS);
+ - ]
194 [ + + + - : 3733 : SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT);
+ - ]
195 [ + + + - : 3733 : SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE);
+ - ]
196 : :
197 [ + + ]: 3733 : if (nvme_driver_init() == 0) {
198 [ + + ]: 3733 : if (FIELD_OK(hostnqn)) {
199 : 3727 : spdk_uuid_fmt_lower(host_id_str, sizeof(host_id_str),
200 [ + - ]: 3727 : &g_spdk_nvme_driver->default_extended_host_id);
201 [ + + ]: 3727 : snprintf(opts->hostnqn, sizeof(opts->hostnqn),
202 : 1064 : "nqn.2014-08.org.nvmexpress:uuid:%s", host_id_str);
203 : 1064 : }
204 : :
205 [ + + ]: 3733 : if (FIELD_OK(extended_host_id)) {
206 [ + - + - : 3727 : memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
+ - + - ]
207 : : sizeof(opts->extended_host_id));
208 : 1064 : }
209 : :
210 : 1065 : }
211 : :
212 [ + + + - : 3733 : SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
+ - ]
213 : :
214 [ + + ]: 3733 : if (FIELD_OK(src_addr)) {
215 [ + + + - ]: 3727 : memset(opts->src_addr, 0, sizeof(opts->src_addr));
216 : 1064 : }
217 : :
218 [ + + ]: 3733 : if (FIELD_OK(src_svcid)) {
219 [ + + + - ]: 3727 : memset(opts->src_svcid, 0, sizeof(opts->src_svcid));
220 : 1064 : }
221 : :
222 [ + + ]: 3733 : if (FIELD_OK(host_id)) {
223 [ + + + - ]: 3727 : memset(opts->host_id, 0, sizeof(opts->host_id));
224 : 1064 : }
225 : :
226 [ + + + - : 3733 : SET_FIELD(command_set, CHAR_BIT);
+ - ]
227 [ + + + - : 3733 : SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
+ - ]
228 [ + + + - : 3733 : SET_FIELD(header_digest, false);
+ - ]
229 [ + + + - : 3733 : SET_FIELD(data_digest, false);
+ - ]
230 [ + + + - : 3733 : SET_FIELD(disable_error_logging, false);
+ - ]
231 [ + + + - : 3733 : SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT);
+ - ]
232 [ + + + - : 3733 : SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE);
+ - ]
233 [ + + + - : 3733 : SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT);
+ - ]
234 [ + + + - : 3733 : SET_FIELD(disable_read_ana_log_page, false);
+ - ]
235 [ + + + - : 3733 : SET_FIELD(disable_read_changed_ns_list_log_page, false);
+ - ]
236 : :
237 [ + + ]: 3733 : if (FIELD_OK(psk)) {
238 [ + + + - ]: 3727 : memset(opts->psk, 0, sizeof(opts->psk));
239 : 1064 : }
240 : :
241 : : #undef FIELD_OK
242 : : #undef SET_FIELD
243 : 3733 : }
244 : :
245 : : const struct spdk_nvme_ctrlr_opts *
246 : 1358 : spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr)
247 : : {
248 [ + - ]: 1358 : return &ctrlr->opts;
249 : : }
250 : :
251 : : /**
252 : : * This function will be called when the process allocates the IO qpair.
253 : : * Note: the ctrlr_lock must be held when calling this function.
254 : : */
255 : : static void
256 : 5461 : nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair)
257 : : {
258 : 15 : struct spdk_nvme_ctrlr_process *active_proc;
259 [ + - + - ]: 5461 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
260 : :
261 : 5461 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
262 [ + + ]: 5461 : if (active_proc) {
263 [ + - + - : 5371 : TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq);
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - ]
264 [ + - + - ]: 5371 : qpair->active_proc = active_proc;
265 : 1062 : }
266 : 5461 : }
267 : :
268 : : /**
269 : : * This function will be called when the process frees the IO qpair.
270 : : * Note: the ctrlr_lock must be held when calling this function.
271 : : */
272 : : static void
273 : 5461 : nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair)
274 : : {
275 : 15 : struct spdk_nvme_ctrlr_process *active_proc;
276 [ + - + - ]: 5461 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
277 : 15 : struct spdk_nvme_qpair *active_qpair, *tmp_qpair;
278 : :
279 : 5461 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
280 [ + + ]: 5461 : if (!active_proc) {
281 : 90 : return;
282 : : }
283 : :
284 [ + - + - : 5708 : TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs,
+ - - + +
- + - + -
- + ]
285 : : per_process_tailq, tmp_qpair) {
286 [ + + ]: 5708 : if (active_qpair == qpair) {
287 [ + + + - : 5371 : TAILQ_REMOVE(&active_proc->allocated_io_qpairs,
+ - - + #
# # # # #
# # # # #
# # # # #
# # - + -
+ - + - +
- + - + +
- + - + -
+ - + - +
- + - ]
288 : : active_qpair, per_process_tailq);
289 : :
290 : 5371 : break;
291 : : }
292 : 0 : }
293 [ - + ]: 1077 : }
294 : :
295 : : void
296 : 7877 : spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr,
297 : : struct spdk_nvme_io_qpair_opts *opts,
298 : : size_t opts_size)
299 : : {
300 [ + + # # ]: 7877 : assert(ctrlr);
301 : :
302 [ + + # # ]: 7877 : assert(opts);
303 : :
304 [ + + ]: 7877 : memset(opts, 0, opts_size);
305 : :
306 : : #define FIELD_OK(field) \
307 : : offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size
308 : :
309 [ + + ]: 7877 : if (FIELD_OK(qprio)) {
310 [ + - + - ]: 7877 : opts->qprio = SPDK_NVME_QPRIO_URGENT;
311 : 1090 : }
312 : :
313 [ + + ]: 7877 : if (FIELD_OK(io_queue_size)) {
314 [ + - + - : 7877 : opts->io_queue_size = ctrlr->opts.io_queue_size;
+ - + - +
- ]
315 : 1090 : }
316 : :
317 [ + + ]: 7877 : if (FIELD_OK(io_queue_requests)) {
318 [ + - + - : 7871 : opts->io_queue_requests = ctrlr->opts.io_queue_requests;
+ - + - +
- ]
319 : 1089 : }
320 : :
321 [ + + ]: 7877 : if (FIELD_OK(delay_cmd_submit)) {
322 [ + - + - : 7871 : opts->delay_cmd_submit = false;
+ - ]
323 : 1089 : }
324 : :
325 [ + + ]: 7877 : if (FIELD_OK(sq.vaddr)) {
326 [ + - + - : 7871 : opts->sq.vaddr = NULL;
+ - ]
327 : 1089 : }
328 : :
329 [ + + ]: 7877 : if (FIELD_OK(sq.paddr)) {
330 [ + - + - : 7871 : opts->sq.paddr = 0;
+ - ]
331 : 1089 : }
332 : :
333 [ + + ]: 7877 : if (FIELD_OK(sq.buffer_size)) {
334 [ + - + - : 7871 : opts->sq.buffer_size = 0;
+ - ]
335 : 1089 : }
336 : :
337 [ + + ]: 7877 : if (FIELD_OK(cq.vaddr)) {
338 [ + - + - : 7871 : opts->cq.vaddr = NULL;
+ - ]
339 : 1089 : }
340 : :
341 [ + + ]: 7877 : if (FIELD_OK(cq.paddr)) {
342 [ + - + - : 7871 : opts->cq.paddr = 0;
+ - ]
343 : 1089 : }
344 : :
345 [ + + ]: 7877 : if (FIELD_OK(cq.buffer_size)) {
346 [ + - + - : 7871 : opts->cq.buffer_size = 0;
+ - ]
347 : 1089 : }
348 : :
349 [ + + ]: 7877 : if (FIELD_OK(create_only)) {
350 [ + - + - ]: 7871 : opts->create_only = false;
351 : 1089 : }
352 : :
353 [ + + ]: 7877 : if (FIELD_OK(async_mode)) {
354 [ + - + - ]: 7871 : opts->async_mode = false;
355 : 1089 : }
356 : :
357 : : #undef FIELD_OK
358 : 7877 : }
359 : :
360 : : static struct spdk_nvme_qpair *
361 : 5504 : nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
362 : : const struct spdk_nvme_io_qpair_opts *opts)
363 : : {
364 : 22 : int32_t qid;
365 : 22 : struct spdk_nvme_qpair *qpair;
366 : 22 : union spdk_nvme_cc_register cc;
367 : :
368 [ + + ]: 5504 : if (!ctrlr) {
369 : 0 : return NULL;
370 : : }
371 : :
372 : 5504 : nvme_ctrlr_lock(ctrlr);
373 [ + - + - : 5504 : cc.raw = ctrlr->process_init_cc.raw;
+ - ]
374 : :
375 [ + + + - : 5504 : if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) {
+ + ]
376 : 12 : nvme_ctrlr_unlock(ctrlr);
377 : 12 : return NULL;
378 : : }
379 : :
380 : : /*
381 : : * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
382 : : * default round robin arbitration method.
383 : : */
384 [ + + + + : 5492 : if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) {
+ - + + ]
385 [ + - + + : 18 : NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
386 : 18 : nvme_ctrlr_unlock(ctrlr);
387 : 18 : return NULL;
388 : : }
389 : :
390 : 5474 : qid = spdk_nvme_ctrlr_alloc_qid(ctrlr);
391 [ + + ]: 5474 : if (qid < 0) {
392 : 13 : nvme_ctrlr_unlock(ctrlr);
393 : 13 : return NULL;
394 : : }
395 : :
396 : 5461 : qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts);
397 [ + + ]: 5461 : if (qpair == NULL) {
398 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
399 : 0 : spdk_nvme_ctrlr_free_qid(ctrlr, qid);
400 : 0 : nvme_ctrlr_unlock(ctrlr);
401 : 0 : return NULL;
402 : : }
403 : :
404 [ + - + - : 5461 : TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - ]
405 : :
406 : 5461 : nvme_ctrlr_proc_add_io_qpair(qpair);
407 : :
408 : 5461 : nvme_ctrlr_unlock(ctrlr);
409 : :
410 : 5461 : return qpair;
411 : 1084 : }
412 : :
413 : : int
414 : 5461 : spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
415 : : {
416 : 15 : int rc;
417 : :
418 [ - + ]: 5461 : if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) {
419 : 0 : return -EISCONN;
420 : : }
421 : :
422 : 5461 : nvme_ctrlr_lock(ctrlr);
423 : 5461 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
424 : 5461 : nvme_ctrlr_unlock(ctrlr);
425 : :
426 [ + + + - : 5461 : if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
+ - ]
427 : 0 : spdk_delay_us(100);
428 : 0 : }
429 : :
430 : 5461 : return rc;
431 : 1077 : }
432 : :
433 : : void
434 : 1748 : spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair)
435 : : {
436 [ + - + - ]: 1748 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
437 : :
438 : 1748 : nvme_ctrlr_lock(ctrlr);
439 : 1748 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
440 : 1748 : nvme_ctrlr_unlock(ctrlr);
441 : 1748 : }
442 : :
443 : : struct spdk_nvme_qpair *
444 : 5510 : spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
445 : : const struct spdk_nvme_io_qpair_opts *user_opts,
446 : : size_t opts_size)
447 : : {
448 : :
449 : 5510 : struct spdk_nvme_qpair *qpair = NULL;
450 : 957 : struct spdk_nvme_io_qpair_opts opts;
451 : 23 : int rc;
452 : :
453 : 5510 : nvme_ctrlr_lock(ctrlr);
454 : :
455 [ + + + - : 5510 : if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) {
+ + ]
456 : : /* When controller is resetting or initializing, free_io_qids is deleted or not created yet.
457 : : * We can't create IO qpair in that case */
458 : 6 : goto unlock;
459 : : }
460 : :
461 : : /*
462 : : * Get the default options, then overwrite them with the user-provided options
463 : : * up to opts_size.
464 : : *
465 : : * This allows for extensions of the opts structure without breaking
466 : : * ABI compatibility.
467 : : */
468 : 5504 : spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts));
469 [ + + ]: 5504 : if (user_opts) {
470 [ - + + - : 2395 : memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size));
+ - ]
471 : :
472 : : /* If user passes buffers, make sure they're big enough for the requested queue size */
473 [ + + + - : 2395 : if (opts.sq.vaddr) {
+ - ]
474 [ # # # # : 0 : if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) {
# # # # ]
475 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
476 : : opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd)));
477 : 0 : goto unlock;
478 : : }
479 : 0 : }
480 [ + + + - : 2395 : if (opts.cq.vaddr) {
+ - ]
481 [ # # # # : 0 : if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) {
# # # # ]
482 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
483 : : opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl)));
484 : 0 : goto unlock;
485 : : }
486 : 0 : }
487 : 19 : }
488 : :
489 : 5504 : qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts);
490 : :
491 [ + + + + : 5504 : if (qpair == NULL || opts.create_only == true) {
+ + + + ]
492 : 2056 : goto unlock;
493 : : }
494 : :
495 : 3448 : rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair);
496 [ + + ]: 3448 : if (rc != 0) {
497 [ + - + + : 6 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
498 : 6 : nvme_ctrlr_proc_remove_io_qpair(qpair);
499 [ + + + - : 6 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
+ - - + #
# # # # #
# # # # #
# # # # #
# # + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - ]
500 [ + - + - : 6 : spdk_bit_array_set(ctrlr->free_io_qids, qpair->id);
+ - + - ]
501 : 6 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
502 : 6 : qpair = NULL;
503 : 6 : goto unlock;
504 : : }
505 : :
506 : 3153 : unlock:
507 : 5510 : nvme_ctrlr_unlock(ctrlr);
508 : :
509 : 5533 : return qpair;
510 : 23 : }
511 : :
512 : : int
513 : 13487 : spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair)
514 : : {
515 : 8 : struct spdk_nvme_ctrlr *ctrlr;
516 : 8 : enum nvme_qpair_state qpair_state;
517 : 8 : int rc;
518 : :
519 [ + + # # ]: 13487 : assert(qpair != NULL);
520 [ + + # # ]: 13487 : assert(nvme_qpair_is_admin_queue(qpair) == false);
521 [ + + + - : 13487 : assert(qpair->ctrlr != NULL);
+ - # # ]
522 : :
523 [ + - + - ]: 13487 : ctrlr = qpair->ctrlr;
524 : 13487 : nvme_ctrlr_lock(ctrlr);
525 : 13487 : qpair_state = nvme_qpair_get_state(qpair);
526 : :
527 [ + + + + : 13487 : if (ctrlr->is_removed) {
+ - + + ]
528 : 12 : rc = -ENODEV;
529 : 12 : goto out;
530 : : }
531 : :
532 [ + + + + : 13475 : if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) {
+ + + + -
+ ]
533 : 13 : rc = -EAGAIN;
534 : 13 : goto out;
535 : : }
536 : :
537 [ + + + + : 13462 : if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) {
+ + + + -
+ ]
538 : 12 : rc = -ENXIO;
539 : 12 : goto out;
540 : : }
541 : :
542 [ + + ]: 13450 : if (qpair_state != NVME_QPAIR_DISCONNECTED) {
543 : 6 : rc = 0;
544 : 6 : goto out;
545 : : }
546 : :
547 : 13444 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
548 [ + + ]: 13444 : if (rc) {
549 : 13436 : rc = -EAGAIN;
550 : 13436 : goto out;
551 : : }
552 : :
553 : 7 : out:
554 : 13487 : nvme_ctrlr_unlock(ctrlr);
555 : 13495 : return rc;
556 : 8 : }
557 : :
558 : : spdk_nvme_qp_failure_reason
559 : 1030429 : spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr)
560 : : {
561 [ + - + - : 1030429 : return ctrlr->adminq->transport_failure_reason;
+ - ]
562 : : }
563 : :
564 : : /*
565 : : * This internal function will attempt to take the controller
566 : : * lock before calling disconnect on a controller qpair.
567 : : * Functions already holding the controller lock should
568 : : * call nvme_transport_ctrlr_disconnect_qpair directly.
569 : : */
570 : : void
571 : 12583 : nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair)
572 : : {
573 [ # # # # ]: 12583 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
574 : :
575 [ - + # # ]: 12583 : assert(ctrlr != NULL);
576 : 12583 : nvme_ctrlr_lock(ctrlr);
577 : 12583 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
578 : 12583 : nvme_ctrlr_unlock(ctrlr);
579 : 12583 : }
580 : :
581 : : int
582 : 5455 : spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
583 : : {
584 : 14 : struct spdk_nvme_ctrlr *ctrlr;
585 : :
586 [ + + ]: 5455 : if (qpair == NULL) {
587 : 0 : return 0;
588 : : }
589 : :
590 [ + - + - ]: 5455 : ctrlr = qpair->ctrlr;
591 : :
592 [ + + - + ]: 5455 : if (qpair->in_completion_context) {
593 : : /*
594 : : * There are many cases where it is convenient to delete an io qpair in the context
595 : : * of that qpair's completion routine. To handle this properly, set a flag here
596 : : * so that the completion routine will perform an actual delete after the context
597 : : * unwinds.
598 : : */
599 [ # # ]: 0 : qpair->delete_after_completion_context = 1;
600 : 0 : return 0;
601 : : }
602 : :
603 [ + - ]: 5455 : qpair->destroy_in_progress = 1;
604 : :
605 : 5455 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
606 : :
607 [ + + + - : 5455 : if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) {
+ + + - +
- + - ]
608 [ + - + - : 2013 : spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair);
+ - + - ]
609 : 1 : }
610 : :
611 : : /* Do not retry. */
612 : 5455 : nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING);
613 : :
614 : : /* In the multi-process case, a process may call this function on a foreign
615 : : * I/O qpair (i.e. one that this process did not create) when that qpairs process
616 : : * exits unexpectedly. In that case, we must not try to abort any reqs associated
617 : : * with that qpair, since the callbacks will also be foreign to this process.
618 : : */
619 [ + - + - : 5455 : if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) {
- + ]
620 : 5455 : nvme_qpair_abort_all_queued_reqs(qpair);
621 : 1076 : }
622 : :
623 : 5455 : nvme_ctrlr_lock(ctrlr);
624 : :
625 : 5455 : nvme_ctrlr_proc_remove_io_qpair(qpair);
626 : :
627 [ + + + - : 5455 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
+ - + + +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - ]
628 [ + - + - ]: 5455 : spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id);
629 : :
630 : 5455 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
631 : 5455 : nvme_ctrlr_unlock(ctrlr);
632 : 5455 : return 0;
633 : 1076 : }
634 : :
635 : : static void
636 : 126 : nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
637 : : struct spdk_nvme_intel_log_page_directory *log_page_directory)
638 : : {
639 [ + + ]: 126 : if (log_page_directory == NULL) {
640 : 0 : return;
641 : : }
642 : :
643 [ + + + - : 126 : assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL);
+ - + - #
# ]
644 : :
645 [ + - + - : 126 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
+ - + - ]
646 : :
647 [ + + + - : 128 : if (log_page_directory->read_latency_log_len ||
+ + + + ]
648 [ + + + - ]: 17 : (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) {
649 [ + - + - : 115 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
+ - + - ]
650 : 4 : }
651 [ + + + - : 128 : if (log_page_directory->write_latency_log_len ||
+ + + + ]
652 [ + + + - ]: 17 : (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) {
653 [ + - + - : 115 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
+ - + - ]
654 : 4 : }
655 [ + + + - : 126 : if (log_page_directory->temperature_statistics_log_len) {
+ + ]
656 [ + - + - : 120 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
+ - + - ]
657 : 4 : }
658 [ + + + - : 126 : if (log_page_directory->smart_log_len) {
+ + ]
659 [ + - + - : 114 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
+ - + - ]
660 : 3 : }
661 [ + + + - : 126 : if (log_page_directory->marketing_description_log_len) {
+ + ]
662 [ + - + - : 114 : ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
+ - + - ]
663 : 3 : }
664 : 5 : }
665 : :
666 : : struct intel_log_pages_ctx {
667 : : struct spdk_nvme_intel_log_page_directory log_page_directory;
668 : : struct spdk_nvme_ctrlr *ctrlr;
669 : : };
670 : :
671 : : static void
672 : 114 : nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl)
673 : : {
674 : 114 : struct intel_log_pages_ctx *ctx = arg;
675 [ + - + - ]: 114 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
676 : :
677 [ + - + - : 114 : if (!spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
+ - ]
678 [ + - ]: 114 : nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory);
679 : 3 : }
680 : :
681 : 117 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
682 [ + - + - : 114 : ctrlr->opts.admin_timeout_ms);
+ - ]
683 : 114 : free(ctx);
684 : 114 : }
685 : :
686 : : static int
687 : 114 : nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
688 : : {
689 : 114 : int rc = 0;
690 : 1 : struct intel_log_pages_ctx *ctx;
691 : :
692 : 114 : ctx = calloc(1, sizeof(*ctx));
693 [ + + ]: 114 : if (!ctx) {
694 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
695 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
696 : 0 : return 0;
697 : : }
698 : :
699 [ + - + - ]: 114 : ctx->ctrlr = ctrlr;
700 : :
701 : 114 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY,
702 [ + - ]: 114 : SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory,
703 : : sizeof(struct spdk_nvme_intel_log_page_directory),
704 : 3 : 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx);
705 [ - + ]: 114 : if (rc != 0) {
706 : 0 : free(ctx);
707 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
708 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
709 : 0 : return 0;
710 : : }
711 : :
712 : 117 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES,
713 [ - + - + : 114 : ctrlr->opts.admin_timeout_ms);
- + ]
714 : :
715 : 114 : return 0;
716 : 3 : }
717 : :
718 : : static int
719 : 33 : nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
720 : : {
721 : 4 : uint32_t ana_log_page_size;
722 : :
723 [ + - + - : 37 : ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid *
+ - ]
724 [ + - + - ]: 33 : sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count *
725 : : sizeof(uint32_t);
726 : :
727 : : /* Number of active namespaces may have changed.
728 : : * Check if ANA log page fits into existing buffer.
729 : : */
730 [ + - + - : 33 : if (ana_log_page_size > ctrlr->ana_log_page_size) {
- + ]
731 : 4 : void *new_buffer;
732 : :
733 [ + + + - : 33 : if (ctrlr->ana_log_page) {
+ + ]
734 [ + - + - ]: 6 : new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size);
735 : 1 : } else {
736 : 27 : new_buffer = calloc(1, ana_log_page_size);
737 : : }
738 : :
739 [ + + ]: 33 : if (!new_buffer) {
740 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n",
# # # # #
# # # # #
# # # # #
# # # #
# ]
741 : : ana_log_page_size);
742 : 0 : return -ENXIO;
743 : : }
744 : :
745 [ + - + - ]: 33 : ctrlr->ana_log_page = new_buffer;
746 [ + + + - : 33 : if (ctrlr->copied_ana_desc) {
+ + ]
747 [ + - + - ]: 6 : new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size);
748 : 1 : } else {
749 : 27 : new_buffer = calloc(1, ana_log_page_size);
750 : : }
751 : :
752 [ + + ]: 33 : if (!new_buffer) {
753 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n",
# # # # #
# # # # #
# # # # #
# # # #
# ]
754 : : ana_log_page_size);
755 : 0 : return -ENOMEM;
756 : : }
757 : :
758 [ + - + - ]: 33 : ctrlr->copied_ana_desc = new_buffer;
759 [ + - + - ]: 33 : ctrlr->ana_log_page_size = ana_log_page_size;
760 [ - + ]: 4 : }
761 : :
762 : 33 : return 0;
763 : 4 : }
764 : :
765 : : static int
766 : 33 : nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
767 : : {
768 : 4 : struct nvme_completion_poll_status *status;
769 : 4 : int rc;
770 : :
771 : 33 : rc = nvme_ctrlr_alloc_ana_log_page(ctrlr);
772 [ - + ]: 33 : if (rc != 0) {
773 : 0 : return rc;
774 : : }
775 : :
776 : 33 : status = calloc(1, sizeof(*status));
777 [ + + ]: 33 : if (status == NULL) {
778 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
779 : 0 : return -ENOMEM;
780 : : }
781 : :
782 : 37 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS,
783 [ + - + - ]: 33 : SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page,
784 [ + - + - ]: 4 : ctrlr->ana_log_page_size, 0,
785 : 4 : nvme_completion_poll_cb, status);
786 [ - + ]: 33 : if (rc != 0) {
787 : 0 : free(status);
788 : 0 : return rc;
789 : : }
790 : :
791 [ + + + - : 37 : if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock,
+ - - + ]
792 [ + - + - : 33 : ctrlr->opts.admin_timeout_ms * 1000)) {
+ - ]
793 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
794 : 0 : free(status);
795 : 0 : }
796 : 0 : return -EIO;
797 : : }
798 : :
799 : 33 : free(status);
800 : 33 : return 0;
801 : 4 : }
802 : :
803 : : static int
804 : 39 : nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc,
805 : : void *cb_arg)
806 : : {
807 : 39 : struct spdk_nvme_ctrlr *ctrlr = cb_arg;
808 : 5 : struct spdk_nvme_ns *ns;
809 : 5 : uint32_t i, nsid;
810 : :
811 [ + + + - : 102 : for (i = 0; i < desc->num_of_nsid; i++) {
+ + ]
812 [ + - + - : 63 : nsid = desc->nsid[i];
+ - ]
813 [ + - + + : 63 : if (nsid == 0 || nsid > ctrlr->cdata.nn) {
+ - + - -
+ ]
814 : 0 : continue;
815 : : }
816 : :
817 : 63 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
818 [ - + # # ]: 63 : assert(ns != NULL);
819 : :
820 [ + - + - : 63 : ns->ana_group_id = desc->ana_group_id;
+ - + - ]
821 [ + - + - : 63 : ns->ana_state = desc->ana_state;
+ - ]
822 : 9 : }
823 : :
824 : 39 : return 0;
825 : 5 : }
826 : :
827 : : int
828 : 33 : nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr,
829 : : spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg)
830 : : {
831 : 4 : struct spdk_nvme_ana_group_descriptor *copied_desc;
832 : 4 : uint8_t *orig_desc;
833 : 4 : uint32_t i, desc_size, copy_len;
834 : 33 : int rc = 0;
835 : :
836 [ + + + - : 33 : if (ctrlr->ana_log_page == NULL) {
+ - ]
837 : 0 : return -EINVAL;
838 : : }
839 : :
840 [ + - + - ]: 33 : copied_desc = ctrlr->copied_ana_desc;
841 : :
842 [ + - + - : 33 : orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page);
+ - ]
843 [ + - + - ]: 33 : copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page);
844 : :
845 [ + + + - : 72 : for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) {
+ - + - +
+ ]
846 [ + + + + ]: 39 : memcpy(copied_desc, orig_desc, copy_len);
847 : :
848 [ - + + - ]: 39 : rc = cb_fn(copied_desc, cb_arg);
849 [ + + ]: 39 : if (rc != 0) {
850 : 0 : break;
851 : : }
852 : :
853 : 39 : desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) +
854 [ + - + - ]: 39 : copied_desc->num_of_nsid * sizeof(uint32_t);
855 [ + - ]: 39 : orig_desc += desc_size;
856 : 39 : copy_len -= desc_size;
857 : 5 : }
858 : :
859 : 33 : return rc;
860 : 4 : }
861 : :
862 : : static int
863 : 2735 : nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
864 : : {
865 : 2735 : int rc = 0;
866 : :
867 [ + + + - ]: 2735 : memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
868 : : /* Mandatory pages */
869 [ + - + - : 2735 : ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
+ - + - ]
870 [ + - + - : 2735 : ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
+ - + - ]
871 [ + - + - : 2735 : ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
+ - + - ]
872 [ + + + - : 2735 : if (ctrlr->cdata.lpa.celp) {
+ - + + ]
873 [ + - + - : 2645 : ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
+ - + - ]
874 : 1063 : }
875 : :
876 [ + + + - : 2735 : if (ctrlr->cdata.cmic.ana_reporting) {
+ - + + ]
877 [ + - + - : 27 : ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true;
+ - + - ]
878 [ + + + + : 27 : if (!ctrlr->opts.disable_read_ana_log_page) {
+ - + - -
+ ]
879 : 21 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
880 [ + + ]: 21 : if (rc == 0) {
881 : 23 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
882 : 2 : ctrlr);
883 : 2 : }
884 : 2 : }
885 : 2 : }
886 : :
887 [ + + + - : 2735 : if (ctrlr->cdata.ctratt.fdps) {
+ - + - ]
888 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true;
# # # # ]
889 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true;
# # # # ]
890 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true;
# # # # ]
891 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true;
# # # # ]
892 : 0 : }
893 : :
894 [ + + + - : 2738 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL &&
+ - + + -
+ ]
895 [ + + + - : 1966 : ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE &&
+ - + + ]
896 [ + - + - ]: 114 : !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) {
897 : 117 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES,
898 [ + - + - : 114 : ctrlr->opts.admin_timeout_ms);
+ - ]
899 : :
900 : 3 : } else {
901 : 3696 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
902 [ + - + - : 2621 : ctrlr->opts.admin_timeout_ms);
+ - ]
903 : :
904 : : }
905 : :
906 : 2751 : return rc;
907 : 16 : }
908 : :
909 : : static void
910 : 1966 : nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
911 : : {
912 [ + - + - : 1966 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
+ - + - ]
913 [ + - + - : 1966 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
+ - + - ]
914 [ + - + - : 1966 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
+ - + - ]
915 [ + - + - : 1966 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
+ - + - ]
916 [ + - + - : 1966 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
+ - + - ]
917 [ + - + - : 1966 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
+ - + - ]
918 [ + - + - : 1966 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
+ - + - ]
919 : 1966 : }
920 : :
921 : : static void
922 : 2747 : nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr)
923 : : {
924 : 18 : uint32_t cdw11;
925 : 18 : struct nvme_completion_poll_status *status;
926 : :
927 [ + + + - : 2747 : if (ctrlr->opts.arbitration_burst == 0) {
+ - + + ]
928 : 2735 : return;
929 : : }
930 : :
931 [ + + + - : 12 : if (ctrlr->opts.arbitration_burst > 7) {
+ - + + ]
932 [ + - + + : 6 : NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
933 : 6 : return;
934 : : }
935 : :
936 : 6 : status = calloc(1, sizeof(*status));
937 [ + + ]: 6 : if (!status) {
938 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
939 : 0 : return;
940 : : }
941 : :
942 [ + - + - : 6 : cdw11 = ctrlr->opts.arbitration_burst;
+ - ]
943 : :
944 [ + + ]: 6 : if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) {
945 [ + - + - : 6 : cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8;
+ - + - ]
946 [ + - + - : 6 : cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16;
+ - + - ]
947 [ + - + - : 6 : cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24;
+ - + - ]
948 : 1 : }
949 : :
950 [ + + + - : 8 : if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION,
+ - ]
951 : 1 : cdw11, 0, NULL, 0,
952 : 2 : nvme_completion_poll_cb, status) < 0) {
953 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
954 : 0 : free(status);
955 : 0 : return;
956 : : }
957 : :
958 [ + + + - : 7 : if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
+ - ]
959 [ + - + - : 6 : ctrlr->opts.admin_timeout_ms * 1000)) {
+ - ]
960 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
961 : 0 : }
962 : :
963 [ + + + - : 6 : if (!status->timed_out) {
+ - - + ]
964 : 6 : free(status);
965 : 1 : }
966 [ - + ]: 1080 : }
967 : :
968 : : static void
969 : 2735 : nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
970 : : {
971 [ + + + - ]: 2735 : memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
972 : : /* Mandatory features */
973 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
+ - + - ]
974 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
+ - + - ]
975 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
+ - + - ]
976 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
+ - + - ]
977 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
+ - + - ]
978 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
+ - + - ]
979 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
+ - + - ]
980 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
+ - + - ]
981 [ + - + - : 2735 : ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
+ - + - ]
982 : : /* Optional features */
983 [ + + + - : 2735 : if (ctrlr->cdata.vwc.present) {
+ - + + ]
984 [ + - + - : 2509 : ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
+ - + - ]
985 : 1060 : }
986 [ + + + - : 2735 : if (ctrlr->cdata.apsta.supported) {
+ - + - ]
987 [ # # # # : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
# # # # ]
988 : 0 : }
989 [ + + + - : 2735 : if (ctrlr->cdata.hmpre) {
+ - + - ]
990 [ # # # # : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
# # # # ]
991 : 0 : }
992 [ + + + - : 2735 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
+ - + + ]
993 : 1966 : nvme_ctrlr_set_intel_supported_features(ctrlr);
994 : 1056 : }
995 : :
996 : 2735 : nvme_ctrlr_set_arbitration_feature(ctrlr);
997 : 2735 : }
998 : :
999 : : bool
1000 : 155934 : spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr)
1001 : : {
1002 [ - + # # : 155934 : return ctrlr->is_failed;
# # ]
1003 : : }
1004 : :
1005 : : void
1006 : 520 : nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
1007 : : {
1008 : : /*
1009 : : * Set the flag here and leave the work failure of qpairs to
1010 : : * spdk_nvme_qpair_process_completions().
1011 : : */
1012 [ + + + - ]: 520 : if (hot_remove) {
1013 [ # # # # ]: 39 : ctrlr->is_removed = true;
1014 : 0 : }
1015 : :
1016 [ + + + + : 520 : if (ctrlr->is_failed) {
+ - - + ]
1017 [ + + + + : 14 : NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1018 : 14 : return;
1019 : : }
1020 : :
1021 [ + + + + : 506 : if (ctrlr->is_disconnecting) {
+ - - + ]
1022 [ - + - + : 9 : NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n");
- - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1023 : 9 : return;
1024 : : }
1025 : :
1026 [ + - + - ]: 497 : ctrlr->is_failed = true;
1027 : 497 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1028 [ + - + - ]: 497 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1029 [ + + + + : 497 : NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
1030 : 1 : }
1031 : :
1032 : : /**
1033 : : * This public API function will try to take the controller lock.
1034 : : * Any private functions being called from a thread already holding
1035 : : * the ctrlr lock should call nvme_ctrlr_fail directly.
1036 : : */
1037 : : void
1038 : 27 : spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
1039 : : {
1040 : 27 : nvme_ctrlr_lock(ctrlr);
1041 : 27 : nvme_ctrlr_fail(ctrlr, false);
1042 : 27 : nvme_ctrlr_unlock(ctrlr);
1043 : 27 : }
1044 : :
1045 : : static void
1046 : 2795 : nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1047 : : {
1048 : 2795 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1049 [ + - + - ]: 2795 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1050 : :
1051 [ + - + + : 2795 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1052 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1053 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1054 : 0 : return;
1055 : : }
1056 : :
1057 [ + + + + : 2795 : if (ctrlr->opts.no_shn_notification) {
+ - + - -
+ ]
1058 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1059 : 0 : return;
1060 : : }
1061 : :
1062 : : /*
1063 : : * The NVMe specification defines RTD3E to be the time between
1064 : : * setting SHN = 1 until the controller will set SHST = 10b.
1065 : : * If the device doesn't report RTD3 entry latency, or if it
1066 : : * reports RTD3 entry latency less than 10 seconds, pick
1067 : : * 10 seconds as a reasonable amount of time to
1068 : : * wait before proceeding.
1069 : : */
1070 [ + + + + : 2795 : NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1071 [ + - + - : 2795 : ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000);
+ - + - +
- + - ]
1072 [ + - + - : 2795 : ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000);
- + # # #
# + - +
- ]
1073 [ + + + + : 2795 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
1074 : :
1075 [ + - + - ]: 2795 : ctx->shutdown_start_tsc = spdk_get_ticks();
1076 [ + - + - ]: 2795 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1077 [ - + ]: 1100 : }
1078 : :
1079 : : static void
1080 : 2795 : nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1081 : : {
1082 : 2795 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1083 [ + - + - ]: 2795 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1084 : 38 : union spdk_nvme_cc_register cc;
1085 : 38 : int rc;
1086 : :
1087 [ + - + + : 2795 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1088 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1089 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1090 : 0 : return;
1091 : : }
1092 : :
1093 [ + + # # ]: 2795 : assert(value <= UINT32_MAX);
1094 : 2795 : cc.raw = (uint32_t)value;
1095 : :
1096 [ + + + + : 2795 : if (ctrlr->opts.no_shn_notification) {
+ - + - -
+ ]
1097 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1098 [ # # ]: 0 : if (cc.bits.en == 0) {
1099 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1100 : 0 : return;
1101 : : }
1102 : :
1103 : 0 : cc.bits.en = 0;
1104 : 0 : } else {
1105 : 2795 : cc.bits.shn = SPDK_NVME_SHN_NORMAL;
1106 : : }
1107 : :
1108 : 2795 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx);
1109 [ + + ]: 2795 : if (rc != 0) {
1110 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1111 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1112 : 0 : }
1113 [ - + ]: 1100 : }
1114 : :
1115 : : static void
1116 : 2920 : nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr,
1117 : : struct nvme_ctrlr_detach_ctx *ctx)
1118 : : {
1119 : 46 : int rc;
1120 : :
1121 [ + + + + : 2920 : if (ctrlr->is_removed) {
+ - - + ]
1122 [ # # # # ]: 36 : ctx->shutdown_complete = true;
1123 : 36 : return;
1124 : : }
1125 : :
1126 [ + + + - : 3985 : if (ctrlr->adminq == NULL ||
+ + + + ]
1127 [ + + + - : 2842 : ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) {
+ - ]
1128 [ + + + + : 86 : NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1129 [ + - + - ]: 86 : ctx->shutdown_complete = true;
1130 : 86 : return;
1131 : : }
1132 : :
1133 [ + - + - ]: 2798 : ctx->state = NVME_CTRLR_DETACH_SET_CC;
1134 : 2798 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx);
1135 [ + + ]: 2798 : if (rc != 0) {
1136 [ - + - - : 3 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1137 [ # # # # ]: 3 : ctx->shutdown_complete = true;
1138 : 0 : }
1139 [ - + ]: 1108 : }
1140 : :
1141 : : static void
1142 : 6055497 : nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1143 : : {
1144 : 6055497 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1145 : :
1146 [ + - + + : 6055497 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1147 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1148 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1149 : 0 : return;
1150 : : }
1151 : :
1152 [ + + # # ]: 6055497 : assert(value <= UINT32_MAX);
1153 [ + - + - : 6055497 : ctx->csts.raw = (uint32_t)value;
+ - ]
1154 [ + - + - ]: 6055497 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE;
1155 [ - + ]: 402714 : }
1156 : :
1157 : : static int
1158 : 19139971 : nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr,
1159 : : struct nvme_ctrlr_detach_ctx *ctx)
1160 : : {
1161 : 76 : union spdk_nvme_csts_register csts;
1162 : 76 : uint32_t ms_waited;
1163 : :
1164 [ + + + - : 19139971 : switch (ctx->state) {
- + + + ]
1165 : 6593482 : case NVME_CTRLR_DETACH_SET_CC:
1166 : : case NVME_CTRLR_DETACH_GET_CSTS:
1167 : : /* We're still waiting for the register operation to complete */
1168 [ + - + - ]: 7028977 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
1169 : 7028977 : return -EAGAIN;
1170 : :
1171 : 5652783 : case NVME_CTRLR_DETACH_CHECK_CSTS:
1172 [ + - + - ]: 6055497 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS;
1173 [ - + ]: 6055497 : if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) {
1174 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1175 : 0 : return -EIO;
1176 : : }
1177 : 6055497 : return -EAGAIN;
1178 : :
1179 : 5652783 : case NVME_CTRLR_DETACH_GET_CSTS_DONE:
1180 [ + - + - ]: 6055497 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1181 : 6055497 : break;
1182 : :
1183 : 0 : default:
1184 [ # # ]: 0 : assert(0 && "Should never happen");
1185 : : return -EINVAL;
1186 : : }
1187 : :
1188 [ + + + - : 6055497 : ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz();
+ - ]
1189 [ + - + - : 6055497 : csts.raw = ctx->csts.raw;
+ - ]
1190 : :
1191 [ + + ]: 6055497 : if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
1192 [ + + + + : 2795 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1193 : 2795 : return 0;
1194 : : }
1195 : :
1196 [ + - + - : 6052702 : if (ms_waited < ctx->shutdown_timeout_ms) {
+ - ]
1197 : 6052702 : return -EAGAIN;
1198 : : }
1199 : :
1200 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
1201 : : ctx->shutdown_timeout_ms);
1202 [ # # # # : 0 : if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) {
# # ]
1203 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1204 : 0 : }
1205 : :
1206 : 0 : return 0;
1207 : 1240923 : }
1208 : :
1209 : : static inline uint64_t
1210 : 4554863 : nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr)
1211 : : {
1212 [ + - + - : 4554863 : return ctrlr->cap.bits.to * 500;
+ - + - ]
1213 : : }
1214 : :
1215 : : static void
1216 : 2845 : nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1217 : : {
1218 : 2845 : struct spdk_nvme_ctrlr *ctrlr = ctx;
1219 : :
1220 [ + - + + : 2845 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
+ + ]
1221 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1222 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1223 : 0 : return;
1224 : : }
1225 : :
1226 : 3921 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
1227 : 1076 : nvme_ctrlr_get_ready_timeout(ctrlr));
1228 [ - + ]: 1076 : }
1229 : :
1230 : : static int
1231 : 2887 : nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
1232 : : {
1233 : 21 : union spdk_nvme_cc_register cc;
1234 : 21 : int rc;
1235 : :
1236 : 2887 : rc = nvme_transport_ctrlr_enable(ctrlr);
1237 [ - + ]: 2887 : if (rc != 0) {
1238 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1239 : 0 : return rc;
1240 : : }
1241 : :
1242 [ + - + - : 2887 : cc.raw = ctrlr->process_init_cc.raw;
+ - ]
1243 [ - + ]: 2887 : if (cc.bits.en != 0) {
1244 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1245 : 0 : return -EINVAL;
1246 : : }
1247 : :
1248 : 2887 : cc.bits.en = 1;
1249 : 2887 : cc.bits.css = 0;
1250 : 2887 : cc.bits.shn = 0;
1251 : 2887 : cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
1252 : 2887 : cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
1253 : :
1254 : : /* Page size is 2 ^ (12 + mps). */
1255 [ + - + - ]: 2887 : cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12;
1256 : :
1257 : : /*
1258 : : * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS.
1259 : : * A controller that does not have any bit set in CAP.CSS is not spec compliant.
1260 : : * Try to support such a controller regardless.
1261 : : */
1262 [ + + + - : 2887 : if (ctrlr->cap.bits.css == 0) {
+ - + + ]
1263 [ + + + + : 126 : NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1264 [ + - + - : 126 : ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM;
+ - + - ]
1265 : 21 : }
1266 : :
1267 : : /*
1268 : : * If the user did not explicitly request a command set, or supplied a value larger than
1269 : : * what can be saved in CC.CSS, use the most reasonable default.
1270 : : */
1271 [ + + + - : 2887 : if (ctrlr->opts.command_set >= CHAR_BIT) {
+ - + + ]
1272 [ + + + - : 2635 : if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) {
+ - + - -
+ ]
1273 [ # # # # : 543 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS;
# # ]
1274 [ + - + - : 2092 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) {
+ - + - +
- ]
1275 [ + - + - : 2092 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
+ - ]
1276 [ # # # # : 1062 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) {
# # # # #
# ]
1277 [ # # # # : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NOIO;
# # ]
1278 : 0 : } else {
1279 : : /* Invalid supported bits detected, falling back to NVM. */
1280 [ # # # # : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
# # ]
1281 : : }
1282 : 1062 : }
1283 : :
1284 : : /* Verify that the selected command set is supported by the controller. */
1285 [ + + + + : 2887 : if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) {
+ - + - +
- + - + -
- + ]
1286 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
1287 : : ctrlr->opts.command_set, ctrlr->cap.bits.css);
1288 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1289 [ # # # # : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
# # ]
1290 : 0 : }
1291 : :
1292 [ + - + - : 2887 : cc.bits.css = ctrlr->opts.command_set;
+ - ]
1293 : :
1294 [ + + + + : 2887 : switch (ctrlr->opts.arb_mechanism) {
+ - + + +
+ ]
1295 : 1749 : case SPDK_NVME_CC_AMS_RR:
1296 : 2821 : break;
1297 : 20 : case SPDK_NVME_CC_AMS_WRR:
1298 [ + + + - : 24 : if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) {
+ - + + ]
1299 : 12 : break;
1300 : : }
1301 : 12 : return -EINVAL;
1302 : 20 : case SPDK_NVME_CC_AMS_VS:
1303 [ + + + - : 24 : if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) {
+ - + + ]
1304 : 12 : break;
1305 : : }
1306 : 12 : return -EINVAL;
1307 : 15 : default:
1308 : 18 : return -EINVAL;
1309 : : }
1310 : :
1311 [ + - + - : 2845 : cc.bits.ams = ctrlr->opts.arb_mechanism;
+ - ]
1312 [ + - + - : 2845 : ctrlr->process_init_cc.raw = cc.raw;
+ - ]
1313 : :
1314 [ - + ]: 2845 : if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) {
1315 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1316 : 0 : return -EIO;
1317 : : }
1318 : :
1319 : 2845 : return 0;
1320 : 1083 : }
1321 : :
1322 : : static const char *
1323 : 306 : nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
1324 : : {
1325 [ - + + + : 306 : switch (state) {
+ + + + +
- - - - +
- + + + +
- + + + +
+ + + + -
- - + + +
+ + + + +
+ - + - -
+ + - + -
+ + + +
- ]
1326 : 0 : case NVME_CTRLR_STATE_INIT_DELAY:
1327 : 0 : return "delay init";
1328 : 10 : case NVME_CTRLR_STATE_CONNECT_ADMINQ:
1329 : 10 : return "connect adminq";
1330 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
1331 : 10 : return "wait for connect adminq";
1332 : 10 : case NVME_CTRLR_STATE_READ_VS:
1333 : 10 : return "read vs";
1334 : 10 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
1335 : 10 : return "read vs wait for vs";
1336 : 10 : case NVME_CTRLR_STATE_READ_CAP:
1337 : 10 : return "read cap";
1338 : 10 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
1339 : 10 : return "read cap wait for cap";
1340 : 10 : case NVME_CTRLR_STATE_CHECK_EN:
1341 : 10 : return "check en";
1342 : 10 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
1343 : 10 : return "check en wait for cc";
1344 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
1345 : 0 : return "disable and wait for CSTS.RDY = 1";
1346 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1347 : 0 : return "disable and wait for CSTS.RDY = 1 reg";
1348 : 0 : case NVME_CTRLR_STATE_SET_EN_0:
1349 : 0 : return "set CC.EN = 0";
1350 : 0 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
1351 : 0 : return "set CC.EN = 0 wait for cc";
1352 : 10 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
1353 : 10 : return "disable and wait for CSTS.RDY = 0";
1354 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
1355 : 0 : return "disable and wait for CSTS.RDY = 0 reg";
1356 : 10 : case NVME_CTRLR_STATE_DISABLED:
1357 : 10 : return "controller is disabled";
1358 : 10 : case NVME_CTRLR_STATE_ENABLE:
1359 : 10 : return "enable controller by writing CC.EN = 1";
1360 : 10 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
1361 : 10 : return "enable controller by writing CC.EN = 1 reg";
1362 : 10 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
1363 : 10 : return "wait for CSTS.RDY = 1";
1364 : 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1365 : 0 : return "wait for CSTS.RDY = 1 reg";
1366 : 10 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
1367 : 10 : return "reset admin queue";
1368 : 10 : case NVME_CTRLR_STATE_IDENTIFY:
1369 : 10 : return "identify controller";
1370 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
1371 : 10 : return "wait for identify controller";
1372 : 10 : case NVME_CTRLR_STATE_CONFIGURE_AER:
1373 : 10 : return "configure AER";
1374 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
1375 : 10 : return "wait for configure aer";
1376 : 10 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
1377 : 10 : return "set keep alive timeout";
1378 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
1379 : 10 : return "wait for set keep alive timeout";
1380 : 6 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
1381 : 6 : return "identify controller iocs specific";
1382 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
1383 : 0 : return "wait for identify controller iocs specific";
1384 : 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
1385 : 0 : return "get zns cmd and effects log page";
1386 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
1387 : 0 : return "wait for get zns cmd and effects log page";
1388 : 6 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
1389 : 6 : return "set number of queues";
1390 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
1391 : 6 : return "wait for set number of queues";
1392 : 6 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
1393 : 6 : return "identify active ns";
1394 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
1395 : 6 : return "wait for identify active ns";
1396 : 6 : case NVME_CTRLR_STATE_IDENTIFY_NS:
1397 : 6 : return "identify ns";
1398 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
1399 : 6 : return "wait for identify ns";
1400 : 6 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
1401 : 6 : return "identify namespace id descriptors";
1402 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
1403 : 6 : return "wait for identify namespace id descriptors";
1404 : 6 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
1405 : 6 : return "identify ns iocs specific";
1406 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
1407 : 0 : return "wait for identify ns iocs specific";
1408 : 6 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
1409 : 6 : return "set supported log pages";
1410 : 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
1411 : 0 : return "set supported INTEL log pages";
1412 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
1413 : 0 : return "wait for supported INTEL log pages";
1414 : 6 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
1415 : 6 : return "set supported features";
1416 : 6 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
1417 : 6 : return "set doorbell buffer config";
1418 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
1419 : 0 : return "wait for doorbell buffer config";
1420 : 6 : case NVME_CTRLR_STATE_SET_HOST_ID:
1421 : 6 : return "set host ID";
1422 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
1423 : 0 : return "wait for set host ID";
1424 : 6 : case NVME_CTRLR_STATE_TRANSPORT_READY:
1425 : 6 : return "transport ready";
1426 : 10 : case NVME_CTRLR_STATE_READY:
1427 : 10 : return "ready";
1428 : 5 : case NVME_CTRLR_STATE_ERROR:
1429 : 6 : return "error";
1430 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
1431 : 0 : return "disconnected";
1432 : : }
1433 : 0 : return "unknown";
1434 : 1 : };
1435 : :
1436 : : static void
1437 : 180187 : _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1438 : : uint64_t timeout_in_ms, bool quiet)
1439 : : {
1440 : 714 : uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
1441 : :
1442 [ + - + - ]: 180187 : ctrlr->state = state;
1443 [ + + ]: 180187 : if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) {
1444 [ + + + - ]: 70903 : if (!quiet) {
1445 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
1446 : : nvme_ctrlr_state_string(ctrlr->state));
1447 : 0 : }
1448 : 70903 : return;
1449 : : }
1450 : :
1451 [ + + ]: 109284 : if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
1452 : 31999 : goto inf;
1453 : : }
1454 : :
1455 [ + - ]: 77285 : ticks_per_ms = spdk_get_ticks_hz() / 1000;
1456 [ + + - + ]: 77285 : if (timeout_in_ms > UINT64_MAX / ticks_per_ms) {
1457 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr,
# # # # #
# # # # #
# # # # #
# # # #
# ]
1458 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1459 : 0 : goto inf;
1460 : : }
1461 : :
1462 : 77285 : now_ticks = spdk_get_ticks();
1463 : 77285 : timeout_in_ticks = timeout_in_ms * ticks_per_ms;
1464 [ + + ]: 77285 : if (timeout_in_ticks > UINT64_MAX - now_ticks) {
1465 [ + - + + : 6 : NVME_CTRLR_ERRLOG(ctrlr,
+ - + - +
- + - + -
- + # # #
# + - +
- ]
1466 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1467 : 6 : goto inf;
1468 : : }
1469 : :
1470 [ + - + - ]: 77279 : ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
1471 [ + - - + ]: 77279 : if (!quiet) {
1472 [ + + + + : 77279 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n",
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
1473 : : nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
1474 : 28675 : }
1475 : 77279 : return;
1476 : 21765 : inf:
1477 [ + - - + ]: 32005 : if (!quiet) {
1478 [ + + + + : 32005 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n",
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
1479 : : nvme_ctrlr_state_string(ctrlr->state));
1480 : 10240 : }
1481 [ + - + - ]: 32005 : ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
1482 [ - + ]: 46858 : }
1483 : :
1484 : : static void
1485 : 109284 : nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1486 : : uint64_t timeout_in_ms)
1487 : : {
1488 : 109284 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false);
1489 : 109284 : }
1490 : :
1491 : : static void
1492 : 70903 : nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1493 : : uint64_t timeout_in_ms)
1494 : : {
1495 : 70903 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true);
1496 : 70903 : }
1497 : :
1498 : : static void
1499 : 3473 : nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1500 : : {
1501 [ + - + - ]: 3473 : spdk_free(ctrlr->cdata_zns);
1502 [ + - + - ]: 3473 : ctrlr->cdata_zns = NULL;
1503 : 3473 : }
1504 : :
1505 : : static void
1506 : 3473 : nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1507 : : {
1508 : 3473 : nvme_ctrlr_free_zns_specific_data(ctrlr);
1509 : 3473 : }
1510 : :
1511 : : static void
1512 : 3479 : nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr)
1513 : : {
1514 [ + + + - : 3479 : if (ctrlr->shadow_doorbell) {
+ + ]
1515 [ + - + - ]: 608 : spdk_free(ctrlr->shadow_doorbell);
1516 [ + - + - ]: 608 : ctrlr->shadow_doorbell = NULL;
1517 : 1 : }
1518 : :
1519 [ + + + - : 3479 : if (ctrlr->eventidx) {
+ + ]
1520 [ + - + - ]: 608 : spdk_free(ctrlr->eventidx);
1521 [ + - + - ]: 608 : ctrlr->eventidx = NULL;
1522 : 1 : }
1523 : 3479 : }
1524 : :
1525 : : static void
1526 : 612 : nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl)
1527 : : {
1528 : 612 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1529 : :
1530 [ + - + + : 612 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
+ - ]
1531 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1532 : 0 : } else {
1533 [ + + + + : 612 : NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1534 : : }
1535 : 613 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1536 [ + - + - : 612 : ctrlr->opts.admin_timeout_ms);
+ - ]
1537 : 612 : }
1538 : :
1539 : : static int
1540 : 2729 : nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr)
1541 : : {
1542 : 2729 : int rc = 0;
1543 : 459 : uint64_t prp1, prp2, len;
1544 : :
1545 [ + + + - : 2729 : if (!ctrlr->cdata.oacs.doorbell_buffer_config) {
+ - + + ]
1546 : 3193 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1547 [ + - + - : 2117 : ctrlr->opts.admin_timeout_ms);
+ - ]
1548 : 2117 : return 0;
1549 : : }
1550 : :
1551 [ + + + - : 612 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
+ - - + ]
1552 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1553 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
1554 : 0 : return 0;
1555 : : }
1556 : :
1557 : : /* only 1 page size for doorbell buffer */
1558 [ + - + - : 612 : ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
+ - + - +
- + - ]
1559 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1560 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1561 [ + + + - : 612 : if (ctrlr->shadow_doorbell == NULL) {
- + ]
1562 : 0 : rc = -ENOMEM;
1563 : 0 : goto error;
1564 : : }
1565 : :
1566 [ + - + - ]: 612 : len = ctrlr->page_size;
1567 [ + - + - ]: 612 : prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len);
1568 [ + - + + : 612 : if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
+ - - + ]
1569 : 0 : rc = -EFAULT;
1570 : 0 : goto error;
1571 : : }
1572 : :
1573 [ + - + - : 612 : ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
+ - + - +
- + - ]
1574 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1575 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1576 [ + + + - : 612 : if (ctrlr->eventidx == NULL) {
+ - ]
1577 : 0 : rc = -ENOMEM;
1578 : 0 : goto error;
1579 : : }
1580 : :
1581 [ + - + - ]: 612 : len = ctrlr->page_size;
1582 [ + - + - ]: 612 : prp2 = spdk_vtophys(ctrlr->eventidx, &len);
1583 [ + - + + : 612 : if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
+ - - + ]
1584 : 0 : rc = -EFAULT;
1585 : 0 : goto error;
1586 : : }
1587 : :
1588 : 613 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG,
1589 [ - + - + : 612 : ctrlr->opts.admin_timeout_ms);
- + ]
1590 : :
1591 : 613 : rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2,
1592 : 1 : nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr);
1593 [ - + ]: 612 : if (rc != 0) {
1594 : 0 : goto error;
1595 : : }
1596 : :
1597 : 612 : return 0;
1598 : :
1599 : 0 : error:
1600 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1601 : 0 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1602 : 0 : return rc;
1603 : 1077 : }
1604 : :
1605 : : void
1606 : 5634 : nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr)
1607 : : {
1608 : 47 : struct nvme_request *req, *tmp;
1609 : 5634 : struct spdk_nvme_cpl cpl = {};
1610 : :
1611 [ + - + - ]: 5634 : cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION;
1612 [ + - + - ]: 5634 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
1613 : :
1614 [ + + + - : 5634 : STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) {
+ - + - #
# # # # #
+ - ]
1615 [ # # # # : 0 : STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1616 [ # # ]: 0 : ctrlr->outstanding_aborts++;
1617 : :
1618 [ # # # # : 0 : nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl);
# # # # #
# # # ]
1619 : 0 : }
1620 : 5634 : }
1621 : :
1622 : : static int
1623 : 559 : nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1624 : : {
1625 [ + + + + : 559 : if (ctrlr->is_resetting || ctrlr->is_removed) {
+ + + + +
- + - + -
- + ]
1626 : : /*
1627 : : * Controller is already resetting or has been removed. Return
1628 : : * immediately since there is no need to kick off another
1629 : : * reset in these cases.
1630 : : */
1631 [ + + + - : 6 : return ctrlr->is_resetting ? -EBUSY : -ENXIO;
+ - ]
1632 : : }
1633 : :
1634 [ + - + - ]: 553 : ctrlr->is_resetting = true;
1635 [ + - + - ]: 553 : ctrlr->is_failed = false;
1636 [ + - + - ]: 553 : ctrlr->is_disconnecting = true;
1637 [ + - + - ]: 553 : ctrlr->prepare_for_reset = true;
1638 : :
1639 [ + + + + : 553 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
1640 : :
1641 : : /* Disable keep-alive, it'll be re-enabled as part of the init process */
1642 [ + - + - ]: 553 : ctrlr->keep_alive_interval_ticks = 0;
1643 : :
1644 : : /* Abort all of the queued abort requests */
1645 : 553 : nvme_ctrlr_abort_queued_aborts(ctrlr);
1646 : :
1647 [ + - + - ]: 553 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
1648 : :
1649 [ + - + - : 553 : ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
+ - ]
1650 [ + - + - ]: 553 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1651 : :
1652 : 553 : return 0;
1653 : 2 : }
1654 : :
1655 : : static void
1656 : 553 : nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr)
1657 : : {
1658 [ + + + + : 553 : assert(ctrlr->is_failed == false);
+ - + - #
# ]
1659 [ + - + - ]: 553 : ctrlr->is_disconnecting = false;
1660 : :
1661 : : /* Doorbell buffer config is invalid during reset */
1662 : 553 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1663 : :
1664 : : /* I/O Command Set Specific Identify Controller data is invalidated during reset */
1665 : 553 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
1666 : :
1667 [ + - ]: 553 : spdk_bit_array_free(&ctrlr->free_io_qids);
1668 : :
1669 : : /* Set the state back to DISCONNECTED to cause a full hardware reset. */
1670 : 553 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE);
1671 : 553 : }
1672 : :
1673 : : int
1674 : 496 : spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1675 : : {
1676 : 0 : int rc;
1677 : :
1678 : 496 : nvme_ctrlr_lock(ctrlr);
1679 : 496 : rc = nvme_ctrlr_disconnect(ctrlr);
1680 : 496 : nvme_ctrlr_unlock(ctrlr);
1681 : :
1682 : 496 : return rc;
1683 : 0 : }
1684 : :
1685 : : void
1686 : 553 : spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr)
1687 : : {
1688 : 553 : nvme_ctrlr_lock(ctrlr);
1689 : :
1690 [ + - + - ]: 553 : ctrlr->prepare_for_reset = false;
1691 : :
1692 : : /* Set the state back to INIT to cause a full hardware reset. */
1693 : 553 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
1694 : :
1695 : : /* Return without releasing ctrlr_lock. ctrlr_lock will be released when
1696 : : * spdk_nvme_ctrlr_reset_poll_async() returns 0.
1697 : : */
1698 : 553 : }
1699 : :
1700 : : int
1701 : 29 : nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
1702 : : {
1703 : 0 : bool async;
1704 : 0 : int rc;
1705 : :
1706 [ + - + - : 58 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc ||
# # ]
1707 [ - + ]: 58 : spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) {
1708 [ # # ]: 0 : assert(false);
1709 : : return -EINVAL;
1710 : : }
1711 : :
1712 : : /* Force a synchronous connect. */
1713 [ # # ]: 29 : async = qpair->async;
1714 [ # # ]: 29 : qpair->async = false;
1715 : 29 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
1716 [ # # # # ]: 29 : qpair->async = async;
1717 : :
1718 [ - + ]: 29 : if (rc != 0) {
1719 [ # # ]: 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1720 : 0 : }
1721 : :
1722 : 29 : return rc;
1723 : 0 : }
1724 : :
1725 : : /**
1726 : : * This function will be called when the controller is being reinitialized.
1727 : : * Note: the ctrlr_lock must be held when calling this function.
1728 : : */
1729 : : int
1730 : 183007 : spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr)
1731 : : {
1732 : 24 : struct spdk_nvme_ns *ns, *tmp_ns;
1733 : 24 : struct spdk_nvme_qpair *qpair;
1734 : 183007 : int rc = 0, rc_tmp = 0;
1735 : :
1736 [ + + ]: 183007 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1737 [ + + + - : 421 : NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1738 : 421 : rc = -1;
1739 : 0 : }
1740 [ + + + + : 183007 : if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) {
+ + - + ]
1741 : 182454 : return -EAGAIN;
1742 : : }
1743 : :
1744 : : /*
1745 : : * For non-fabrics controllers, the memory locations of the transport qpair
1746 : : * don't change when the controller is reset. They simply need to be
1747 : : * re-enabled with admin commands to the controller. For fabric
1748 : : * controllers we need to disconnect and reconnect the qpair on its
1749 : : * own thread outside of the context of the reset.
1750 : : */
1751 [ + + + + ]: 553 : if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
1752 : : /* Reinitialize qpairs */
1753 [ + + + - : 121 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
+ - + - #
# # # #
# ]
1754 : : /* Always clear the qid bit here, even for a foreign qpair. We need
1755 : : * to make sure another process doesn't get the chance to grab that
1756 : : * qid.
1757 : : */
1758 [ - + # # : 29 : assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id));
# # # # #
# # # ]
1759 [ # # # # : 29 : spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id);
# # # # ]
1760 [ + + # # : 29 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) {
# # ]
1761 : : /*
1762 : : * We cannot reinitialize a foreign qpair. The qpair's owning
1763 : : * process will take care of it. Set failure reason to FAILURE_RESET
1764 : : * to ensure that happens.
1765 : : */
1766 [ # # ]: 23 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET;
1767 : 23 : continue;
1768 : : }
1769 : 6 : rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair);
1770 [ - + ]: 6 : if (rc_tmp != 0) {
1771 : 0 : rc = rc_tmp;
1772 : 0 : }
1773 : 0 : }
1774 : 1 : }
1775 : :
1776 : : /*
1777 : : * Take this opportunity to remove inactive namespaces. During a reset namespace
1778 : : * handles can be invalidated.
1779 : : */
1780 [ + + + + : 1176 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
+ + ]
1781 [ + + + + : 623 : if (!ns->active) {
+ - + + ]
1782 [ + - ]: 7 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
1783 : 7 : spdk_free(ns);
1784 : 1 : }
1785 : 4 : }
1786 : :
1787 [ + + ]: 553 : if (rc) {
1788 : 421 : nvme_ctrlr_fail(ctrlr, false);
1789 : 0 : }
1790 [ + - + - ]: 553 : ctrlr->is_resetting = false;
1791 : :
1792 : 553 : nvme_ctrlr_unlock(ctrlr);
1793 : :
1794 [ + + + - : 553 : if (!ctrlr->cdata.oaes.ns_attribute_notices) {
+ - - + ]
1795 : : /*
1796 : : * If controller doesn't support ns_attribute_notices and
1797 : : * namespace attributes change (e.g. number of namespaces)
1798 : : * we need to update system handling device reset.
1799 : : */
1800 : 18 : nvme_io_msg_ctrlr_update(ctrlr);
1801 : 1 : }
1802 : :
1803 : 553 : return rc;
1804 : 24 : }
1805 : :
1806 : : /*
1807 : : * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset
1808 : : * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair.
1809 : : * The following two functions are added to do a Controller Level Reset. They have
1810 : : * to be called under the nvme controller's lock.
1811 : : */
1812 : : void
1813 : 92 : nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
1814 : : {
1815 [ + + + + : 92 : assert(ctrlr->is_disconnecting == true);
+ - + - #
# ]
1816 : :
1817 : 92 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
1818 : 92 : }
1819 : :
1820 : : int
1821 : 1232 : nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr)
1822 : : {
1823 : 1232 : int rc = 0;
1824 : :
1825 [ + + ]: 1232 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1826 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1827 : 0 : rc = -1;
1828 : 0 : }
1829 : :
1830 [ + + + - : 1232 : if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) {
+ + + - ]
1831 : 1140 : return -EAGAIN;
1832 : : }
1833 : :
1834 : 92 : return rc;
1835 : 2 : }
1836 : :
1837 : : static void
1838 : 57 : nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr)
1839 : : {
1840 : 1 : struct spdk_nvme_qpair *qpair;
1841 : :
1842 [ + + + - : 88 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
+ - + - #
# # # #
# ]
1843 [ # # ]: 31 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1844 : 0 : }
1845 : 57 : }
1846 : :
1847 : : int
1848 : 63 : spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
1849 : : {
1850 : 2 : int rc;
1851 : :
1852 : 63 : nvme_ctrlr_lock(ctrlr);
1853 : :
1854 : 63 : rc = nvme_ctrlr_disconnect(ctrlr);
1855 [ + + ]: 63 : if (rc == 0) {
1856 : 57 : nvme_ctrlr_fail_io_qpairs(ctrlr);
1857 : 1 : }
1858 : :
1859 : 63 : nvme_ctrlr_unlock(ctrlr);
1860 : :
1861 [ + + ]: 63 : if (rc != 0) {
1862 [ + - ]: 6 : if (rc == -EBUSY) {
1863 : 6 : rc = 0;
1864 : 1 : }
1865 : 6 : return rc;
1866 : : }
1867 : :
1868 : 1 : while (1) {
1869 : 385 : rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr);
1870 [ + + ]: 385 : if (rc == -ENXIO) {
1871 : 57 : break;
1872 : : }
1873 : : }
1874 : :
1875 : 57 : spdk_nvme_ctrlr_reconnect_async(ctrlr);
1876 : :
1877 : 24 : while (true) {
1878 : 53928 : rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr);
1879 [ + + ]: 53928 : if (rc != -EAGAIN) {
1880 : 57 : break;
1881 : : }
1882 : : }
1883 : :
1884 : 57 : return rc;
1885 : 2 : }
1886 : :
1887 : : int
1888 : 0 : spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr)
1889 : : {
1890 : 0 : union spdk_nvme_cap_register cap;
1891 : 0 : int rc = 0;
1892 : :
1893 : 0 : cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
1894 [ # # ]: 0 : if (cap.bits.nssrs == 0) {
1895 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1896 : 0 : return -ENOTSUP;
1897 : : }
1898 : :
1899 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1900 : 0 : nvme_ctrlr_lock(ctrlr);
1901 [ # # # # ]: 0 : ctrlr->is_resetting = true;
1902 : 0 : rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE);
1903 [ # # # # ]: 0 : ctrlr->is_resetting = false;
1904 : :
1905 : 0 : nvme_ctrlr_unlock(ctrlr);
1906 : : /*
1907 : : * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause
1908 : : * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup.
1909 : : */
1910 : 0 : return rc;
1911 : 0 : }
1912 : :
1913 : : int
1914 : 41 : spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid)
1915 : : {
1916 : 41 : int rc = 0;
1917 : :
1918 : 41 : nvme_ctrlr_lock(ctrlr);
1919 : :
1920 [ + + + + : 41 : if (ctrlr->is_failed == false) {
+ - + + ]
1921 : 6 : rc = -EPERM;
1922 : 6 : goto out;
1923 : : }
1924 : :
1925 [ + + + - : 35 : if (trid->trtype != ctrlr->trid.trtype) {
+ - + - +
- + + ]
1926 : 6 : rc = -EINVAL;
1927 : 6 : goto out;
1928 : : }
1929 : :
1930 [ + + + + : 29 : if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) {
+ + + - +
- + + ]
1931 : 6 : rc = -EINVAL;
1932 : 6 : goto out;
1933 : : }
1934 : :
1935 [ + - ]: 23 : ctrlr->trid = *trid;
1936 : :
1937 : 37 : out:
1938 : 41 : nvme_ctrlr_unlock(ctrlr);
1939 : 45 : return rc;
1940 : 4 : }
1941 : :
1942 : : void
1943 : 776 : spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr,
1944 : : spdk_nvme_remove_cb remove_cb, void *remove_ctx)
1945 : : {
1946 [ - + ]: 776 : if (!spdk_process_is_primary()) {
1947 : 0 : return;
1948 : : }
1949 : :
1950 : 776 : nvme_ctrlr_lock(ctrlr);
1951 [ - + - + ]: 776 : ctrlr->remove_cb = remove_cb;
1952 [ - + - + ]: 776 : ctrlr->cb_ctx = remove_ctx;
1953 : 776 : nvme_ctrlr_unlock(ctrlr);
1954 : 1 : }
1955 : :
1956 : : static void
1957 : 2857 : nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
1958 : : {
1959 : 2857 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1960 : :
1961 [ + - + + : 2857 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1962 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
1963 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1964 : 0 : return;
1965 : : }
1966 : :
1967 : : /*
1968 : : * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
1969 : : * controller supports.
1970 : : */
1971 [ + - + - ]: 2857 : ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr);
1972 [ + + + + : 2857 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
1973 [ + + + - : 2857 : if (ctrlr->cdata.mdts > 0) {
+ - + + ]
1974 [ + + + + : 2752 : ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size,
+ + + - +
- + - + -
- + + - -
+ # # # #
+ - + - +
- + - + -
- + + - +
- + - ]
1975 : : ctrlr->min_page_size * (1 << ctrlr->cdata.mdts));
1976 [ + + + + : 2752 : NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
1977 : 1062 : }
1978 : :
1979 [ + + + + : 2857 : NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1980 [ + + + - : 2857 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
+ - + + ]
1981 [ + - + - : 742 : ctrlr->cntlid = ctrlr->cdata.cntlid;
+ - + - +
- ]
1982 : 3 : } else {
1983 : : /*
1984 : : * Fabrics controllers should already have CNTLID from the Connect command.
1985 : : *
1986 : : * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data,
1987 : : * trust the one from Connect.
1988 : : */
1989 [ + + + - : 2115 : if (ctrlr->cntlid != ctrlr->cdata.cntlid) {
+ - + - +
- + + ]
1990 [ + + + + : 42 : NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n",
+ - - + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1991 : : ctrlr->cdata.cntlid, ctrlr->cntlid);
1992 : 7 : }
1993 : : }
1994 : :
1995 [ + + + - : 2857 : if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
+ - + + +
- + - -
+ ]
1996 [ + + + - : 2632 : assert(ctrlr->cdata.sgls.supported != 0x3);
+ - + - #
# ]
1997 [ + - + - ]: 2632 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
1998 [ + + + - : 2632 : if (ctrlr->cdata.sgls.supported == 0x2) {
+ - + + ]
1999 [ + - + - ]: 43 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT;
2000 : 7 : }
2001 : :
2002 [ + - + - ]: 2632 : ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr);
2003 [ + + + + : 2632 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
2004 : 1060 : }
2005 : :
2006 [ + + + - : 2857 : if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
+ - - + #
# # # #
# ]
2007 [ # # # # ]: 1 : ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED;
2008 : 0 : }
2009 : :
2010 [ + + + - : 2857 : if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
+ - - + #
# # # #
# ]
2011 [ # # # # ]: 44 : ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
2012 : 0 : }
2013 : :
2014 [ + + + - : 2857 : if (ctrlr->cdata.oacs.directives) {
+ - + - ]
2015 [ # # # # ]: 607 : ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED;
2016 : 0 : }
2017 : :
2018 [ + + + + : 2857 : NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n",
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2019 : : ctrlr->cdata.fuses.compare_and_write);
2020 [ + + + - : 2857 : if (ctrlr->cdata.fuses.compare_and_write) {
+ - + + ]
2021 [ + - + - ]: 2016 : ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED;
2022 : 1060 : }
2023 : :
2024 : 3935 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2025 [ + - + - : 2857 : ctrlr->opts.admin_timeout_ms);
+ - ]
2026 [ - + ]: 1078 : }
2027 : :
2028 : : static int
2029 : 2857 : nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
2030 : : {
2031 : 16 : int rc;
2032 : :
2033 : 3935 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
2034 [ + - + - : 2857 : ctrlr->opts.admin_timeout_ms);
+ - ]
2035 : :
2036 : 2857 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0,
2037 [ + - ]: 2857 : &ctrlr->cdata, sizeof(ctrlr->cdata),
2038 : 1078 : nvme_ctrlr_identify_done, ctrlr);
2039 [ - + ]: 2857 : if (rc != 0) {
2040 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2041 : 0 : return rc;
2042 : : }
2043 : :
2044 : 2857 : return 0;
2045 : 1078 : }
2046 : :
2047 : : static void
2048 : 615 : nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl)
2049 : : {
2050 : 0 : struct spdk_nvme_cmds_and_effect_log_page *log_page;
2051 : 615 : struct spdk_nvme_ctrlr *ctrlr = arg;
2052 : :
2053 [ + - - + : 615 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2054 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
2055 [ # # # # ]: 0 : spdk_free(ctrlr->tmp_ptr);
2056 [ # # # # ]: 0 : ctrlr->tmp_ptr = NULL;
2057 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2058 : 0 : return;
2059 : : }
2060 : :
2061 [ # # # # ]: 615 : log_page = ctrlr->tmp_ptr;
2062 : :
2063 [ + - # # : 615 : if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) {
# # # # #
# ]
2064 [ # # # # ]: 615 : ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED;
2065 : 0 : }
2066 [ # # # # ]: 615 : spdk_free(ctrlr->tmp_ptr);
2067 [ # # # # ]: 615 : ctrlr->tmp_ptr = NULL;
2068 : :
2069 [ # # # # : 615 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms);
# # ]
2070 [ # # ]: 0 : }
2071 : :
2072 : : static int
2073 : 615 : nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr)
2074 : : {
2075 : 0 : int rc;
2076 : :
2077 [ - + # # : 615 : assert(!ctrlr->tmp_ptr);
# # # # ]
2078 [ # # # # ]: 615 : ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL,
2079 : : SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2080 [ - + # # : 615 : if (!ctrlr->tmp_ptr) {
# # ]
2081 : 0 : rc = -ENOMEM;
2082 : 0 : goto error;
2083 : : }
2084 : :
2085 : 615 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG,
2086 [ # # # # : 615 : ctrlr->opts.admin_timeout_ms);
# # ]
2087 : :
2088 : 615 : rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG,
2089 [ # # # # ]: 0 : 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page),
2090 [ # # # # ]: 0 : 0, 0, 0, SPDK_NVME_CSI_ZNS << 24,
2091 : 0 : nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr);
2092 [ - + ]: 615 : if (rc != 0) {
2093 : 0 : goto error;
2094 : : }
2095 : :
2096 : 615 : return 0;
2097 : :
2098 : 0 : error:
2099 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2100 [ # # # # ]: 0 : spdk_free(ctrlr->tmp_ptr);
2101 [ # # # # ]: 0 : ctrlr->tmp_ptr = NULL;
2102 : 0 : return rc;
2103 : 0 : }
2104 : :
2105 : : static void
2106 : 615 : nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl)
2107 : : {
2108 : 615 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2109 : :
2110 [ + - - + : 615 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2111 : : /* no need to print an error, the controller simply does not support ZNS */
2112 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2113 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2114 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
2115 : 0 : return;
2116 : : }
2117 : :
2118 : : /* A zero zasl value means use mdts */
2119 [ - + # # : 615 : if (ctrlr->cdata_zns->zasl) {
# # # # #
# ]
2120 [ # # # # : 0 : uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl);
# # # # #
# # # # #
# # ]
2121 [ # # # # : 0 : ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append);
# # # # #
# # # #
# ]
2122 : 0 : } else {
2123 [ # # # # : 615 : ctrlr->max_zone_append_size = ctrlr->max_xfer_size;
# # # # ]
2124 : : }
2125 : :
2126 : 615 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG,
2127 [ # # # # : 615 : ctrlr->opts.admin_timeout_ms);
# # ]
2128 [ # # ]: 0 : }
2129 : :
2130 : : /**
2131 : : * This function will try to fetch the I/O Command Specific Controller data structure for
2132 : : * each I/O Command Set supported by SPDK.
2133 : : *
2134 : : * If an I/O Command Set is not supported by the controller, "Invalid Field in Command"
2135 : : * will be returned. Since we are fetching in a exploratively way, getting an error back
2136 : : * from the controller should not be treated as fatal.
2137 : : *
2138 : : * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set).
2139 : : *
2140 : : * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific
2141 : : * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set).
2142 : : */
2143 : : static int
2144 : 2753 : nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2145 : : {
2146 : 19 : int rc;
2147 : :
2148 [ + + ]: 2753 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2149 : 3219 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2150 [ + - + - : 2138 : ctrlr->opts.admin_timeout_ms);
+ - ]
2151 : 2138 : return 0;
2152 : : }
2153 : :
2154 : : /*
2155 : : * Since SPDK currently only needs to fetch a single Command Set, keep the code here,
2156 : : * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates,
2157 : : * which would require additional functions and complexity for no good reason.
2158 : : */
2159 [ - + # # : 615 : assert(!ctrlr->cdata_zns);
# # # # ]
2160 [ # # # # ]: 615 : ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2161 : : SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2162 [ - + # # : 615 : if (!ctrlr->cdata_zns) {
# # ]
2163 : 0 : rc = -ENOMEM;
2164 : 0 : goto error;
2165 : : }
2166 : :
2167 : 615 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC,
2168 [ # # # # : 615 : ctrlr->opts.admin_timeout_ms);
# # ]
2169 : :
2170 : 615 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS,
2171 [ # # # # ]: 615 : ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns),
2172 : 0 : nvme_ctrlr_identify_zns_specific_done, ctrlr);
2173 [ - + ]: 615 : if (rc != 0) {
2174 : 0 : goto error;
2175 : : }
2176 : :
2177 : 615 : return 0;
2178 : :
2179 : 0 : error:
2180 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2181 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2182 : 0 : return rc;
2183 : 1081 : }
2184 : :
2185 : : enum nvme_active_ns_state {
2186 : : NVME_ACTIVE_NS_STATE_IDLE,
2187 : : NVME_ACTIVE_NS_STATE_PROCESSING,
2188 : : NVME_ACTIVE_NS_STATE_DONE,
2189 : : NVME_ACTIVE_NS_STATE_ERROR
2190 : : };
2191 : :
2192 : : typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *);
2193 : :
2194 : : struct nvme_active_ns_ctx {
2195 : : struct spdk_nvme_ctrlr *ctrlr;
2196 : : uint32_t page_count;
2197 : : uint32_t next_nsid;
2198 : : uint32_t *new_ns_list;
2199 : : nvme_active_ns_ctx_deleter deleter;
2200 : :
2201 : : enum nvme_active_ns_state state;
2202 : : };
2203 : :
2204 : : static struct nvme_active_ns_ctx *
2205 : 3012 : nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter)
2206 : : {
2207 : 45 : struct nvme_active_ns_ctx *ctx;
2208 : 3012 : uint32_t *new_ns_list = NULL;
2209 : :
2210 : 3012 : ctx = calloc(1, sizeof(*ctx));
2211 [ + + ]: 3012 : if (!ctx) {
2212 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
2213 : 0 : return NULL;
2214 : : }
2215 : :
2216 [ + - + - ]: 3012 : new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size,
2217 : : NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE);
2218 [ + + ]: 3012 : if (!new_ns_list) {
2219 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
2220 : 0 : free(ctx);
2221 : 0 : return NULL;
2222 : : }
2223 : :
2224 [ + - + - ]: 3012 : ctx->page_count = 1;
2225 [ + - + - ]: 3012 : ctx->new_ns_list = new_ns_list;
2226 [ + - + - ]: 3012 : ctx->ctrlr = ctrlr;
2227 [ + - + - ]: 3012 : ctx->deleter = deleter;
2228 : :
2229 : 3012 : return ctx;
2230 : 1107 : }
2231 : :
2232 : : static void
2233 : 3012 : nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx)
2234 : : {
2235 [ + - + - ]: 3012 : spdk_free(ctx->new_ns_list);
2236 : 3012 : free(ctx);
2237 : 3012 : }
2238 : :
2239 : : static int
2240 : 112947 : nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2241 : : {
2242 : 92418 : struct spdk_nvme_ns tmp, *ns;
2243 : :
2244 [ + + # # ]: 112947 : assert(ctrlr != NULL);
2245 : :
2246 [ + - ]: 112947 : tmp.id = nsid;
2247 [ + - ]: 112947 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
2248 [ + + ]: 112947 : if (ns == NULL) {
2249 : 0 : return -EINVAL;
2250 : : }
2251 : :
2252 : 112947 : nvme_ns_destruct(ns);
2253 [ + - + - ]: 112947 : ns->active = false;
2254 : :
2255 : 112947 : return 0;
2256 : 19465 : }
2257 : :
2258 : : static int
2259 : 76652 : nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2260 : : {
2261 : 12311 : struct spdk_nvme_ns *ns;
2262 : :
2263 [ + - + + : 76652 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
+ - + - -
+ ]
2264 : 0 : return -EINVAL;
2265 : : }
2266 : :
2267 : : /* Namespaces are constructed on demand, so simply request it. */
2268 : 76652 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2269 [ + + ]: 76652 : if (ns == NULL) {
2270 : 0 : return -ENOMEM;
2271 : : }
2272 : :
2273 [ + - + - ]: 76652 : ns->active = true;
2274 : :
2275 : 76652 : return 0;
2276 : 13373 : }
2277 : :
2278 : : static void
2279 : 3006 : nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list,
2280 : : size_t max_entries)
2281 : : {
2282 : 3006 : uint32_t active_ns_count = 0;
2283 : 44 : size_t i;
2284 : 44 : uint32_t nsid;
2285 : 44 : struct spdk_nvme_ns *ns, *tmp_ns;
2286 : 44 : int rc;
2287 : :
2288 : : /* First, remove namespaces that no longer exist */
2289 [ + + + + : 95396 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
+ + ]
2290 [ + - + - ]: 92390 : nsid = new_ns_list[0];
2291 : 92390 : active_ns_count = 0;
2292 [ + + ]: 21285120 : while (nsid != 0) {
2293 [ + + + - : 21220778 : if (nsid == ns->id) {
+ + ]
2294 : 28048 : break;
2295 : : }
2296 : :
2297 [ + - + - ]: 21192730 : nsid = new_ns_list[active_ns_count++];
2298 : : }
2299 : :
2300 [ + + + - : 92390 : if (nsid != ns->id) {
+ + ]
2301 : : /* Did not find this namespace id in the new list. */
2302 [ + + + + : 64342 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id);
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
2303 [ + - + - ]: 64342 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
2304 : 10717 : }
2305 : 15343 : }
2306 : :
2307 : : /* Next, add new namespaces */
2308 : 3006 : active_ns_count = 0;
2309 [ + + ]: 79658 : for (i = 0; i < max_entries; i++) {
2310 [ + - + - ]: 79658 : nsid = new_ns_list[active_ns_count];
2311 : :
2312 [ + + ]: 79658 : if (nsid == 0) {
2313 : 3006 : break;
2314 : : }
2315 : :
2316 : : /* If the namespace already exists, this will not construct it a second time. */
2317 : 76652 : rc = nvme_ctrlr_construct_namespace(ctrlr, nsid);
2318 [ - + ]: 76652 : if (rc != 0) {
2319 : : /* We can't easily handle a failure here. But just move on. */
2320 [ # # ]: 0 : assert(false);
2321 : : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n");
2322 : : continue;
2323 : : }
2324 : :
2325 : 76652 : active_ns_count++;
2326 : 13373 : }
2327 : :
2328 [ + - + - ]: 3006 : ctrlr->active_ns_count = active_ns_count;
2329 : 3006 : }
2330 : :
2331 : : static void
2332 : 2917 : nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2333 : : {
2334 : 2917 : struct nvme_active_ns_ctx *ctx = arg;
2335 : 2917 : uint32_t *new_ns_list = NULL;
2336 : :
2337 [ + + + + : 2917 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + + +
- + - + -
- + ]
2338 [ + - + - ]: 6 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2339 : 6 : goto out;
2340 : : }
2341 : :
2342 [ + - + - : 2911 : ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1];
+ - + - +
- + - + -
+ - ]
2343 [ + + + - : 2911 : if (ctx->next_nsid == 0) {
+ + ]
2344 [ + - + - ]: 2881 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2345 : 2881 : goto out;
2346 : : }
2347 : :
2348 [ + - ]: 30 : ctx->page_count++;
2349 [ + - + - ]: 35 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2350 [ + - + - ]: 30 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2351 [ + - + - : 30 : ctx->ctrlr->page_size);
+ - + - ]
2352 [ + + ]: 30 : if (!new_ns_list) {
2353 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2354 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2355 : 0 : goto out;
2356 : : }
2357 : :
2358 [ + - + - ]: 30 : ctx->new_ns_list = new_ns_list;
2359 : 30 : nvme_ctrlr_identify_active_ns_async(ctx);
2360 : 30 : return;
2361 : :
2362 : 1800 : out:
2363 [ + + + - : 2887 : if (ctx->deleter) {
+ + ]
2364 [ + - + - : 2688 : ctx->deleter(ctx);
- + + - ]
2365 : 1071 : }
2366 [ - + ]: 1092 : }
2367 : :
2368 : : static void
2369 : 3042 : nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx)
2370 : : {
2371 [ + - + - ]: 3042 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2372 : 50 : uint32_t i;
2373 : 50 : int rc;
2374 : :
2375 [ + + + - : 3042 : if (ctrlr->cdata.nn == 0) {
+ - + + ]
2376 [ + - + - ]: 96 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2377 : 96 : goto out;
2378 : : }
2379 : :
2380 [ + + + - : 2946 : assert(ctx->new_ns_list != NULL);
+ - # # ]
2381 : :
2382 : : /*
2383 : : * If controller doesn't support active ns list CNS 0x02 dummy up
2384 : : * an active ns list, i.e. all namespaces report as active
2385 : : */
2386 [ + + + + : 2946 : if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) {
+ - + - +
- + + + -
+ - - + ]
2387 : 4 : uint32_t *new_ns_list;
2388 : :
2389 : : /*
2390 : : * Active NS list must always end with zero element.
2391 : : * So, we allocate for cdata.nn+1.
2392 : : */
2393 [ + - + - : 29 : ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1,
+ - + - +
- ]
2394 : : sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0]));
2395 [ + - + - ]: 33 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2396 [ + - + - ]: 29 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2397 [ + - + - : 29 : ctx->ctrlr->page_size);
+ - + - ]
2398 [ + + ]: 29 : if (!new_ns_list) {
2399 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2400 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2401 : 0 : goto out;
2402 : : }
2403 : :
2404 [ + - + - ]: 29 : ctx->new_ns_list = new_ns_list;
2405 [ + - + - : 29 : ctx->new_ns_list[ctrlr->cdata.nn] = 0;
+ - + - +
- + - +
- ]
2406 [ + + + - : 24556 : for (i = 0; i < ctrlr->cdata.nn; i++) {
+ - + + ]
2407 [ + - + - : 24527 : ctx->new_ns_list[i] = i + 1;
+ - + - ]
2408 : 4087 : }
2409 : :
2410 [ + - + - ]: 29 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2411 : 29 : goto out;
2412 [ - + ]: 4 : }
2413 : :
2414 [ + - + - ]: 2917 : ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING;
2415 [ + - + - ]: 4009 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0,
2416 [ + - + - : 2917 : &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list),
+ - + - +
- ]
2417 : 1092 : nvme_ctrlr_identify_active_ns_async_done, ctx);
2418 [ - + ]: 2917 : if (rc != 0) {
2419 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2420 : 0 : goto out;
2421 : : }
2422 : :
2423 : 2917 : return;
2424 : :
2425 : 105 : out:
2426 [ + + + - : 125 : if (ctx->deleter) {
+ + ]
2427 [ + - + - : 95 : ctx->deleter(ctx);
- + + - ]
2428 : 15 : }
2429 [ - + ]: 1112 : }
2430 : :
2431 : : static void
2432 : 2783 : _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx)
2433 : : {
2434 [ + - + - ]: 2783 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2435 : 24 : struct spdk_nvme_ns *ns;
2436 : :
2437 [ + + + - : 2783 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
- + ]
2438 : 0 : nvme_active_ns_ctx_destroy(ctx);
2439 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2440 : 0 : return;
2441 : : }
2442 : :
2443 [ + + + - : 2783 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
+ - # # ]
2444 : :
2445 [ + + + + ]: 2948 : RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) {
2446 : 165 : nvme_ns_free_iocs_specific_data(ns);
2447 : 4 : }
2448 : :
2449 [ + - + - : 2783 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
+ - + - ]
2450 : 2783 : nvme_active_ns_ctx_destroy(ctx);
2451 [ + - + - : 2783 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms);
+ - ]
2452 [ - + ]: 1086 : }
2453 : :
2454 : : static void
2455 : 2783 : _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2456 : : {
2457 : 24 : struct nvme_active_ns_ctx *ctx;
2458 : :
2459 : 2783 : ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter);
2460 [ + + ]: 2783 : if (!ctx) {
2461 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2462 : 0 : return;
2463 : : }
2464 : :
2465 : 3869 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS,
2466 [ + + + + : 2783 : ctrlr->opts.admin_timeout_ms);
+ + ]
2467 : 2783 : nvme_ctrlr_identify_active_ns_async(ctx);
2468 [ - + ]: 1086 : }
2469 : :
2470 : : int
2471 : 229 : nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2472 : : {
2473 : 21 : struct nvme_active_ns_ctx *ctx;
2474 : 21 : int rc;
2475 : :
2476 : 229 : ctx = nvme_active_ns_ctx_create(ctrlr, NULL);
2477 [ + + ]: 229 : if (!ctx) {
2478 : 0 : return -ENOMEM;
2479 : : }
2480 : :
2481 : 229 : nvme_ctrlr_identify_active_ns_async(ctx);
2482 [ + + + - : 166218 : while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) {
+ - ]
2483 [ # # # # ]: 165989 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
2484 [ - + ]: 165989 : if (rc < 0) {
2485 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2486 : 0 : break;
2487 : : }
2488 : : }
2489 : :
2490 [ + + + - : 229 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
+ + ]
2491 : 6 : nvme_active_ns_ctx_destroy(ctx);
2492 : 6 : return -ENXIO;
2493 : : }
2494 : :
2495 [ + + + - : 223 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
+ - # # ]
2496 [ + - + - : 223 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
+ - + - ]
2497 : 223 : nvme_active_ns_ctx_destroy(ctx);
2498 : :
2499 : 223 : return 0;
2500 : 21 : }
2501 : :
2502 : : static void
2503 : 2750 : nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2504 : : {
2505 : 2750 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2506 [ + - + - ]: 2750 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2507 : 21 : uint32_t nsid;
2508 : 21 : int rc;
2509 : :
2510 [ + - + + : 2750 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2511 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2512 : 0 : return;
2513 : : }
2514 : :
2515 : 2750 : nvme_ns_set_identify_data(ns);
2516 : :
2517 : : /* move on to the next active NS */
2518 [ + - + - ]: 2750 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2519 : 2750 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2520 [ + + ]: 2750 : if (ns == NULL) {
2521 : 3554 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2522 [ + + + + : 2486 : ctrlr->opts.admin_timeout_ms);
+ + ]
2523 : 2486 : return;
2524 : : }
2525 [ + - + - ]: 264 : ns->ctrlr = ctrlr;
2526 [ + - + - ]: 264 : ns->id = nsid;
2527 : :
2528 : 264 : rc = nvme_ctrlr_identify_ns_async(ns);
2529 [ + + ]: 264 : if (rc) {
2530 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2531 : 0 : }
2532 [ - + ]: 1083 : }
2533 : :
2534 : : static int
2535 : 2750 : nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns)
2536 : : {
2537 [ + - + - ]: 2750 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2538 : 21 : struct spdk_nvme_ns_data *nsdata;
2539 : :
2540 [ + - ]: 2750 : nsdata = &ns->nsdata;
2541 : :
2542 : 3833 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS,
2543 [ + - + - : 2750 : ctrlr->opts.admin_timeout_ms);
+ - ]
2544 [ + - + - : 2750 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0,
+ - + - ]
2545 : 1083 : nsdata, sizeof(*nsdata),
2546 : 1083 : nvme_ctrlr_identify_ns_async_done, ns);
2547 : 21 : }
2548 : :
2549 : : static int
2550 : 2723 : nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2551 : : {
2552 : 14 : uint32_t nsid;
2553 : 14 : struct spdk_nvme_ns *ns;
2554 : 14 : int rc;
2555 : :
2556 : 2723 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2557 : 2723 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2558 [ + + ]: 2723 : if (ns == NULL) {
2559 : : /* No active NS, move on to the next state */
2560 : 245 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2561 [ - + - + : 237 : ctrlr->opts.admin_timeout_ms);
- + ]
2562 : 237 : return 0;
2563 : : }
2564 : :
2565 [ + - + - ]: 2486 : ns->ctrlr = ctrlr;
2566 [ + - + - ]: 2486 : ns->id = nsid;
2567 : :
2568 : 2486 : rc = nvme_ctrlr_identify_ns_async(ns);
2569 [ + + ]: 2486 : if (rc) {
2570 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2571 : 0 : }
2572 : :
2573 : 2486 : return rc;
2574 : 1076 : }
2575 : :
2576 : : static int
2577 : 641 : nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
2578 : : {
2579 : 4 : uint32_t nsid;
2580 : 4 : struct spdk_nvme_ns *ns;
2581 : 4 : int rc;
2582 : :
2583 [ + + ]: 641 : if (!prev_nsid) {
2584 : 627 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2585 : 2 : } else {
2586 : : /* move on to the next active NS */
2587 : 14 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid);
2588 : : }
2589 : :
2590 : 641 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2591 [ + + ]: 641 : if (ns == NULL) {
2592 : : /* No first/next active NS, move on to the next state */
2593 : 9 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2594 [ + - + - : 8 : ctrlr->opts.admin_timeout_ms);
+ - ]
2595 : 8 : return 0;
2596 : : }
2597 : :
2598 : : /* loop until we find a ns which has (supported) iocs specific data */
2599 [ + + ]: 811 : while (!nvme_ns_has_supported_iocs_specific_data(ns)) {
2600 [ + - + - ]: 797 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2601 : 797 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2602 [ + + ]: 797 : if (ns == NULL) {
2603 : : /* no namespace with (supported) iocs specific data found */
2604 : 620 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2605 [ - + - + : 619 : ctrlr->opts.admin_timeout_ms);
- + ]
2606 : 619 : return 0;
2607 : : }
2608 : : }
2609 : :
2610 : 14 : rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns);
2611 [ + + ]: 14 : if (rc) {
2612 : 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2613 : 1 : }
2614 : :
2615 : 14 : return rc;
2616 : 4 : }
2617 : :
2618 : : static void
2619 : 2 : nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2620 : : {
2621 : 2 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2622 [ # # # # ]: 2 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2623 : :
2624 [ + - - + : 2 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2625 : 0 : nvme_ns_free_zns_specific_data(ns);
2626 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2627 : 0 : return;
2628 : : }
2629 : :
2630 [ # # # # ]: 2 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2631 [ # # ]: 0 : }
2632 : :
2633 : : static int
2634 : 14 : nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns)
2635 : : {
2636 [ + - + - ]: 14 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2637 : 2 : int rc;
2638 : :
2639 [ + - + - : 14 : switch (ns->csi) {
+ - ]
2640 : 12 : case SPDK_NVME_CSI_ZNS:
2641 : 14 : break;
2642 : 0 : default:
2643 : : /*
2644 : : * This switch must handle all cases for which
2645 : : * nvme_ns_has_supported_iocs_specific_data() returns true,
2646 : : * other cases should never happen.
2647 : : */
2648 [ # # ]: 0 : assert(0);
2649 : : }
2650 : :
2651 [ + + + - : 14 : assert(!ns->nsdata_zns);
+ - # # ]
2652 [ + - + - ]: 14 : ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2653 : : SPDK_MALLOC_SHARE);
2654 [ + + + - : 14 : if (!ns->nsdata_zns) {
+ - ]
2655 : 0 : return -ENOMEM;
2656 : : }
2657 : :
2658 : 16 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2659 [ + - + - : 14 : ctrlr->opts.admin_timeout_ms);
+ - ]
2660 [ + - + - : 16 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
+ - + - +
- + - ]
2661 [ + - + - ]: 14 : ns->nsdata_zns, sizeof(*ns->nsdata_zns),
2662 : 2 : nvme_ctrlr_identify_ns_zns_specific_async_done, ns);
2663 [ + + ]: 14 : if (rc) {
2664 : 6 : nvme_ns_free_zns_specific_data(ns);
2665 : 1 : }
2666 : :
2667 : 14 : return rc;
2668 : 2 : }
2669 : :
2670 : : static int
2671 : 2723 : nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2672 : : {
2673 [ + + ]: 2723 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2674 : : /* Multi IOCS not supported/enabled, move on to the next state */
2675 : 3184 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2676 [ + - + - : 2108 : ctrlr->opts.admin_timeout_ms);
+ - ]
2677 : 2108 : return 0;
2678 : : }
2679 : :
2680 : 615 : return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0);
2681 : 1076 : }
2682 : :
2683 : : static void
2684 : 2555 : nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2685 : : {
2686 : 2555 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2687 [ + - + - ]: 2555 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2688 : 6 : uint32_t nsid;
2689 : 6 : int rc;
2690 : :
2691 [ + + + + : 2555 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2692 : : /*
2693 : : * Many controllers claim to be compatible with NVMe 1.3, however,
2694 : : * they do not implement NS ID Desc List. Therefore, instead of setting
2695 : : * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion
2696 : : * error and move on to the next state.
2697 : : *
2698 : : * The proper way is to create a new quirk for controllers that violate
2699 : : * the NVMe 1.3 spec by not supporting NS ID Desc List.
2700 : : * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since
2701 : : * it is too generic and was added in order to handle controllers that
2702 : : * violate the NVMe 1.1 spec by not supporting ACTIVE LIST).
2703 : : */
2704 : 20 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2705 [ # # # # : 20 : ctrlr->opts.admin_timeout_ms);
# # ]
2706 : 20 : return;
2707 : : }
2708 : :
2709 : 2535 : nvme_ns_set_id_desc_list_data(ns);
2710 : :
2711 : : /* move on to the next active NS */
2712 [ + - + - ]: 2535 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2713 : 2535 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2714 [ + + ]: 2535 : if (ns == NULL) {
2715 : 3399 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2716 [ + + + + : 2337 : ctrlr->opts.admin_timeout_ms);
+ + ]
2717 : 2337 : return;
2718 : : }
2719 : :
2720 : 198 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2721 [ + + ]: 198 : if (rc) {
2722 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2723 : 0 : }
2724 [ - + ]: 1066 : }
2725 : :
2726 : : static int
2727 : 2555 : nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns)
2728 : : {
2729 [ + - + - ]: 2555 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2730 : :
2731 [ + + + - ]: 2555 : memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list));
2732 : :
2733 : 3621 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS,
2734 [ + - + - : 2555 : ctrlr->opts.admin_timeout_ms);
+ - ]
2735 [ + - + - ]: 3831 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST,
2736 [ + - + - : 2555 : 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list),
+ - ]
2737 : 1066 : nvme_ctrlr_identify_id_desc_async_done, ns);
2738 : 6 : }
2739 : :
2740 : : static int
2741 : 2723 : nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2742 : : {
2743 : 14 : uint32_t nsid;
2744 : 14 : struct spdk_nvme_ns *ns;
2745 : 14 : int rc;
2746 : :
2747 [ + + + - : 3799 : if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) &&
+ - + - +
- + + +
+ ]
2748 [ + + + - : 179 : !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) ||
+ - + - ]
2749 [ + + + - ]: 2558 : (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2750 [ + + + + : 179 : NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2751 : : /* NS ID Desc List not supported, move on to the next state */
2752 : 193 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2753 [ + - + - : 179 : ctrlr->opts.admin_timeout_ms);
+ - ]
2754 : 179 : return 0;
2755 : : }
2756 : :
2757 : 2544 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2758 : 2544 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2759 [ + + ]: 2544 : if (ns == NULL) {
2760 : : /* No active NS, move on to the next state */
2761 : 187 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2762 [ # # # # : 187 : ctrlr->opts.admin_timeout_ms);
# # ]
2763 : 187 : return 0;
2764 : : }
2765 : :
2766 : 2357 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2767 [ + + ]: 2357 : if (rc) {
2768 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2769 : 0 : }
2770 : :
2771 : 2357 : return rc;
2772 : 1076 : }
2773 : :
2774 : : static void
2775 : 2753 : nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr)
2776 : : {
2777 [ + + ]: 2753 : if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
2778 [ + + + - : 1885 : if (ctrlr->cdata.nvmf_specific.ioccsz < 4) {
+ - + - +
- ]
2779 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
2780 : : ctrlr->cdata.nvmf_specific.ioccsz);
2781 [ # # # # : 0 : ctrlr->cdata.nvmf_specific.ioccsz = 4;
# # # # ]
2782 [ # # ]: 0 : assert(0);
2783 : : }
2784 [ + - + - : 1885 : ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd);
+ - + - +
- + - ]
2785 [ + - + - : 1885 : ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff;
+ - + - +
- + - ]
2786 : 1057 : }
2787 : 2753 : }
2788 : :
2789 : : static void
2790 : 2753 : nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl)
2791 : : {
2792 : 19 : uint32_t cq_allocated, sq_allocated, min_allocated, i;
2793 : 2753 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2794 : :
2795 [ + - + + : 2753 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2796 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
2797 [ # # # # : 0 : ctrlr->opts.num_io_queues = 0;
# # ]
2798 : 0 : } else {
2799 : : /*
2800 : : * Data in cdw0 is 0-based.
2801 : : * Lower 16-bits indicate number of submission queues allocated.
2802 : : * Upper 16-bits indicate number of completion queues allocated.
2803 : : */
2804 [ + - + - ]: 2753 : sq_allocated = (cpl->cdw0 & 0xFFFF) + 1;
2805 [ + - + - : 2753 : cq_allocated = (cpl->cdw0 >> 16) + 1;
+ - ]
2806 : :
2807 : : /*
2808 : : * For 1:1 queue mapping, set number of allocated queues to be minimum of
2809 : : * submission and completion queues.
2810 : : */
2811 [ - + ]: 2753 : min_allocated = spdk_min(sq_allocated, cq_allocated);
2812 : :
2813 : : /* Set number of queues to be minimum of requested and actually allocated. */
2814 [ + - + - : 2753 : ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues);
+ - + + +
- + - + -
+ - + - +
- ]
2815 : : }
2816 : :
2817 [ + - + - : 2753 : ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
+ - + - +
- ]
2818 [ + + + - : 2753 : if (ctrlr->free_io_qids == NULL) {
+ - ]
2819 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2820 : 0 : return;
2821 : : }
2822 : :
2823 : : /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */
2824 [ + + + - : 299711 : for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
+ - + + ]
2825 : 296958 : spdk_nvme_ctrlr_free_qid(ctrlr, i);
2826 : 134926 : }
2827 : :
2828 : 3834 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS,
2829 [ + - + - : 2753 : ctrlr->opts.admin_timeout_ms);
+ - ]
2830 [ - + ]: 1081 : }
2831 : :
2832 : : static int
2833 : 2753 : nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr)
2834 : : {
2835 : 19 : int rc;
2836 : :
2837 [ + + + - : 2753 : if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
+ - - + ]
2838 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2839 : : ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
2840 [ # # # # : 0 : ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
# # ]
2841 [ + + + - : 2753 : } else if (ctrlr->opts.num_io_queues < 1) {
+ - + + ]
2842 [ + - + + : 78 : NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
2843 [ + - + - : 78 : ctrlr->opts.num_io_queues = 1;
+ - ]
2844 : 13 : }
2845 : :
2846 : 3834 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES,
2847 [ + - + - : 2753 : ctrlr->opts.admin_timeout_ms);
+ - ]
2848 : :
2849 [ + - + - : 2753 : rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
+ - ]
2850 : 1081 : nvme_ctrlr_set_num_queues_done, ctrlr);
2851 [ - + ]: 2753 : if (rc != 0) {
2852 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2853 : 0 : return rc;
2854 : : }
2855 : :
2856 : 2753 : return 0;
2857 : 1081 : }
2858 : :
2859 : : static void
2860 : 2043 : nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl)
2861 : : {
2862 : 3 : uint32_t keep_alive_interval_us;
2863 : 2043 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2864 : :
2865 [ + + + + : 2043 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + + +
- + - + -
+ + ]
2866 [ + - + - : 14 : if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) &&
+ - + - +
+ ]
2867 [ + + + - : 12 : (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) {
+ - ]
2868 [ + + + + : 6 : NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2869 : 1 : } else {
2870 [ + - + + : 6 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n",
+ - + - +
- + - + -
- + # # #
# + - + -
+ - + - +
- + - + -
+ - ]
2871 : : cpl->status.sc, cpl->status.sct);
2872 [ + - + - : 6 : ctrlr->opts.keep_alive_timeout_ms = 0;
+ - ]
2873 : 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2874 : 6 : return;
2875 : : }
2876 : 1 : } else {
2877 [ + + + - : 2031 : if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) {
+ - + - +
- + + ]
2878 [ + + + + : 48 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n",
+ - - + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
2879 : : cpl->cdw0);
2880 : 8 : }
2881 : :
2882 [ + - + - : 2031 : ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0;
+ - + - +
- ]
2883 : : }
2884 : :
2885 [ + + + - : 2037 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
+ - + + ]
2886 [ + - + - ]: 42 : ctrlr->keep_alive_interval_ticks = 0;
2887 : 7 : } else {
2888 [ + - + - : 1995 : keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2;
+ - + - ]
2889 : :
2890 [ + + + + : 1995 : NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us);
+ + + - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2891 : :
2892 [ + - + - : 1995 : ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) /
+ - ]
2893 : : UINT64_C(1000000);
2894 : :
2895 : : /* Schedule the first Keep Alive to be sent as soon as possible. */
2896 [ + - + - ]: 1995 : ctrlr->next_keep_alive_tick = spdk_get_ticks();
2897 : : }
2898 : :
2899 [ + + ]: 2037 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2900 : 122 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2901 : 0 : } else {
2902 : 2977 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2903 [ + - + - : 1915 : ctrlr->opts.admin_timeout_ms);
+ - ]
2904 : : }
2905 [ - + ]: 1063 : }
2906 : :
2907 : : static int
2908 : 2893 : nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr)
2909 : : {
2910 : 22 : int rc;
2911 : :
2912 [ + + + - : 2893 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
+ - + + ]
2913 [ - + ]: 200 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2914 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2915 : 0 : } else {
2916 : 219 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2917 [ + - + - : 200 : ctrlr->opts.admin_timeout_ms);
+ - ]
2918 : : }
2919 : 200 : return 0;
2920 : : }
2921 : :
2922 : : /* Note: Discovery controller identify data does not populate KAS according to spec. */
2923 [ + + + + : 2693 : if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) {
+ - + - +
+ ]
2924 [ + + + + : 650 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2925 [ + - + - : 650 : ctrlr->opts.keep_alive_timeout_ms = 0;
+ - ]
2926 : 652 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2927 [ + - + - : 650 : ctrlr->opts.admin_timeout_ms);
+ - ]
2928 : 650 : return 0;
2929 : : }
2930 : :
2931 : 3106 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT,
2932 [ + - + - : 2043 : ctrlr->opts.admin_timeout_ms);
+ - ]
2933 : :
2934 : : /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */
2935 : 3106 : rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0,
2936 : 1063 : nvme_ctrlr_set_keep_alive_timeout_done, ctrlr);
2937 [ + + ]: 2043 : if (rc != 0) {
2938 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc);
# # # # #
# # # # #
# # # # #
# # # #
# ]
2939 [ # # # # : 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
# # ]
2940 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2941 : 0 : return rc;
2942 : : }
2943 : :
2944 : 2043 : return 0;
2945 : 1084 : }
2946 : :
2947 : : static void
2948 : 0 : nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl)
2949 : : {
2950 : 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2951 : :
2952 [ # # # # : 0 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2953 : : /*
2954 : : * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature
2955 : : * is optional.
2956 : : */
2957 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2958 : : cpl->status.sc, cpl->status.sct);
2959 : 0 : } else {
2960 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2961 : : }
2962 : :
2963 [ # # # # : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
# # ]
2964 : 0 : }
2965 : :
2966 : : static int
2967 : 2723 : nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr)
2968 : : {
2969 : 14 : uint8_t *host_id;
2970 : 14 : uint32_t host_id_size;
2971 : 14 : int rc;
2972 : :
2973 [ + + + - : 2723 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
+ - + + ]
2974 : : /*
2975 : : * NVMe-oF sends the host ID during Connect and doesn't allow
2976 : : * Set Features - Host Identifier after Connect, so we don't need to do anything here.
2977 : : */
2978 [ + + + + : 1987 : NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n");
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2979 [ + - + - : 1987 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
+ - ]
2980 : 1987 : return 0;
2981 : : }
2982 : :
2983 [ + + + - : 736 : if (ctrlr->cdata.ctratt.host_id_exhid_supported) {
+ - - + ]
2984 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2985 [ # # # # ]: 0 : host_id = ctrlr->opts.extended_host_id;
2986 : 0 : host_id_size = sizeof(ctrlr->opts.extended_host_id);
2987 : 0 : } else {
2988 [ + + + + : 736 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2989 [ + - + - ]: 736 : host_id = ctrlr->opts.host_id;
2990 : 736 : host_id_size = sizeof(ctrlr->opts.host_id);
2991 : : }
2992 : :
2993 : : /* If the user specified an all-zeroes host identifier, don't send the command. */
2994 [ + - ]: 736 : if (spdk_mem_all_zero(host_id, host_id_size)) {
2995 [ + + + + : 736 : NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2996 [ + - + - : 736 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
+ - ]
2997 : 736 : return 0;
2998 : : }
2999 : :
3000 [ # # # # : 0 : SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size);
# # ]
3001 : :
3002 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID,
3003 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
3004 : :
3005 : 0 : rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr);
3006 [ # # ]: 0 : if (rc != 0) {
3007 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc);
# # # # #
# # # # #
# # # # #
# # # #
# ]
3008 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3009 : 0 : return rc;
3010 : : }
3011 : :
3012 : 0 : return 0;
3013 : 1076 : }
3014 : :
3015 : : void
3016 : 127 : nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr)
3017 : : {
3018 : 4 : uint32_t nsid;
3019 : 4 : struct spdk_nvme_ns *ns;
3020 : :
3021 [ + + ]: 142 : for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
3022 [ + + ]: 379 : nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) {
3023 : 252 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
3024 : 252 : nvme_ns_construct(ns, nsid, ctrlr);
3025 : 15 : }
3026 : 127 : }
3027 : :
3028 : : static int
3029 : 127 : nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr)
3030 : : {
3031 : 4 : struct nvme_completion_poll_status *status;
3032 : 127 : int rc = -ENOMEM;
3033 : 127 : char *buffer = NULL;
3034 : 4 : uint32_t nsid;
3035 : 127 : size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t));
3036 : :
3037 [ + + + - : 127 : if (ctrlr->opts.disable_read_changed_ns_list_log_page) {
+ - - + ]
3038 : 0 : return 0;
3039 : : }
3040 : :
3041 : 127 : buffer = spdk_dma_zmalloc(buf_size, 4096, NULL);
3042 [ + + ]: 127 : if (!buffer) {
3043 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting "
# # # # #
# # # # #
# # # # #
# # # #
# ]
3044 : : "changed ns log.\n");
3045 : 0 : return rc;
3046 : : }
3047 : :
3048 : 127 : status = calloc(1, sizeof(*status));
3049 [ + + ]: 127 : if (!status) {
3050 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3051 : 0 : goto free_buffer;
3052 : : }
3053 : :
3054 : 131 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr,
3055 : : SPDK_NVME_LOG_CHANGED_NS_LIST,
3056 : : SPDK_NVME_GLOBAL_NS_TAG,
3057 : 4 : buffer, buf_size, 0,
3058 : 4 : nvme_completion_poll_cb, status);
3059 : :
3060 [ - + ]: 127 : if (rc) {
3061 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc);
# # # # #
# # # # #
# # # # #
# # # #
# ]
3062 : 0 : free(status);
3063 : 0 : goto free_buffer;
3064 : : }
3065 : :
3066 [ + - + - ]: 131 : rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status,
3067 [ + - + - : 127 : ctrlr->opts.admin_timeout_ms * 1000);
+ - ]
3068 [ + + + - : 127 : if (!status->timed_out) {
+ - - + ]
3069 : 127 : free(status);
3070 : 4 : }
3071 : :
3072 [ - + ]: 127 : if (rc) {
3073 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc);
# # # # #
# # # # #
# # # # #
# # # #
# ]
3074 : 0 : goto free_buffer;
3075 : : }
3076 : :
3077 : : /* only check the case of overflow. */
3078 : 127 : nsid = from_le32(buffer);
3079 [ + - ]: 127 : if (nsid == 0xffffffffu) {
3080 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3081 : 0 : }
3082 : :
3083 : 123 : free_buffer:
3084 : 127 : spdk_dma_free(buffer);
3085 : 127 : return rc;
3086 : 4 : }
3087 : :
3088 : : void
3089 : 233 : nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr,
3090 : : const struct spdk_nvme_cpl *cpl)
3091 : : {
3092 : 5 : union spdk_nvme_async_event_completion event;
3093 : 5 : struct spdk_nvme_ctrlr_process *active_proc;
3094 : 5 : int rc;
3095 : :
3096 [ + - + - ]: 233 : event.raw = cpl->cdw0;
3097 : :
3098 [ + + + + ]: 233 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3099 [ + + ]: 167 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) {
3100 : 127 : nvme_ctrlr_clear_changed_ns_log(ctrlr);
3101 : :
3102 : 127 : rc = nvme_ctrlr_identify_active_ns(ctrlr);
3103 [ - + ]: 127 : if (rc) {
3104 : 0 : return;
3105 : : }
3106 : 127 : nvme_ctrlr_update_namespaces(ctrlr);
3107 : 127 : nvme_io_msg_ctrlr_update(ctrlr);
3108 : 4 : }
3109 : :
3110 [ + + + + ]: 233 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3111 [ + + ]: 167 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) {
3112 [ + + + + : 26 : if (!ctrlr->opts.disable_read_ana_log_page) {
+ - + - -
+ ]
3113 : 6 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
3114 [ - + ]: 6 : if (rc) {
3115 : 0 : return;
3116 : : }
3117 : 7 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
3118 : 1 : ctrlr);
3119 : 1 : }
3120 : 1 : }
3121 : :
3122 : 233 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3123 [ + - + + : 233 : if (active_proc && active_proc->aer_cb_fn) {
+ - + + ]
3124 [ + - + - : 102 : active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl);
- + + - +
- + - ]
3125 : 3 : }
3126 [ - + ]: 8 : }
3127 : :
3128 : : static void
3129 : 703 : nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr,
3130 : : const struct spdk_nvme_cpl *cpl)
3131 : : {
3132 : 5 : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event;
3133 : 5 : struct spdk_nvme_ctrlr_process *proc;
3134 : :
3135 : : /* Add async event to each process objects event list */
3136 [ + + + - : 1441 : TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) {
+ - + + +
- + - +
- ]
3137 : : /* Must be shared memory so other processes can access */
3138 : 738 : nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3139 [ + + ]: 738 : if (!nvme_event) {
3140 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3141 : 0 : return;
3142 : : }
3143 [ + - ]: 738 : nvme_event->cpl = *cpl;
3144 : :
3145 [ + - + - : 738 : STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link);
+ - + - +
- + - + -
+ - + - +
- + - +
- ]
3146 : 8 : }
3147 [ - + ]: 8 : }
3148 : :
3149 : : void
3150 : 49353347 : nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr)
3151 : : {
3152 : 5 : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event, *nvme_event_tmp;
3153 : 5 : struct spdk_nvme_ctrlr_process *active_proc;
3154 : :
3155 : 49353347 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3156 : :
3157 [ + + + - : 49353580 : STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) {
+ - + + +
- + - + -
+ + ]
3158 [ + - + + : 233 : STAILQ_REMOVE(&active_proc->async_events, nvme_event,
+ - - + +
- + - + -
+ - + - +
- + - + -
+ - - + +
- + - + -
+ - + - #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
3159 : : spdk_nvme_ctrlr_aer_completion_list, link);
3160 [ + - ]: 233 : nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl);
3161 : 233 : spdk_free(nvme_event);
3162 : :
3163 : 8 : }
3164 : 49353347 : }
3165 : :
3166 : : static void
3167 : 11501 : nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
3168 : : {
3169 : 11501 : struct nvme_async_event_request *aer = arg;
3170 [ + - + - ]: 11501 : struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
3171 : :
3172 [ + - + - : 15757 : if (cpl->status.sct == SPDK_NVME_SCT_GENERIC &&
+ - + - +
+ ]
3173 [ + + + - : 11501 : cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
+ - ]
3174 : : /*
3175 : : * This is simulated when controller is being shut down, to
3176 : : * effectively abort outstanding asynchronous event requests
3177 : : * and make sure all memory is freed. Do not repost the
3178 : : * request in this case.
3179 : : */
3180 : 10798 : return;
3181 : : }
3182 : :
3183 [ + + + - : 703 : if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
+ - - + #
# ]
3184 [ # # # # : 0 : cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) {
# # ]
3185 : : /*
3186 : : * SPDK will only send as many AERs as the device says it supports,
3187 : : * so this status code indicates an out-of-spec device. Do not repost
3188 : : * the request in this case.
3189 : : */
3190 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n"
# # # # #
# # # # #
# # # # #
# # # #
# ]
3191 : : "handling. Do not repost this AER.\n");
3192 : 0 : return;
3193 : : }
3194 : :
3195 : : /* Add the events to the list */
3196 : 703 : nvme_ctrlr_queue_async_event(ctrlr, cpl);
3197 : :
3198 : : /* If the ctrlr was removed or in the destruct state, we should not send aer again */
3199 [ + + + + : 703 : if (ctrlr->is_removed || ctrlr->is_destructed) {
+ + + + +
- + - + -
+ + ]
3200 : 146 : return;
3201 : : }
3202 : :
3203 : : /*
3204 : : * Repost another asynchronous event request to replace the one
3205 : : * that just completed.
3206 : : */
3207 [ + + ]: 557 : if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
3208 : : /*
3209 : : * We can't do anything to recover from a failure here,
3210 : : * so just print a warning message and leave the AER unsubmitted.
3211 : : */
3212 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3213 : 0 : }
3214 [ - + ]: 4256 : }
3215 : :
3216 : : static int
3217 : 11715 : nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
3218 : : struct nvme_async_event_request *aer)
3219 : : {
3220 : 24 : struct nvme_request *req;
3221 : :
3222 [ + - + - ]: 11715 : aer->ctrlr = ctrlr;
3223 [ + - + - ]: 11715 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer);
3224 [ + - + - ]: 11715 : aer->req = req;
3225 [ + + ]: 11715 : if (req == NULL) {
3226 : 0 : return -1;
3227 : : }
3228 : :
3229 [ + - + - ]: 11715 : req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
3230 : 11715 : return nvme_ctrlr_submit_admin_request(ctrlr, req);
3231 : 4275 : }
3232 : :
3233 : : static void
3234 : 2875 : nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl)
3235 : : {
3236 : 19 : struct nvme_async_event_request *aer;
3237 : 19 : int rc;
3238 : 19 : uint32_t i;
3239 : 2875 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3240 : :
3241 [ + - + + : 2875 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3242 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3243 [ # # # # ]: 0 : ctrlr->num_aers = 0;
3244 : 0 : } else {
3245 : : /* aerl is a zero-based value, so we need to add 1 here. */
3246 [ + - + - : 2875 : ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
+ - + - -
+ + - + -
+ - + - +
- + - ]
3247 : : }
3248 : :
3249 [ + + + - : 14033 : for (i = 0; i < ctrlr->num_aers; i++) {
+ + ]
3250 [ + - + - : 11158 : aer = &ctrlr->aer[i];
+ - ]
3251 : 11158 : rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
3252 [ + + ]: 11158 : if (rc) {
3253 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3254 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3255 : 0 : return;
3256 : : }
3257 : 4267 : }
3258 [ + - + - : 2875 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms);
+ - ]
3259 [ - + ]: 1081 : }
3260 : :
3261 : : static int
3262 : 2875 : nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
3263 : : {
3264 : 19 : union spdk_nvme_feat_async_event_configuration config;
3265 : 19 : int rc;
3266 : :
3267 : 2875 : config.raw = 0;
3268 : :
3269 [ + + ]: 2875 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3270 : 122 : config.bits.discovery_log_change_notice = 1;
3271 : 0 : } else {
3272 : 2753 : config.bits.crit_warn.bits.available_spare = 1;
3273 : 2753 : config.bits.crit_warn.bits.temperature = 1;
3274 : 2753 : config.bits.crit_warn.bits.device_reliability = 1;
3275 : 2753 : config.bits.crit_warn.bits.read_only = 1;
3276 : 2753 : config.bits.crit_warn.bits.volatile_memory_backup = 1;
3277 : :
3278 [ + + + - : 2753 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) {
+ - + - +
- + + ]
3279 [ + + + - : 2658 : if (ctrlr->cdata.oaes.ns_attribute_notices) {
+ - + + ]
3280 : 2531 : config.bits.ns_attr_notice = 1;
3281 : 1060 : }
3282 [ + + + - : 2658 : if (ctrlr->cdata.oaes.fw_activation_notices) {
+ - + + ]
3283 : 125 : config.bits.fw_activation_notice = 1;
3284 : 2 : }
3285 [ + + + - : 2658 : if (ctrlr->cdata.oaes.ana_change_notices) {
+ - + - ]
3286 : 15 : config.bits.ana_change_notice = 1;
3287 : 0 : }
3288 : 1066 : }
3289 [ + + + + : 2753 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) {
+ - + - +
- + + + -
+ - + - +
- ]
3290 : 23 : config.bits.telemetry_log_notice = 1;
3291 : 0 : }
3292 : : }
3293 : :
3294 : 3956 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER,
3295 [ + - + - : 2875 : ctrlr->opts.admin_timeout_ms);
+ - ]
3296 : :
3297 : 3956 : rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config,
3298 : : nvme_ctrlr_configure_aer_done,
3299 : 1081 : ctrlr);
3300 [ - + ]: 2875 : if (rc != 0) {
3301 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3302 : 0 : return rc;
3303 : : }
3304 : :
3305 : 2875 : return 0;
3306 : 1081 : }
3307 : :
3308 : : struct spdk_nvme_ctrlr_process *
3309 : 150397803 : nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid)
3310 : : {
3311 : 61 : struct spdk_nvme_ctrlr_process *active_proc;
3312 : :
3313 [ + + + - : 281565838 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
+ - + + #
# # # #
# ]
3314 [ + + + - : 281562578 : if (active_proc->pid == pid) {
- + ]
3315 : 150394543 : return active_proc;
3316 : : }
3317 : 0 : }
3318 : :
3319 : 3260 : return NULL;
3320 : 549745 : }
3321 : :
3322 : : struct spdk_nvme_ctrlr_process *
3323 : 150394605 : nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr)
3324 : : {
3325 : 150394605 : return nvme_ctrlr_get_process(ctrlr, getpid());
3326 : : }
3327 : :
3328 : : /**
3329 : : * This function will be called when a process is using the controller.
3330 : : * 1. For the primary process, it is called when constructing the controller.
3331 : : * 2. For the secondary process, it is called at probing the controller.
3332 : : * Note: will check whether the process is already added for the same process.
3333 : : */
3334 : : int
3335 : 2943 : nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
3336 : : {
3337 : 4 : struct spdk_nvme_ctrlr_process *ctrlr_proc;
3338 : 2943 : pid_t pid = getpid();
3339 : :
3340 : : /* Check whether the process is already added or not */
3341 [ + + ]: 2943 : if (nvme_ctrlr_get_process(ctrlr, pid)) {
3342 : 37 : return 0;
3343 : : }
3344 : :
3345 : : /* Initialize the per process properties for this ctrlr */
3346 : 2906 : ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process),
3347 : : 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3348 [ + + ]: 2906 : if (ctrlr_proc == NULL) {
3349 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3350 : :
3351 : 0 : return -1;
3352 : : }
3353 : :
3354 [ + - + - ]: 2906 : ctrlr_proc->is_primary = spdk_process_is_primary();
3355 [ + - + - ]: 2906 : ctrlr_proc->pid = pid;
3356 [ + - + - : 2906 : STAILQ_INIT(&ctrlr_proc->active_reqs);
+ - + - +
- + - + -
+ - ]
3357 [ + - + - ]: 2906 : ctrlr_proc->devhandle = devhandle;
3358 [ + - + - ]: 2906 : ctrlr_proc->ref = 0;
3359 [ + - + - : 2906 : TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs);
+ - + - +
- + - + -
+ - ]
3360 [ + - + - : 2906 : STAILQ_INIT(&ctrlr_proc->async_events);
+ - + - +
- + - + -
+ - ]
3361 : :
3362 [ + - + - : 2906 : TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq);
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - ]
3363 : :
3364 : 2906 : return 0;
3365 : 1066 : }
3366 : :
3367 : : /**
3368 : : * This function will be called when the process detaches the controller.
3369 : : * Note: the ctrlr_lock must be held when calling this function.
3370 : : */
3371 : : static void
3372 : 231 : nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr,
3373 : : struct spdk_nvme_ctrlr_process *proc)
3374 : : {
3375 : 1 : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3376 : :
3377 [ + + + - : 231 : assert(STAILQ_EMPTY(&proc->active_reqs));
+ - + - #
# ]
3378 : :
3379 [ + + + - : 251 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
+ - + - #
# # # # #
- + ]
3380 : 20 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3381 : 0 : }
3382 : :
3383 [ + + + - : 231 : TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq);
+ - - + #
# # # # #
# # # # #
# # # # #
# # + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - ]
3384 : :
3385 [ + - + - : 231 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
+ - - + ]
3386 [ + - + - ]: 231 : spdk_pci_device_detach(proc->devhandle);
3387 : 1 : }
3388 : :
3389 : 231 : spdk_free(proc);
3390 : 231 : }
3391 : :
3392 : : /**
3393 : : * This function will be called when the process exited unexpectedly
3394 : : * in order to free any incomplete nvme request, allocated IO qpairs
3395 : : * and allocated memory.
3396 : : * Note: the ctrlr_lock must be held when calling this function.
3397 : : */
3398 : : static void
3399 : 9 : nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc)
3400 : : {
3401 : 0 : struct nvme_request *req, *tmp_req;
3402 : 0 : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3403 : 0 : struct spdk_nvme_ctrlr_aer_completion_list *event;
3404 : :
3405 [ - + # # : 9 : STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
# # # # #
# # # # #
# # ]
3406 [ # # # # : 0 : STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
3407 : :
3408 [ # # # # : 0 : assert(req->pid == proc->pid);
# # # # #
# # # ]
3409 : 0 : nvme_cleanup_user_req(req);
3410 : 0 : nvme_free_request(req);
3411 : 0 : }
3412 : :
3413 : : /* Remove async event from each process objects event list */
3414 [ - + # # : 9 : while (!STAILQ_EMPTY(&proc->async_events)) {
# # # # ]
3415 [ # # # # : 0 : event = STAILQ_FIRST(&proc->async_events);
# # ]
3416 [ # # # # : 0 : STAILQ_REMOVE_HEAD(&proc->async_events, link);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3417 : 0 : spdk_free(event);
3418 : : }
3419 : :
3420 [ - + # # : 9 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
# # # # #
# # # # #
# # ]
3421 [ # # # # : 0 : TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
3422 : :
3423 : : /*
3424 : : * The process may have been killed while some qpairs were in their
3425 : : * completion context. Clear that flag here to allow these IO
3426 : : * qpairs to be deleted.
3427 : : */
3428 [ # # ]: 0 : qpair->in_completion_context = 0;
3429 : :
3430 [ # # ]: 0 : qpair->no_deletion_notification_needed = 1;
3431 : :
3432 : 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3433 : 0 : }
3434 : :
3435 : 9 : spdk_free(proc);
3436 : 9 : }
3437 : :
3438 : : /**
3439 : : * This function will be called when destructing the controller.
3440 : : * 1. There is no more admin request on this controller.
3441 : : * 2. Clean up any left resource allocation when its associated process is gone.
3442 : : */
3443 : : void
3444 : 2949 : nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr)
3445 : : {
3446 : 49 : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3447 : :
3448 : : /* Free all the processes' properties and make sure no pending admin IOs */
3449 [ + + + - : 5611 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
+ - + + +
- + - + -
+ + ]
3450 [ + + + - : 2662 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
+ - - + #
# # # # #
# # # # #
# # # # #
# # + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - ]
3451 : :
3452 [ + + + - : 2662 : assert(STAILQ_EMPTY(&active_proc->active_reqs));
+ - + - #
# ]
3453 : :
3454 : 2662 : spdk_free(active_proc);
3455 : 1065 : }
3456 : 2949 : }
3457 : :
3458 : : /**
3459 : : * This function will be called when any other process attaches or
3460 : : * detaches the controller in order to cleanup those unexpectedly
3461 : : * terminated processes.
3462 : : * Note: the ctrlr_lock must be held when calling this function.
3463 : : */
3464 : : static int
3465 : 8326 : nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr)
3466 : : {
3467 : 0 : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3468 : 8326 : int active_proc_count = 0;
3469 : :
3470 [ + + + - : 17555 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
+ - + + +
- + - + -
+ + ]
3471 [ + + + - : 9229 : if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) {
- + # # #
# ]
3472 [ + - - + : 9 : NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
3473 : :
3474 [ + - # # : 9 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
3475 : :
3476 : 9 : nvme_ctrlr_cleanup_process(active_proc);
3477 : 0 : } else {
3478 [ + - ]: 9220 : active_proc_count++;
3479 : : }
3480 : 3186 : }
3481 : :
3482 : 8326 : return active_proc_count;
3483 : 0 : }
3484 : :
3485 : : void
3486 : 2784 : nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr)
3487 : : {
3488 : 0 : struct spdk_nvme_ctrlr_process *active_proc;
3489 : :
3490 : 2784 : nvme_ctrlr_lock(ctrlr);
3491 : :
3492 : 2784 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3493 : :
3494 : 2784 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3495 [ + - ]: 2784 : if (active_proc) {
3496 [ + - + - ]: 2784 : active_proc->ref++;
3497 : 1062 : }
3498 : :
3499 : 2784 : nvme_ctrlr_unlock(ctrlr);
3500 : 2784 : }
3501 : :
3502 : : void
3503 : 2771 : nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr)
3504 : : {
3505 : 0 : struct spdk_nvme_ctrlr_process *active_proc;
3506 : 0 : int proc_count;
3507 : :
3508 : 2771 : nvme_ctrlr_lock(ctrlr);
3509 : :
3510 : 2771 : proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr);
3511 : :
3512 : 2771 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3513 [ + + ]: 2771 : if (active_proc) {
3514 [ + - + - ]: 2771 : active_proc->ref--;
3515 [ + + + - : 2771 : assert(active_proc->ref >= 0);
+ - # # ]
3516 : :
3517 : : /*
3518 : : * The last active process will be removed at the end of
3519 : : * the destruction of the controller.
3520 : : */
3521 [ + - + + : 2771 : if (active_proc->ref == 0 && proc_count != 1) {
+ - + - ]
3522 : 225 : nvme_ctrlr_remove_process(ctrlr, active_proc);
3523 : 0 : }
3524 : 1062 : }
3525 : :
3526 : 2771 : nvme_ctrlr_unlock(ctrlr);
3527 : 2771 : }
3528 : :
3529 : : int
3530 : 2771 : nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr)
3531 : : {
3532 : 0 : struct spdk_nvme_ctrlr_process *active_proc;
3533 : 2771 : int ref = 0;
3534 : :
3535 : 2771 : nvme_ctrlr_lock(ctrlr);
3536 : :
3537 : 2771 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3538 : :
3539 [ + + + - : 5837 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
+ - + + +
- + - +
- ]
3540 [ + - + - : 3066 : ref += active_proc->ref;
+ - ]
3541 : 1062 : }
3542 : :
3543 : 2771 : nvme_ctrlr_unlock(ctrlr);
3544 : :
3545 : 2771 : return ref;
3546 : 0 : }
3547 : :
3548 : : /**
3549 : : * Get the PCI device handle which is only visible to its associated process.
3550 : : */
3551 : : struct spdk_pci_device *
3552 : 791 : nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr)
3553 : : {
3554 : 0 : struct spdk_nvme_ctrlr_process *active_proc;
3555 : 791 : struct spdk_pci_device *devhandle = NULL;
3556 : :
3557 : 791 : nvme_ctrlr_lock(ctrlr);
3558 : :
3559 : 791 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3560 [ + - ]: 791 : if (active_proc) {
3561 [ + - + - ]: 791 : devhandle = active_proc->devhandle;
3562 : 2 : }
3563 : :
3564 : 791 : nvme_ctrlr_unlock(ctrlr);
3565 : :
3566 : 791 : return devhandle;
3567 : 0 : }
3568 : :
3569 : : static void
3570 : 2887 : nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3571 : : {
3572 : 2887 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3573 : :
3574 [ + - + + : 2887 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3575 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3576 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3577 : 0 : return;
3578 : : }
3579 : :
3580 [ + + # # ]: 2887 : assert(value <= UINT32_MAX);
3581 [ + - + - : 2887 : ctrlr->vs.raw = (uint32_t)value;
+ - ]
3582 : 2887 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE);
3583 [ - + ]: 1083 : }
3584 : :
3585 : : static void
3586 : 2887 : nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3587 : : {
3588 : 2887 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3589 : :
3590 [ + - + + : 2887 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
+ + ]
3591 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3592 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3593 : 0 : return;
3594 : : }
3595 : :
3596 [ + - + - : 2887 : ctrlr->cap.raw = value;
+ - ]
3597 : 2887 : nvme_ctrlr_init_cap(ctrlr);
3598 : 2887 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
3599 [ - + ]: 1083 : }
3600 : :
3601 : : static void
3602 : 2979 : nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3603 : : {
3604 : 2979 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3605 : 22 : enum nvme_ctrlr_state state;
3606 : :
3607 [ + - + + : 2979 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3608 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3609 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3610 : 0 : return;
3611 : : }
3612 : :
3613 [ + + # # ]: 2979 : assert(value <= UINT32_MAX);
3614 [ + - + - : 2979 : ctrlr->process_init_cc.raw = (uint32_t)value;
+ - ]
3615 : :
3616 [ + + + - : 2979 : if (ctrlr->process_init_cc.bits.en) {
+ - + + ]
3617 [ + + + + : 637 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3618 : 637 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1;
3619 : 2 : } else {
3620 : 2342 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0;
3621 : : }
3622 : :
3623 : 2979 : nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr));
3624 [ - + ]: 1084 : }
3625 : :
3626 : : static void
3627 : 637 : nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3628 : : {
3629 : 637 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3630 : :
3631 [ + - + + : 637 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3632 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3633 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3634 : 0 : return;
3635 : : }
3636 : :
3637 : : /*
3638 : : * Wait 2.5 seconds before accessing PCI registers.
3639 : : * Not using sleep() to avoid blocking other controller's initialization.
3640 : : */
3641 [ + + + - : 637 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
+ - ]
3642 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3643 [ # # # # : 0 : ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000);
# # ]
3644 : 0 : }
3645 : :
3646 : 639 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3647 : 2 : nvme_ctrlr_get_ready_timeout(ctrlr));
3648 [ - + ]: 2 : }
3649 : :
3650 : : static void
3651 : 637 : nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3652 : : {
3653 : 637 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3654 : 2 : union spdk_nvme_cc_register cc;
3655 : 2 : int rc;
3656 : :
3657 [ + - + + : 637 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3658 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3659 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3660 : 0 : return;
3661 : : }
3662 : :
3663 [ + + # # ]: 637 : assert(value <= UINT32_MAX);
3664 : 637 : cc.raw = (uint32_t)value;
3665 : 637 : cc.bits.en = 0;
3666 [ + - + - : 637 : ctrlr->process_init_cc.raw = cc.raw;
+ - ]
3667 : :
3668 : 639 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC,
3669 : 2 : nvme_ctrlr_get_ready_timeout(ctrlr));
3670 : :
3671 : 637 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr);
3672 [ + + ]: 637 : if (rc != 0) {
3673 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3674 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3675 : 0 : }
3676 [ - + ]: 2 : }
3677 : :
3678 : : static void
3679 : 637 : nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3680 : : {
3681 : 637 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3682 : 2 : union spdk_nvme_csts_register csts;
3683 : :
3684 [ + - + + : 637 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3685 : : /* While a device is resetting, it may be unable to service MMIO reads
3686 : : * temporarily. Allow for this case.
3687 : : */
3688 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # # # #
# # # #
# ]
3689 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3690 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3691 : : NVME_TIMEOUT_KEEP_EXISTING);
3692 : 0 : } else {
3693 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3694 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3695 : : }
3696 : :
3697 : 0 : return;
3698 : : }
3699 : :
3700 [ + + # # ]: 637 : assert(value <= UINT32_MAX);
3701 : 637 : csts.raw = (uint32_t)value;
3702 [ - + - - ]: 637 : if (csts.bits.rdy == 1 || csts.bits.cfs == 1) {
3703 : 639 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0,
3704 : 2 : nvme_ctrlr_get_ready_timeout(ctrlr));
3705 : 2 : } else {
3706 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3707 : 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3708 : : NVME_TIMEOUT_KEEP_EXISTING);
3709 : : }
3710 [ - + ]: 2 : }
3711 : :
3712 : : static void
3713 : 3770 : nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3714 : : {
3715 : 3770 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3716 : 22 : union spdk_nvme_csts_register csts;
3717 : :
3718 [ + - + + : 3770 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3719 : : /* While a device is resetting, it may be unable to service MMIO reads
3720 : : * temporarily. Allow for this case.
3721 : : */
3722 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # # # #
# # # #
# ]
3723 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3724 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3725 : : NVME_TIMEOUT_KEEP_EXISTING);
3726 : 0 : } else {
3727 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3728 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3729 : : }
3730 : :
3731 : 0 : return;
3732 : : }
3733 : :
3734 [ + + # # ]: 3770 : assert(value <= UINT32_MAX);
3735 : 3770 : csts.raw = (uint32_t)value;
3736 [ + + ]: 3770 : if (csts.bits.rdy == 0) {
3737 [ + + + + : 2979 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n");
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3738 : 4063 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED,
3739 : 1084 : nvme_ctrlr_get_ready_timeout(ctrlr));
3740 : 1084 : } else {
3741 : 791 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3742 : : NVME_TIMEOUT_KEEP_EXISTING);
3743 : : }
3744 [ - + ]: 1084 : }
3745 : :
3746 : : static void
3747 : 34260 : nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value,
3748 : : const struct spdk_nvme_cpl *cpl)
3749 : : {
3750 : 34260 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3751 : 9 : union spdk_nvme_csts_register csts;
3752 : :
3753 [ + - + + : 34260 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3754 : : /* While a device is resetting, it may be unable to service MMIO reads
3755 : : * temporarily. Allow for this case.
3756 : : */
3757 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # # # #
# # # #
# ]
3758 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3759 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3760 : : NVME_TIMEOUT_KEEP_EXISTING);
3761 : 0 : } else {
3762 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
3763 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3764 : : }
3765 : :
3766 : 0 : return;
3767 : : }
3768 : :
3769 [ + + # # ]: 34260 : assert(value <= UINT32_MAX);
3770 : 34260 : csts.raw = value;
3771 [ + + ]: 34260 : if (csts.bits.rdy == 1) {
3772 [ + + + + : 2815 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3773 : : /*
3774 : : * The controller has been enabled.
3775 : : * Perform the rest of initialization serially.
3776 : : */
3777 : 3886 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
3778 [ + - + - : 2815 : ctrlr->opts.admin_timeout_ms);
+ - ]
3779 : 1071 : } else {
3780 : 31445 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3781 : : NVME_TIMEOUT_KEEP_EXISTING);
3782 : : }
3783 [ - + ]: 3964 : }
3784 : :
3785 : : /**
3786 : : * This function will be called repeatedly during initialization until the controller is ready.
3787 : : */
3788 : : int
3789 : 147723782 : nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
3790 : : {
3791 : 430 : uint32_t ready_timeout_in_ms;
3792 : 430 : uint64_t ticks;
3793 : 147723782 : int rc = 0;
3794 : :
3795 : 147723782 : ticks = spdk_get_ticks();
3796 : :
3797 : : /*
3798 : : * May need to avoid accessing any register on the target controller
3799 : : * for a while. Return early without touching the FSM.
3800 : : * Check sleep_timeout_tsc > 0 for unit test.
3801 : : */
3802 [ + + + - : 179453099 : if ((ctrlr->sleep_timeout_tsc > 0) &&
+ + + + ]
3803 [ + + + - ]: 143179729 : (ticks <= ctrlr->sleep_timeout_tsc)) {
3804 : 143179633 : return 0;
3805 : : }
3806 [ + - + - ]: 4544149 : ctrlr->sleep_timeout_tsc = 0;
3807 : :
3808 : 4544149 : ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr);
3809 : :
3810 : : /*
3811 : : * Check if the current initialization step is done or has timed out.
3812 : : */
3813 [ + - + + : 4544149 : switch (ctrlr->state) {
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + - - ]
3814 : 653 : case NVME_CTRLR_STATE_INIT_DELAY:
3815 : 656 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms);
3816 [ + + + - : 656 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) {
- + ]
3817 : : /*
3818 : : * Controller may need some delay before it's enabled.
3819 : : *
3820 : : * This is a workaround for an issue where the PCIe-attached NVMe controller
3821 : : * is not ready after VFIO reset. We delay the initialization rather than the
3822 : : * enabling itself, because this is required only for the very first enabling
3823 : : * - directly after a VFIO reset.
3824 : : */
3825 [ + + + + : 96 : NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3826 [ + - + - : 96 : ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000);
+ - ]
3827 : 3 : }
3828 : 656 : break;
3829 : :
3830 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
3831 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
3832 : 0 : break;
3833 : :
3834 : 2234 : case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */
3835 [ + - + - ]: 3317 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq);
3836 [ + + ]: 3317 : if (rc == 0) {
3837 : 3317 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ,
3838 : : NVME_TIMEOUT_INFINITE);
3839 : 1083 : } else {
3840 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3841 : : }
3842 : 3317 : break;
3843 : :
3844 : 1488930 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
3845 [ + - + - ]: 1918519 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3846 : :
3847 [ + + + + : 1918519 : switch (nvme_qpair_get_state(ctrlr->adminq)) {
+ + - - +
- ]
3848 : 890743 : case NVME_QPAIR_CONNECTING:
3849 : 1319249 : break;
3850 : 1121 : case NVME_QPAIR_CONNECTED:
3851 [ + - + - ]: 2195 : nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED);
3852 : : /* Fall through */
3853 : 1804 : case NVME_QPAIR_ENABLED:
3854 : 2887 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS,
3855 : : NVME_TIMEOUT_INFINITE);
3856 : : /* Abort any queued requests that were sent while the adminq was connecting
3857 : : * to avoid stalling the init process during a reset, as requests don't get
3858 : : * resubmitted while the controller is resetting and subsequent commands
3859 : : * would get queued too.
3860 : : */
3861 [ - + - + ]: 2887 : nvme_qpair_abort_queued_reqs(ctrlr->adminq);
3862 : 2887 : break;
3863 : 595956 : case NVME_QPAIR_DISCONNECTING:
3864 [ - + # # : 595956 : assert(ctrlr->adminq->async == true);
# # # # #
# ]
3865 : 595956 : break;
3866 : 427 : case NVME_QPAIR_DISCONNECTED:
3867 : : /* fallthrough */
3868 : : default:
3869 : 427 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3870 : 427 : break;
3871 : : }
3872 : :
3873 : 1918519 : break;
3874 : :
3875 : 1804 : case NVME_CTRLR_STATE_READ_VS:
3876 : 2887 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE);
3877 : 2887 : rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr);
3878 : 2887 : break;
3879 : :
3880 : 1804 : case NVME_CTRLR_STATE_READ_CAP:
3881 : 2887 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE);
3882 : 2887 : rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr);
3883 : 2887 : break;
3884 : :
3885 : 1895 : case NVME_CTRLR_STATE_CHECK_EN:
3886 : : /* Begin the hardware initialization by making sure the controller is disabled. */
3887 : 2979 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms);
3888 : 2979 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr);
3889 : 2979 : break;
3890 : :
3891 : 635 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
3892 : : /*
3893 : : * Controller is currently enabled. We need to disable it to cause a reset.
3894 : : *
3895 : : * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
3896 : : * Wait for the ready bit to be 1 before disabling the controller.
3897 : : */
3898 : 637 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3899 : : NVME_TIMEOUT_KEEP_EXISTING);
3900 : 637 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr);
3901 : 637 : break;
3902 : :
3903 : 635 : case NVME_CTRLR_STATE_SET_EN_0:
3904 [ + + + + : 637 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n");
+ - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3905 : 637 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms);
3906 : 637 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr);
3907 : 637 : break;
3908 : :
3909 : 2686 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
3910 : 3770 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS,
3911 : : NVME_TIMEOUT_KEEP_EXISTING);
3912 : 3770 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr);
3913 : 3770 : break;
3914 : :
3915 : 1890 : case NVME_CTRLR_STATE_DISABLED:
3916 [ + + + + : 2973 : if (ctrlr->is_disconnecting) {
+ - - + ]
3917 [ - + - + : 86 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n");
- - - - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3918 : 0 : } else {
3919 : 2887 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
3920 : :
3921 : : /*
3922 : : * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting
3923 : : * set to 1 if it is too soon after CSTS.RDY is reported as 0.
3924 : : */
3925 : 2887 : spdk_delay_us(100);
3926 : : }
3927 : 2973 : break;
3928 : :
3929 : 1804 : case NVME_CTRLR_STATE_ENABLE:
3930 [ + + + + : 2887 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n");
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3931 : 2887 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms);
3932 : 2887 : rc = nvme_ctrlr_enable(ctrlr);
3933 [ + + ]: 2887 : if (rc) {
3934 [ + - + + : 42 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc);
+ - + - +
- + - + -
- + # # #
# + - +
- ]
3935 : 7 : }
3936 : 2887 : return rc;
3937 : :
3938 : 30296 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
3939 : 34260 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3940 : : NVME_TIMEOUT_KEEP_EXISTING);
3941 : 34260 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1,
3942 : : ctrlr);
3943 : 34260 : break;
3944 : :
3945 : 1744 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
3946 [ + - + - ]: 2815 : nvme_transport_qpair_reset(ctrlr->adminq);
3947 : 2815 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE);
3948 : 2815 : break;
3949 : :
3950 : 1779 : case NVME_CTRLR_STATE_IDENTIFY:
3951 : 2857 : rc = nvme_ctrlr_identify(ctrlr);
3952 : 2857 : break;
3953 : :
3954 : 1794 : case NVME_CTRLR_STATE_CONFIGURE_AER:
3955 : 2875 : rc = nvme_ctrlr_configure_aer(ctrlr);
3956 : 2875 : break;
3957 : :
3958 : 1809 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
3959 : 2893 : rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
3960 : 2893 : break;
3961 : :
3962 : 1672 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
3963 : 2753 : rc = nvme_ctrlr_identify_iocs_specific(ctrlr);
3964 : 2753 : break;
3965 : :
3966 : 615 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
3967 : 615 : rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr);
3968 : 615 : break;
3969 : :
3970 : 1672 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
3971 : 2753 : nvme_ctrlr_update_nvmf_ioccsz(ctrlr);
3972 : 2753 : rc = nvme_ctrlr_set_num_queues(ctrlr);
3973 : 2753 : break;
3974 : :
3975 : 1697 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
3976 : 2783 : _nvme_ctrlr_identify_active_ns(ctrlr);
3977 : 2783 : break;
3978 : :
3979 : 1647 : case NVME_CTRLR_STATE_IDENTIFY_NS:
3980 : 2723 : rc = nvme_ctrlr_identify_namespaces(ctrlr);
3981 : 2723 : break;
3982 : :
3983 : 1647 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
3984 : 2723 : rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr);
3985 : 2723 : break;
3986 : :
3987 : 1647 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
3988 : 2723 : rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr);
3989 : 2723 : break;
3990 : :
3991 : 1652 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
3992 : 2729 : rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
3993 : 2729 : break;
3994 : :
3995 : 111 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
3996 : 114 : rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr);
3997 : 114 : break;
3998 : :
3999 : 1647 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
4000 : 2723 : nvme_ctrlr_set_supported_features(ctrlr);
4001 : 3799 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
4002 [ + - + - : 2723 : ctrlr->opts.admin_timeout_ms);
+ - ]
4003 : 2723 : break;
4004 : :
4005 : 1647 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
4006 : 2723 : rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
4007 : 2723 : break;
4008 : :
4009 : 1647 : case NVME_CTRLR_STATE_SET_HOST_ID:
4010 : 2723 : rc = nvme_ctrlr_set_host_id(ctrlr);
4011 : 2723 : break;
4012 : :
4013 : 1662 : case NVME_CTRLR_STATE_TRANSPORT_READY:
4014 : 2741 : rc = nvme_transport_ctrlr_ready(ctrlr);
4015 [ + + ]: 2741 : if (rc) {
4016 [ + - + + : 6 : NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc);
+ - + - +
- + - + -
- + # # #
# + - +
- ]
4017 : 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4018 : 1 : } else {
4019 : 2735 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
4020 : : }
4021 : 2741 : break;
4022 : :
4023 : 37 : case NVME_CTRLR_STATE_READY:
4024 [ - + + + : 37 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n");
+ + + - #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
4025 : 37 : return 0;
4026 : :
4027 : 434 : case NVME_CTRLR_STATE_ERROR:
4028 [ + + + - : 434 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4029 : 434 : return -1;
4030 : :
4031 : 2303000 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
4032 : : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
4033 : : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
4034 : : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
4035 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4036 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
4037 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
4038 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4039 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
4040 : : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
4041 : : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
4042 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
4043 : : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
4044 : : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
4045 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
4046 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
4047 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
4048 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
4049 : : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
4050 : : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
4051 : : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
4052 : : /*
4053 : : * nvme_ctrlr_process_init() may be called from the completion context
4054 : : * for the admin qpair. Avoid recursive calls for this case.
4055 : : */
4056 [ + + + - : 2525003 : if (!ctrlr->adminq->in_completion_context) {
+ - - + ]
4057 [ + - + - ]: 2524917 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4058 : 222003 : }
4059 : 2525003 : break;
4060 : :
4061 : 0 : default:
4062 [ # # ]: 0 : assert(0);
4063 : : return -1;
4064 : : }
4065 : :
4066 [ + + ]: 4540791 : if (rc) {
4067 [ + - + + : 6 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n",
+ - + - +
- + - + -
- + # # #
# + - + -
+ - + - +
- + - ]
4068 : : rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4069 : 1 : }
4070 : :
4071 : : /* Note: we use the ticks captured when we entered this function.
4072 : : * This covers environments where the SPDK process gets swapped out after
4073 : : * we tried to advance the state but before we check the timeout here.
4074 : : * It is not normal for this to happen, but harmless to handle it in this
4075 : : * way.
4076 : : */
4077 [ + + + - : 4762813 : if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
+ + + - ]
4078 [ + + + - ]: 2497179 : ticks > ctrlr->state_timeout_tsc) {
4079 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
4080 : : ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4081 : 0 : return -1;
4082 : : }
4083 : :
4084 : 4540791 : return rc;
4085 : 32408637 : }
4086 : :
4087 : : int
4088 : 2935 : nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx)
4089 : : {
4090 : 599 : pthread_mutexattr_t attr;
4091 : 2935 : int rc = 0;
4092 : :
4093 [ + + - + ]: 2935 : if (pthread_mutexattr_init(&attr)) {
4094 : 0 : return -1;
4095 : : }
4096 [ + + + - : 5870 : if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
+ + ]
4097 : : #ifndef __FreeBSD__
4098 [ + + + - ]: 4762 : pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) ||
4099 [ + + + + ]: 4762 : pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) ||
4100 : : #endif
4101 [ + + ]: 2935 : pthread_mutex_init(mtx, &attr)) {
4102 : 0 : rc = -1;
4103 : 0 : }
4104 [ + + ]: 2935 : pthread_mutexattr_destroy(&attr);
4105 : 2935 : return rc;
4106 : 1108 : }
4107 : :
4108 : : int
4109 : 2935 : nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
4110 : : {
4111 : 46 : int rc;
4112 : :
4113 [ + + + - : 2935 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
+ - + + ]
4114 : 656 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE);
4115 : 3 : } else {
4116 : 2279 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
4117 : : }
4118 : :
4119 [ + + + - : 2935 : if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) {
+ - + - ]
4120 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
4121 : : ctrlr->opts.admin_queue_size);
4122 [ # # # # : 0 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES;
# # ]
4123 : 0 : }
4124 : :
4125 [ + + + - : 2935 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE &&
- + # # ]
4126 [ # # # # : 0 : (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) {
# # # # ]
4127 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr,
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
4128 : : "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n",
4129 : : ctrlr->opts.admin_queue_size);
4130 [ # # # # : 0 : ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size,
# # # # #
# # # #
# ]
4131 : : SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE);
4132 : 0 : }
4133 : :
4134 [ + + + - : 2935 : if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) {
+ - + + ]
4135 [ + - + + : 150 : NVME_CTRLR_ERRLOG(ctrlr,
+ - + - +
- + - + -
- + # # #
# + - + -
+ - + - +
- ]
4136 : : "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n",
4137 : : ctrlr->opts.admin_queue_size);
4138 [ + - + - : 150 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES;
+ - ]
4139 : 25 : }
4140 : :
4141 [ + - + - ]: 2935 : ctrlr->flags = 0;
4142 [ + - + - ]: 2935 : ctrlr->free_io_qids = NULL;
4143 [ + - + - ]: 2935 : ctrlr->is_resetting = false;
4144 [ + - + - ]: 2935 : ctrlr->is_failed = false;
4145 [ + - + - ]: 2935 : ctrlr->is_destructed = false;
4146 : :
4147 [ + - + - : 2935 : TAILQ_INIT(&ctrlr->active_io_qpairs);
+ - + - +
- + - + -
+ - ]
4148 [ + - + - : 2935 : STAILQ_INIT(&ctrlr->queued_aborts);
+ - + - +
- + - + -
+ - ]
4149 [ + - + - ]: 2935 : ctrlr->outstanding_aborts = 0;
4150 : :
4151 [ + - + - ]: 2935 : ctrlr->ana_log_page = NULL;
4152 [ + - + - ]: 2935 : ctrlr->ana_log_page_size = 0;
4153 : :
4154 [ + - ]: 2935 : rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock);
4155 [ - + ]: 2935 : if (rc != 0) {
4156 : 0 : return rc;
4157 : : }
4158 : :
4159 [ + - + - : 2935 : TAILQ_INIT(&ctrlr->active_procs);
+ - + - +
- + - + -
+ - ]
4160 [ + - + - : 2935 : STAILQ_INIT(&ctrlr->register_operations);
+ - + - +
- + - + -
+ - ]
4161 : :
4162 [ + - + - : 2935 : RB_INIT(&ctrlr->ns);
+ - ]
4163 : :
4164 : 2935 : return rc;
4165 : 1108 : }
4166 : :
4167 : : static void
4168 : 2887 : nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr)
4169 : : {
4170 [ + + + - : 2887 : if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
+ - + + ]
4171 [ + - + - ]: 155 : ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
4172 : 7 : }
4173 : :
4174 [ + + + - : 2887 : ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin);
+ - + - +
- + - +
- ]
4175 : :
4176 : : /* For now, always select page_size == min_page_size. */
4177 [ + - + - : 2887 : ctrlr->page_size = ctrlr->min_page_size;
+ - + - ]
4178 : :
4179 [ + - + - : 2887 : ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES);
+ - + + +
- + - + -
+ - + - +
- ]
4180 [ + - + - : 2887 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES);
+ - + - +
- + - + -
+ - # # +
- + - +
- ]
4181 [ + + + - : 2889 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE &&
+ + - + ]
4182 [ + + + - : 103 : ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) {
+ - ]
4183 : : /* If the user specifically set an IO queue size different than the
4184 : : * default, use that value. Otherwise overwrite with the quirked value.
4185 : : * This allows this quirk to be overridden when necessary.
4186 : : * However, cap.mqes still needs to be respected.
4187 : : */
4188 [ + - + - : 90 : ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK;
+ - ]
4189 : 2 : }
4190 [ + - + - : 2887 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u);
+ - + - +
- + - + +
+ - + - +
- + - + -
+ - + - +
- + - ]
4191 : :
4192 [ + - + - : 2887 : ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size);
+ - + - +
- + - + +
+ - + - +
- + - + -
+ - + - +
- + - ]
4193 : 2887 : }
4194 : :
4195 : : void
4196 : 2931 : nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr)
4197 : : {
4198 : 46 : int rc;
4199 : :
4200 [ + + + - : 2931 : if (ctrlr->lock_depth > 0) {
+ - ]
4201 [ # # # # ]: 0 : SPDK_ERRLOG("lock currently held (depth=%d)!\n", ctrlr->lock_depth);
4202 [ # # ]: 0 : assert(false);
4203 : : }
4204 : :
4205 [ + + + - ]: 2931 : rc = pthread_mutex_destroy(&ctrlr->ctrlr_lock);
4206 [ + + ]: 2931 : if (rc) {
4207 : 0 : SPDK_ERRLOG("could not destroy ctrlr_lock: %s\n", spdk_strerror(rc));
4208 [ # # ]: 0 : assert(false);
4209 : : }
4210 : :
4211 : 2931 : nvme_ctrlr_free_processes(ctrlr);
4212 : 2931 : }
4213 : :
4214 : : void
4215 : 2920 : nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr,
4216 : : struct nvme_ctrlr_detach_ctx *ctx)
4217 : : {
4218 : 46 : struct spdk_nvme_qpair *qpair, *tmp;
4219 : :
4220 [ + + + + : 2920 : NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n");
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
4221 : :
4222 [ + - + - ]: 2920 : ctrlr->prepare_for_reset = false;
4223 [ + - + - ]: 2920 : ctrlr->is_destructed = true;
4224 : :
4225 [ + - + - ]: 2920 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4226 : :
4227 : 2920 : nvme_ctrlr_abort_queued_aborts(ctrlr);
4228 [ + - + - ]: 2920 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
4229 : :
4230 [ + + + - : 3084 : TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) {
+ - + + +
- + - + -
+ + ]
4231 : 164 : spdk_nvme_ctrlr_free_io_qpair(qpair);
4232 : 1 : }
4233 : :
4234 : 2920 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
4235 : 2920 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
4236 : :
4237 : 2920 : nvme_ctrlr_shutdown_async(ctrlr, ctx);
4238 : 2920 : }
4239 : :
4240 : : int
4241 : 19140096 : nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr,
4242 : : struct nvme_ctrlr_detach_ctx *ctx)
4243 : : {
4244 : 84 : struct spdk_nvme_ns *ns, *tmp_ns;
4245 : 19140096 : int rc = 0;
4246 : :
4247 [ + + + + : 19140096 : if (!ctx->shutdown_complete) {
+ - + + ]
4248 : 19139971 : rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx);
4249 [ + + ]: 19139971 : if (rc == -EAGAIN) {
4250 : 19137176 : return -EAGAIN;
4251 : : }
4252 : : /* Destruct ctrlr forcefully for any other error. */
4253 : 1100 : }
4254 : :
4255 [ + + + - : 2920 : if (ctx->cb_fn) {
+ + ]
4256 [ + - + - : 2546 : ctx->cb_fn(ctrlr);
- + + - ]
4257 : 1062 : }
4258 : :
4259 [ + - + - ]: 2920 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
4260 : :
4261 [ + + + + : 51525 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
+ + ]
4262 [ + - + - ]: 48605 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
4263 [ + - ]: 48605 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
4264 : 48605 : spdk_free(ns);
4265 : 8748 : }
4266 : :
4267 [ + - + - ]: 2920 : ctrlr->active_ns_count = 0;
4268 : :
4269 [ + - ]: 2920 : spdk_bit_array_free(&ctrlr->free_io_qids);
4270 : :
4271 [ + - + - ]: 2920 : free(ctrlr->ana_log_page);
4272 [ + - + - ]: 2920 : free(ctrlr->copied_ana_desc);
4273 [ + - + - ]: 2920 : ctrlr->ana_log_page = NULL;
4274 [ + - + - ]: 2920 : ctrlr->copied_ana_desc = NULL;
4275 [ + - + - ]: 2920 : ctrlr->ana_log_page_size = 0;
4276 : :
4277 : 2920 : nvme_transport_ctrlr_destruct(ctrlr);
4278 : :
4279 : 2920 : return rc;
4280 : 1240931 : }
4281 : :
4282 : : void
4283 : 374 : nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
4284 : : {
4285 : 374 : struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr };
4286 : 46 : int rc;
4287 : :
4288 : 374 : nvme_ctrlr_destruct_async(ctrlr, &ctx);
4289 : :
4290 : 84 : while (1) {
4291 : 1151 : rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx);
4292 [ + + ]: 1151 : if (rc != -EAGAIN) {
4293 : 374 : break;
4294 : : }
4295 : 777 : nvme_delay(1000);
4296 : : }
4297 : 374 : }
4298 : :
4299 : : int
4300 : 1325829 : nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
4301 : : struct nvme_request *req)
4302 : : {
4303 [ + - + - ]: 1325829 : return nvme_qpair_submit_request(ctrlr->adminq, req);
4304 : : }
4305 : :
4306 : : static void
4307 : 1786 : nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl)
4308 : : {
4309 : : /* Do nothing */
4310 : 1786 : }
4311 : :
4312 : : /*
4313 : : * Check if we need to send a Keep Alive command.
4314 : : * Caller must hold ctrlr->ctrlr_lock.
4315 : : */
4316 : : static int
4317 : 4914746 : nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr)
4318 : : {
4319 : 0 : uint64_t now;
4320 : 0 : struct nvme_request *req;
4321 : 0 : struct spdk_nvme_cmd *cmd;
4322 : 4914746 : int rc = 0;
4323 : :
4324 : 4914746 : now = spdk_get_ticks();
4325 [ + + + - : 4914746 : if (now < ctrlr->next_keep_alive_tick) {
+ + ]
4326 : 4868229 : return rc;
4327 : : }
4328 : :
4329 [ + - + - ]: 46517 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL);
4330 [ + + ]: 46517 : if (req == NULL) {
4331 : 44728 : return rc;
4332 : : }
4333 : :
4334 [ + - ]: 1789 : cmd = &req->cmd;
4335 [ + - ]: 1789 : cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE;
4336 : :
4337 : 1789 : rc = nvme_ctrlr_submit_admin_request(ctrlr, req);
4338 [ + + ]: 1789 : if (rc != 0) {
4339 [ + + + - : 3 : NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4340 : 3 : rc = -ENXIO;
4341 : 0 : }
4342 : :
4343 [ + - + - : 1789 : ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks;
+ - + - ]
4344 : 1789 : return rc;
4345 : 12877 : }
4346 : :
4347 : : int32_t
4348 : 49353326 : spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
4349 : : {
4350 : 1 : int32_t num_completions;
4351 : 1 : int32_t rc;
4352 : 1 : struct spdk_nvme_ctrlr_process *active_proc;
4353 : :
4354 : 49353326 : nvme_ctrlr_lock(ctrlr);
4355 : :
4356 [ + + + - : 49353326 : if (ctrlr->keep_alive_interval_ticks) {
+ + ]
4357 : 4914746 : rc = nvme_ctrlr_keep_alive(ctrlr);
4358 [ + + ]: 4914746 : if (rc) {
4359 : 3 : nvme_ctrlr_unlock(ctrlr);
4360 : 3 : return rc;
4361 : : }
4362 : 12877 : }
4363 : :
4364 : 49353323 : rc = nvme_io_msg_process(ctrlr);
4365 [ + + ]: 49353323 : if (rc < 0) {
4366 : 0 : nvme_ctrlr_unlock(ctrlr);
4367 : 0 : return rc;
4368 : : }
4369 : 49353323 : num_completions = rc;
4370 : :
4371 [ + - + - ]: 49353323 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4372 : :
4373 : : /* Each process has an async list, complete the ones for this process object */
4374 : 49353323 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4375 [ + + ]: 49353323 : if (active_proc) {
4376 : 49353317 : nvme_ctrlr_complete_queued_async_events(ctrlr);
4377 : 12905 : }
4378 : :
4379 [ + + + + : 49353323 : if (rc == -ENXIO && ctrlr->is_disconnecting) {
+ + + - -
+ ]
4380 : 553 : nvme_ctrlr_disconnect_done(ctrlr);
4381 : 1 : }
4382 : :
4383 : 49353323 : nvme_ctrlr_unlock(ctrlr);
4384 : :
4385 [ + + ]: 49353323 : if (rc < 0) {
4386 : 1353 : num_completions = rc;
4387 : 1 : } else {
4388 [ + - ]: 49351970 : num_completions += rc;
4389 : : }
4390 : :
4391 : 49353323 : return num_completions;
4392 : 12906 : }
4393 : :
4394 : : const struct spdk_nvme_ctrlr_data *
4395 : 2478579 : spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
4396 : : {
4397 [ + - ]: 2478579 : return &ctrlr->cdata;
4398 : : }
4399 : :
4400 : 32403 : union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr)
4401 : : {
4402 : 19268 : union spdk_nvme_csts_register csts;
4403 : :
4404 [ - + ]: 32403 : if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
4405 : 0 : csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4406 : 0 : }
4407 : 32403 : return csts;
4408 : : }
4409 : :
4410 : 0 : union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr)
4411 : : {
4412 : 0 : union spdk_nvme_cc_register cc;
4413 : :
4414 [ # # ]: 0 : if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
4415 : 0 : cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4416 : 0 : }
4417 : 0 : return cc;
4418 : : }
4419 : :
4420 : 79 : union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
4421 : : {
4422 [ # # ]: 79 : return ctrlr->cap;
4423 : : }
4424 : :
4425 : 1054 : union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
4426 : : {
4427 [ # # ]: 1054 : return ctrlr->vs;
4428 : : }
4429 : :
4430 : 8 : union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr)
4431 : : {
4432 : 0 : union spdk_nvme_cmbsz_register cmbsz;
4433 : :
4434 [ - + ]: 8 : if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) {
4435 : 0 : cmbsz.raw = 0;
4436 : 0 : }
4437 : :
4438 : 8 : return cmbsz;
4439 : : }
4440 : :
4441 : 8 : union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr)
4442 : : {
4443 : 0 : union spdk_nvme_pmrcap_register pmrcap;
4444 : :
4445 [ - + ]: 8 : if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) {
4446 : 0 : pmrcap.raw = 0;
4447 : 0 : }
4448 : :
4449 : 8 : return pmrcap;
4450 : : }
4451 : :
4452 : 0 : union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr)
4453 : : {
4454 : 0 : union spdk_nvme_bpinfo_register bpinfo;
4455 : :
4456 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
4457 : 0 : bpinfo.raw = 0;
4458 : 0 : }
4459 : :
4460 : 0 : return bpinfo;
4461 : : }
4462 : :
4463 : : uint64_t
4464 : 8 : spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr)
4465 : : {
4466 [ # # # # ]: 8 : return ctrlr->pmr_size;
4467 : : }
4468 : :
4469 : : uint32_t
4470 : 37 : spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
4471 : : {
4472 [ + - + - : 37 : return ctrlr->cdata.nn;
+ - ]
4473 : : }
4474 : :
4475 : : bool
4476 : 55918 : spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4477 : : {
4478 : 46545 : struct spdk_nvme_ns tmp, *ns;
4479 : :
4480 [ + - ]: 55918 : tmp.id = nsid;
4481 [ + - ]: 55918 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4482 : :
4483 [ + + ]: 55918 : if (ns != NULL) {
4484 [ - + - + : 55359 : return ns->active;
- + ]
4485 : : }
4486 : :
4487 : 559 : return false;
4488 : 9301 : }
4489 : :
4490 : : uint32_t
4491 : 8010 : spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr)
4492 : : {
4493 : 35 : struct spdk_nvme_ns *ns;
4494 : :
4495 [ + - ]: 8010 : ns = RB_MIN(nvme_ns_tree, &ctrlr->ns);
4496 [ + + ]: 8010 : if (ns == NULL) {
4497 : 442 : return 0;
4498 : : }
4499 : :
4500 [ + + ]: 35168 : while (ns != NULL) {
4501 [ + + + + : 35145 : if (ns->active) {
+ - + + ]
4502 [ - + - + ]: 7545 : return ns->id;
4503 : : }
4504 : :
4505 : 27600 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4506 : : }
4507 : :
4508 : 23 : return 0;
4509 : 2166 : }
4510 : :
4511 : : uint32_t
4512 : 35985 : spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
4513 : : {
4514 : 25006 : struct spdk_nvme_ns tmp, *ns;
4515 : :
4516 [ + - ]: 35985 : tmp.id = prev_nsid;
4517 [ + - ]: 35985 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4518 [ + + ]: 35985 : if (ns == NULL) {
4519 : 30 : return 0;
4520 : : }
4521 : :
4522 : 35955 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4523 [ + + ]: 45149 : while (ns != NULL) {
4524 [ + + + + : 37700 : if (ns->active) {
+ - + + ]
4525 [ - + - + ]: 28506 : return ns->id;
4526 : : }
4527 : :
4528 : 9194 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4529 : : }
4530 : :
4531 : 7449 : return 0;
4532 : 6780 : }
4533 : :
4534 : : struct spdk_nvme_ns *
4535 : 90678 : spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4536 : : {
4537 : 65424 : struct spdk_nvme_ns tmp;
4538 : 12403 : struct spdk_nvme_ns *ns;
4539 : :
4540 [ + + + + : 90678 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
+ - + - -
+ ]
4541 : 5874 : return NULL;
4542 : : }
4543 : :
4544 : 84804 : nvme_ctrlr_lock(ctrlr);
4545 : :
4546 [ + - ]: 84804 : tmp.id = nsid;
4547 [ + - ]: 84804 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4548 : :
4549 [ + + ]: 84804 : if (ns == NULL) {
4550 : 48616 : ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
4551 [ + + ]: 48616 : if (ns == NULL) {
4552 : 0 : nvme_ctrlr_unlock(ctrlr);
4553 : 0 : return NULL;
4554 : : }
4555 : :
4556 [ + + + + : 48616 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid);
+ + + + #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
4557 [ + - + - ]: 48616 : ns->id = nsid;
4558 [ + - ]: 48616 : RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns);
4559 : 8749 : }
4560 : :
4561 : 84804 : nvme_ctrlr_unlock(ctrlr);
4562 : :
4563 : 84804 : return ns;
4564 : 17718 : }
4565 : :
4566 : : struct spdk_pci_device *
4567 : 145 : spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr)
4568 : : {
4569 [ - + ]: 145 : if (ctrlr == NULL) {
4570 : 0 : return NULL;
4571 : : }
4572 : :
4573 [ - + # # : 145 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
# # # # ]
4574 : 0 : return NULL;
4575 : : }
4576 : :
4577 : 145 : return nvme_ctrlr_proc_get_devhandle(ctrlr);
4578 : 0 : }
4579 : :
4580 : : uint32_t
4581 : 909 : spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr)
4582 : : {
4583 [ + - + - ]: 909 : return ctrlr->max_xfer_size;
4584 : : }
4585 : :
4586 : : void
4587 : 901 : spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
4588 : : spdk_nvme_aer_cb aer_cb_fn,
4589 : : void *aer_cb_arg)
4590 : : {
4591 : 2 : struct spdk_nvme_ctrlr_process *active_proc;
4592 : :
4593 : 901 : nvme_ctrlr_lock(ctrlr);
4594 : :
4595 : 901 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4596 [ + - ]: 901 : if (active_proc) {
4597 [ + - + - ]: 901 : active_proc->aer_cb_fn = aer_cb_fn;
4598 [ + - + - ]: 901 : active_proc->aer_cb_arg = aer_cb_arg;
4599 : 3 : }
4600 : :
4601 : 901 : nvme_ctrlr_unlock(ctrlr);
4602 : 901 : }
4603 : :
4604 : : void
4605 : 0 : spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr)
4606 : : {
4607 [ # # # # : 0 : ctrlr->opts.disable_read_changed_ns_list_log_page = true;
# # ]
4608 : 0 : }
4609 : :
4610 : : void
4611 : 16 : spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr,
4612 : : uint64_t timeout_io_us, uint64_t timeout_admin_us,
4613 : : spdk_nvme_timeout_cb cb_fn, void *cb_arg)
4614 : : {
4615 : 0 : struct spdk_nvme_ctrlr_process *active_proc;
4616 : :
4617 : 16 : nvme_ctrlr_lock(ctrlr);
4618 : :
4619 : 16 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4620 [ + - ]: 16 : if (active_proc) {
4621 [ # # # # : 16 : active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL;
# # ]
4622 [ # # # # : 16 : active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL;
# # ]
4623 [ # # # # ]: 16 : active_proc->timeout_cb_fn = cb_fn;
4624 [ # # # # ]: 16 : active_proc->timeout_cb_arg = cb_arg;
4625 : 0 : }
4626 : :
4627 [ # # # # ]: 16 : ctrlr->timeout_enabled = true;
4628 : :
4629 : 16 : nvme_ctrlr_unlock(ctrlr);
4630 : 16 : }
4631 : :
4632 : : bool
4633 : 365 : spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
4634 : : {
4635 : : /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
4636 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
4637 [ + + + - : 365 : return ctrlr->log_page_supported[log_page];
+ - + - +
- ]
4638 : : }
4639 : :
4640 : : bool
4641 : 24 : spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
4642 : : {
4643 : : /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
4644 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
4645 [ + + + - : 24 : return ctrlr->feature_supported[feature_code];
+ - + - +
- ]
4646 : : }
4647 : :
4648 : : int
4649 : 6 : spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4650 : : struct spdk_nvme_ctrlr_list *payload)
4651 : : {
4652 : 1 : struct nvme_completion_poll_status *status;
4653 : 1 : struct spdk_nvme_ns *ns;
4654 : 1 : int res;
4655 : :
4656 [ + + ]: 6 : if (nsid == 0) {
4657 : 0 : return -EINVAL;
4658 : : }
4659 : :
4660 : 6 : status = calloc(1, sizeof(*status));
4661 [ + + ]: 6 : if (!status) {
4662 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4663 : 0 : return -ENOMEM;
4664 : : }
4665 : :
4666 : 7 : res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
4667 : 1 : nvme_completion_poll_cb, status);
4668 [ - + ]: 6 : if (res) {
4669 : 0 : free(status);
4670 : 0 : return res;
4671 : : }
4672 [ + + + - : 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
+ - - + ]
4673 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4674 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4675 : 0 : free(status);
4676 : 0 : }
4677 : 0 : return -ENXIO;
4678 : : }
4679 : 6 : free(status);
4680 : :
4681 : 6 : res = nvme_ctrlr_identify_active_ns(ctrlr);
4682 [ - + ]: 6 : if (res) {
4683 : 0 : return res;
4684 : : }
4685 : :
4686 : 6 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
4687 [ + + ]: 6 : if (ns == NULL) {
4688 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4689 : 0 : return -ENXIO;
4690 : : }
4691 : :
4692 : 6 : return nvme_ns_construct(ns, nsid, ctrlr);
4693 : 1 : }
4694 : :
4695 : : int
4696 : 6 : spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4697 : : struct spdk_nvme_ctrlr_list *payload)
4698 : : {
4699 : 1 : struct nvme_completion_poll_status *status;
4700 : 1 : int res;
4701 : :
4702 [ + + ]: 6 : if (nsid == 0) {
4703 : 0 : return -EINVAL;
4704 : : }
4705 : :
4706 : 6 : status = calloc(1, sizeof(*status));
4707 [ + + ]: 6 : if (!status) {
4708 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4709 : 0 : return -ENOMEM;
4710 : : }
4711 : :
4712 : 7 : res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
4713 : 1 : nvme_completion_poll_cb, status);
4714 [ - + ]: 6 : if (res) {
4715 : 0 : free(status);
4716 : 0 : return res;
4717 : : }
4718 [ + + + - : 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
+ - - + ]
4719 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4720 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4721 : 0 : free(status);
4722 : 0 : }
4723 : 0 : return -ENXIO;
4724 : : }
4725 : 6 : free(status);
4726 : :
4727 : 6 : return nvme_ctrlr_identify_active_ns(ctrlr);
4728 : 1 : }
4729 : :
4730 : : uint32_t
4731 : 6 : spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
4732 : : {
4733 : 1 : struct nvme_completion_poll_status *status;
4734 : 1 : int res;
4735 : 1 : uint32_t nsid;
4736 : :
4737 : 6 : status = calloc(1, sizeof(*status));
4738 [ + + ]: 6 : if (!status) {
4739 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4740 : 0 : return 0;
4741 : : }
4742 : :
4743 : 6 : res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status);
4744 [ - + ]: 6 : if (res) {
4745 : 0 : free(status);
4746 : 0 : return 0;
4747 : : }
4748 [ + + + - : 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
+ - - + ]
4749 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4750 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4751 : 0 : free(status);
4752 : 0 : }
4753 : 0 : return 0;
4754 : : }
4755 : :
4756 [ + - + - : 6 : nsid = status->cpl.cdw0;
+ - ]
4757 : 6 : free(status);
4758 : :
4759 [ + + # # ]: 6 : assert(nsid > 0);
4760 : :
4761 : : /* Return the namespace ID that was created */
4762 : 6 : return nsid;
4763 : 1 : }
4764 : :
4765 : : int
4766 : 6 : spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4767 : : {
4768 : 1 : struct nvme_completion_poll_status *status;
4769 : 1 : int res;
4770 : :
4771 [ + + ]: 6 : if (nsid == 0) {
4772 : 0 : return -EINVAL;
4773 : : }
4774 : :
4775 : 6 : status = calloc(1, sizeof(*status));
4776 [ + + ]: 6 : if (!status) {
4777 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4778 : 0 : return -ENOMEM;
4779 : : }
4780 : :
4781 : 6 : res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status);
4782 [ - + ]: 6 : if (res) {
4783 : 0 : free(status);
4784 : 0 : return res;
4785 : : }
4786 [ + + + - : 6 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
+ - - + ]
4787 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4788 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4789 : 0 : free(status);
4790 : 0 : }
4791 : 0 : return -ENXIO;
4792 : : }
4793 : 6 : free(status);
4794 : :
4795 : 6 : return nvme_ctrlr_identify_active_ns(ctrlr);
4796 : 1 : }
4797 : :
4798 : : int
4799 : 0 : spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4800 : : struct spdk_nvme_format *format)
4801 : : {
4802 : 0 : struct nvme_completion_poll_status *status;
4803 : 0 : int res;
4804 : :
4805 : 0 : status = calloc(1, sizeof(*status));
4806 [ # # ]: 0 : if (!status) {
4807 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4808 : 0 : return -ENOMEM;
4809 : : }
4810 : :
4811 : 0 : res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
4812 : 0 : status);
4813 [ # # ]: 0 : if (res) {
4814 : 0 : free(status);
4815 : 0 : return res;
4816 : : }
4817 [ # # # # : 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
4818 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4819 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4820 : 0 : free(status);
4821 : 0 : }
4822 : 0 : return -ENXIO;
4823 : : }
4824 : 0 : free(status);
4825 : :
4826 : 0 : return spdk_nvme_ctrlr_reset(ctrlr);
4827 : 0 : }
4828 : :
4829 : : int
4830 : 48 : spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
4831 : : int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status)
4832 : : {
4833 : 40 : struct spdk_nvme_fw_commit fw_commit;
4834 : 8 : struct nvme_completion_poll_status *status;
4835 : 8 : int res;
4836 : 8 : unsigned int size_remaining;
4837 : 8 : unsigned int offset;
4838 : 8 : unsigned int transfer;
4839 : 8 : uint8_t *p;
4840 : :
4841 [ + + ]: 48 : if (!completion_status) {
4842 : 0 : return -EINVAL;
4843 : : }
4844 [ + + ]: 48 : memset(completion_status, 0, sizeof(struct spdk_nvme_status));
4845 [ + + + + ]: 48 : if (size % 4) {
4846 [ + - + + : 6 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
4847 : 6 : return -1;
4848 : : }
4849 : :
4850 : : /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG
4851 : : * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG
4852 : : */
4853 [ - + - - ]: 42 : if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) &&
4854 : 0 : (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) {
4855 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4856 : 0 : return -1;
4857 : : }
4858 : :
4859 : 42 : status = calloc(1, sizeof(*status));
4860 [ + + ]: 42 : if (!status) {
4861 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
4862 : 0 : return -ENOMEM;
4863 : : }
4864 : :
4865 : : /* Firmware download */
4866 : 42 : size_remaining = size;
4867 : 42 : offset = 0;
4868 : 42 : p = payload;
4869 : :
4870 [ + + ]: 60 : while (size_remaining > 0) {
4871 [ + - + - : 42 : transfer = spdk_min(size_remaining, ctrlr->min_page_size);
+ + + - +
- ]
4872 : :
4873 [ + + ]: 42 : memset(status, 0, sizeof(*status));
4874 : 49 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
4875 : : nvme_completion_poll_cb,
4876 : 7 : status);
4877 [ + + ]: 42 : if (res) {
4878 : 12 : free(status);
4879 : 12 : return res;
4880 : : }
4881 : :
4882 [ + + + - : 30 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
+ - + + ]
4883 [ + - + + : 12 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
4884 [ + + + + : 12 : if (!status->timed_out) {
+ - + + ]
4885 : 6 : free(status);
4886 : 1 : }
4887 : 12 : return -ENXIO;
4888 : : }
4889 [ + - ]: 18 : p += transfer;
4890 : 18 : offset += transfer;
4891 : 18 : size_remaining -= transfer;
4892 : : }
4893 : :
4894 : : /* Firmware commit */
4895 [ + + ]: 18 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
4896 : 18 : fw_commit.fs = slot;
4897 : 18 : fw_commit.ca = commit_action;
4898 : :
4899 [ + + ]: 18 : memset(status, 0, sizeof(*status));
4900 : 21 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
4901 : 3 : status);
4902 [ + + ]: 18 : if (res) {
4903 : 6 : free(status);
4904 : 6 : return res;
4905 : : }
4906 : :
4907 [ + - + - : 12 : res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock);
+ - ]
4908 : :
4909 [ + - + - : 12 : memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status));
+ - + - +
- ]
4910 : :
4911 [ + + + - : 12 : if (!status->timed_out) {
+ - - + ]
4912 : 12 : free(status);
4913 : 2 : }
4914 : :
4915 [ + + ]: 12 : if (res) {
4916 [ + + - + : 6 : if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC ||
# # ]
4917 [ # # ]: 0 : completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) {
4918 [ + + - + : 6 : if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
# # ]
4919 [ # # ]: 0 : completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) {
4920 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr,
# # # # #
# # # # #
# # # # #
# # # #
# ]
4921 : : "firmware activation requires conventional reset to be performed. !\n");
4922 : 0 : } else {
4923 [ + - + + : 6 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
+ - + - +
- + - + -
- + # # #
# - + -
+ ]
4924 : : }
4925 : 6 : return -ENXIO;
4926 : : }
4927 : 0 : }
4928 : :
4929 : 6 : return spdk_nvme_ctrlr_reset(ctrlr);
4930 : 8 : }
4931 : :
4932 : : int
4933 : 0 : spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr)
4934 : : {
4935 : 0 : int rc, size;
4936 : 0 : union spdk_nvme_cmbsz_register cmbsz;
4937 : :
4938 : 0 : cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
4939 : :
4940 [ # # # # ]: 0 : if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) {
4941 : 0 : return -ENOTSUP;
4942 : : }
4943 : :
4944 [ # # # # : 0 : size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4));
# # # # ]
4945 : :
4946 : 0 : nvme_ctrlr_lock(ctrlr);
4947 : 0 : rc = nvme_transport_ctrlr_reserve_cmb(ctrlr);
4948 : 0 : nvme_ctrlr_unlock(ctrlr);
4949 : :
4950 [ # # ]: 0 : if (rc < 0) {
4951 : 0 : return rc;
4952 : : }
4953 : :
4954 : 0 : return size;
4955 : 0 : }
4956 : :
4957 : : void *
4958 : 17 : spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
4959 : : {
4960 : 0 : void *buf;
4961 : :
4962 : 17 : nvme_ctrlr_lock(ctrlr);
4963 : 17 : buf = nvme_transport_ctrlr_map_cmb(ctrlr, size);
4964 : 17 : nvme_ctrlr_unlock(ctrlr);
4965 : :
4966 : 17 : return buf;
4967 : 0 : }
4968 : :
4969 : : void
4970 : 2 : spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
4971 : : {
4972 : 2 : nvme_ctrlr_lock(ctrlr);
4973 : 2 : nvme_transport_ctrlr_unmap_cmb(ctrlr);
4974 : 2 : nvme_ctrlr_unlock(ctrlr);
4975 : 2 : }
4976 : :
4977 : : int
4978 : 44 : spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
4979 : : {
4980 : 0 : int rc;
4981 : :
4982 : 44 : nvme_ctrlr_lock(ctrlr);
4983 : 44 : rc = nvme_transport_ctrlr_enable_pmr(ctrlr);
4984 : 44 : nvme_ctrlr_unlock(ctrlr);
4985 : :
4986 : 44 : return rc;
4987 : 0 : }
4988 : :
4989 : : int
4990 : 44 : spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
4991 : : {
4992 : 0 : int rc;
4993 : :
4994 : 44 : nvme_ctrlr_lock(ctrlr);
4995 : 44 : rc = nvme_transport_ctrlr_disable_pmr(ctrlr);
4996 : 44 : nvme_ctrlr_unlock(ctrlr);
4997 : :
4998 : 44 : return rc;
4999 : 0 : }
5000 : :
5001 : : void *
5002 : 44 : spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5003 : : {
5004 : 0 : void *buf;
5005 : :
5006 : 44 : nvme_ctrlr_lock(ctrlr);
5007 : 44 : buf = nvme_transport_ctrlr_map_pmr(ctrlr, size);
5008 : 44 : nvme_ctrlr_unlock(ctrlr);
5009 : :
5010 : 44 : return buf;
5011 : 0 : }
5012 : :
5013 : : int
5014 : 44 : spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
5015 : : {
5016 : 0 : int rc;
5017 : :
5018 : 44 : nvme_ctrlr_lock(ctrlr);
5019 : 44 : rc = nvme_transport_ctrlr_unmap_pmr(ctrlr);
5020 : 44 : nvme_ctrlr_unlock(ctrlr);
5021 : :
5022 : 44 : return rc;
5023 : 0 : }
5024 : :
5025 : : int
5026 : 0 : spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload,
5027 : : uint32_t bprsz, uint32_t bprof, uint32_t bpid)
5028 : : {
5029 : 0 : union spdk_nvme_bprsel_register bprsel;
5030 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5031 : 0 : uint64_t bpmbl, bpmb_size;
5032 : :
5033 [ # # # # : 0 : if (ctrlr->cap.bits.bps == 0) {
# # # # ]
5034 : 0 : return -ENOTSUP;
5035 : : }
5036 : :
5037 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5038 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5039 : 0 : return -EIO;
5040 : : }
5041 : :
5042 [ # # ]: 0 : if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) {
5043 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5044 : 0 : return -EALREADY;
5045 : : }
5046 : :
5047 : 0 : nvme_ctrlr_lock(ctrlr);
5048 : :
5049 : 0 : bpmb_size = bprsz * 4096;
5050 : 0 : bpmbl = spdk_vtophys(payload, &bpmb_size);
5051 [ # # ]: 0 : if (bpmbl == SPDK_VTOPHYS_ERROR) {
5052 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5053 : 0 : nvme_ctrlr_unlock(ctrlr);
5054 : 0 : return -EFAULT;
5055 : : }
5056 : :
5057 [ # # ]: 0 : if (bpmb_size != bprsz * 4096) {
5058 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5059 : 0 : nvme_ctrlr_unlock(ctrlr);
5060 : 0 : return -EFAULT;
5061 : : }
5062 : :
5063 [ # # ]: 0 : if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) {
5064 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5065 : 0 : nvme_ctrlr_unlock(ctrlr);
5066 : 0 : return -EIO;
5067 : : }
5068 : :
5069 : 0 : bprsel.bits.bpid = bpid;
5070 : 0 : bprsel.bits.bprof = bprof;
5071 : 0 : bprsel.bits.bprsz = bprsz;
5072 : :
5073 [ # # ]: 0 : if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) {
5074 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5075 : 0 : nvme_ctrlr_unlock(ctrlr);
5076 : 0 : return -EIO;
5077 : : }
5078 : :
5079 : 0 : nvme_ctrlr_unlock(ctrlr);
5080 : 0 : return 0;
5081 : 0 : }
5082 : :
5083 : : int
5084 : 0 : spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr)
5085 : : {
5086 : 0 : int rc = 0;
5087 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5088 : :
5089 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5090 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5091 : 0 : return -EIO;
5092 : : }
5093 : :
5094 [ # # # # : 0 : switch (bpinfo.bits.brs) {
# ]
5095 : 0 : case SPDK_NVME_BRS_NO_READ:
5096 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5097 : 0 : rc = -EINVAL;
5098 : 0 : break;
5099 : 0 : case SPDK_NVME_BRS_READ_IN_PROGRESS:
5100 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
5101 : 0 : rc = -EAGAIN;
5102 : 0 : break;
5103 : 0 : case SPDK_NVME_BRS_READ_ERROR:
5104 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5105 : 0 : rc = -EIO;
5106 : 0 : break;
5107 : 0 : case SPDK_NVME_BRS_READ_SUCCESS:
5108 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
5109 : 0 : break;
5110 : 0 : default:
5111 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5112 : 0 : rc = -EINVAL;
5113 : 0 : }
5114 : :
5115 : 0 : return rc;
5116 : 0 : }
5117 : :
5118 : : static void
5119 : 0 : nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl)
5120 : : {
5121 : 0 : int res;
5122 : 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
5123 : 0 : struct spdk_nvme_fw_commit fw_commit;
5124 : 0 : struct spdk_nvme_cpl err_cpl =
5125 : : {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }};
5126 : :
5127 [ # # # # : 0 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
5128 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5129 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
# # # # #
# # # ]
5130 : 0 : return;
5131 : : }
5132 : :
5133 [ # # # # : 0 : if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) {
# # ]
5134 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
5135 [ # # # # : 0 : ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size;
# # # # #
# # # #
# ]
5136 [ # # # # : 0 : ctrlr->fw_offset += ctrlr->fw_transfer_size;
# # # # ]
5137 [ # # # # : 0 : ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size;
# # # # ]
5138 [ # # # # : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
# # # # #
# # # # #
# # # # #
# # # ]
5139 [ # # # # : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
# # # # ]
5140 [ # # # # ]: 0 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5141 [ # # ]: 0 : if (res) {
5142 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5143 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5144 : 0 : return;
5145 : : }
5146 : :
5147 [ # # # # : 0 : if (ctrlr->fw_transfer_size < ctrlr->min_page_size) {
# # # # #
# ]
5148 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED;
5149 : 0 : }
5150 [ # # # # : 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) {
# # ]
5151 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
5152 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5153 [ # # # # ]: 0 : fw_commit.bpid = ctrlr->bpid;
5154 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION;
5155 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5156 : 0 : nvme_write_boot_partition_cb, ctrlr);
5157 [ # # ]: 0 : if (res) {
5158 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5159 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
# # # # #
# # # # #
# # # # #
# # # #
# ]
5160 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5161 : 0 : return;
5162 : : }
5163 : :
5164 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE;
5165 [ # # # # : 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) {
# # ]
5166 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
5167 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5168 [ # # # # ]: 0 : fw_commit.bpid = ctrlr->bpid;
5169 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION;
5170 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5171 : 0 : nvme_write_boot_partition_cb, ctrlr);
5172 [ # # ]: 0 : if (res) {
5173 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5174 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
# # # # #
# # # # #
# # # # #
# # # #
# ]
5175 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5176 : 0 : return;
5177 : : }
5178 : :
5179 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE;
5180 [ # # # # : 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) {
# # ]
5181 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
5182 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
# # # # #
# # # ]
5183 : 0 : } else {
5184 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5185 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5186 : 0 : return;
5187 : : }
5188 [ # # ]: 0 : }
5189 : :
5190 : : int
5191 : 0 : spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr,
5192 : : void *payload, uint32_t size, uint32_t bpid,
5193 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
5194 : : {
5195 : 0 : int res;
5196 : :
5197 [ # # # # : 0 : if (ctrlr->cap.bits.bps == 0) {
# # # # ]
5198 : 0 : return -ENOTSUP;
5199 : : }
5200 : :
5201 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING;
5202 [ # # # # ]: 0 : ctrlr->bpid = bpid;
5203 [ # # # # ]: 0 : ctrlr->bp_write_cb_fn = cb_fn;
5204 [ # # # # ]: 0 : ctrlr->bp_write_cb_arg = cb_arg;
5205 [ # # # # ]: 0 : ctrlr->fw_offset = 0;
5206 [ # # # # ]: 0 : ctrlr->fw_size_remaining = size;
5207 [ # # # # ]: 0 : ctrlr->fw_payload = payload;
5208 [ # # # # : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
# # # # #
# # # # #
# # # # #
# # # ]
5209 : :
5210 [ # # # # : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
# # # # ]
5211 [ # # # # ]: 0 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5212 : :
5213 : 0 : return res;
5214 : 0 : }
5215 : :
5216 : : bool
5217 : 8296 : spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr)
5218 : : {
5219 [ + + # # ]: 8296 : assert(ctrlr);
5220 : :
5221 [ + + + - : 8296 : return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN,
+ - + - ]
5222 : : strlen(SPDK_NVMF_DISCOVERY_NQN));
5223 : : }
5224 : :
5225 : : bool
5226 : 3855 : spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr)
5227 : : {
5228 [ + + # # ]: 3855 : assert(ctrlr);
5229 : :
5230 [ + - + - : 3855 : return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype);
+ - ]
5231 : : }
5232 : :
5233 : : int
5234 : 64 : spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5235 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5236 : : {
5237 : 0 : struct nvme_completion_poll_status *status;
5238 : 0 : int res;
5239 : :
5240 : 64 : status = calloc(1, sizeof(*status));
5241 [ - + ]: 64 : if (!status) {
5242 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5243 : 0 : return -ENOMEM;
5244 : : }
5245 : :
5246 : 64 : res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size,
5247 : 0 : nvme_completion_poll_cb, status);
5248 [ - + ]: 64 : if (res) {
5249 : 0 : free(status);
5250 : 0 : return res;
5251 : : }
5252 [ - + # # : 64 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
5253 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5254 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
5255 : 0 : free(status);
5256 : 0 : }
5257 : 0 : return -ENXIO;
5258 : : }
5259 : 64 : free(status);
5260 : :
5261 : 64 : return 0;
5262 : 0 : }
5263 : :
5264 : : int
5265 : 0 : spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5266 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5267 : : {
5268 : 0 : struct nvme_completion_poll_status *status;
5269 : 0 : int res;
5270 : :
5271 : 0 : status = calloc(1, sizeof(*status));
5272 [ # # ]: 0 : if (!status) {
5273 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5274 : 0 : return -ENOMEM;
5275 : : }
5276 : :
5277 : 0 : res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size,
5278 : : nvme_completion_poll_cb,
5279 : 0 : status);
5280 [ # # ]: 0 : if (res) {
5281 : 0 : free(status);
5282 : 0 : return res;
5283 : : }
5284 [ # # # # : 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
5285 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n");
# # # # #
# # # # #
# # # # #
# # # #
# ]
5286 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
5287 : 0 : free(status);
5288 : 0 : }
5289 : 0 : return -ENXIO;
5290 : : }
5291 : :
5292 : 0 : free(status);
5293 : :
5294 : 0 : return 0;
5295 : 0 : }
5296 : :
5297 : : uint64_t
5298 : 5142 : spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr)
5299 : : {
5300 [ + - + - ]: 5142 : return ctrlr->flags;
5301 : : }
5302 : :
5303 : : const struct spdk_nvme_transport_id *
5304 : 1631 : spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr)
5305 : : {
5306 [ # # ]: 1631 : return &ctrlr->trid;
5307 : : }
5308 : :
5309 : : int32_t
5310 : 5474 : spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr)
5311 : : {
5312 : 17 : uint32_t qid;
5313 : :
5314 [ + + + - : 5474 : assert(ctrlr->free_io_qids);
+ - # # ]
5315 : 5474 : nvme_ctrlr_lock(ctrlr);
5316 [ + - + - ]: 5474 : qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
5317 [ + + + - : 5474 : if (qid > ctrlr->opts.num_io_queues) {
+ - + + ]
5318 [ + - + + : 13 : NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n");
+ - + - +
- + - + -
- + # # #
# + - +
- ]
5319 : 13 : nvme_ctrlr_unlock(ctrlr);
5320 : 13 : return -1;
5321 : : }
5322 : :
5323 [ + - + - ]: 5461 : spdk_bit_array_clear(ctrlr->free_io_qids, qid);
5324 : 5461 : nvme_ctrlr_unlock(ctrlr);
5325 : 5461 : return qid;
5326 : 1079 : }
5327 : :
5328 : : void
5329 : 302413 : spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid)
5330 : : {
5331 [ + + + - : 302413 : assert(qid <= ctrlr->opts.num_io_queues);
+ - + - #
# ]
5332 : :
5333 : 302413 : nvme_ctrlr_lock(ctrlr);
5334 : :
5335 [ + + + - : 302413 : if (spdk_likely(ctrlr->free_io_qids)) {
- + ]
5336 [ + - + - ]: 302377 : spdk_bit_array_set(ctrlr->free_io_qids, qid);
5337 : 136002 : }
5338 : :
5339 : 302413 : nvme_ctrlr_unlock(ctrlr);
5340 : 302413 : }
5341 : :
5342 : : int
5343 : 8073 : spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
5344 : : struct spdk_memory_domain **domains, int array_size)
5345 : : {
5346 : 8073 : return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size);
5347 : : }
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