Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (C) 2015 Intel Corporation. All rights reserved.
3 : : * Copyright (c) 2020, 2021 Mellanox Technologies LTD. All rights reserved.
4 : : * Copyright (c) 2021, 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 : : */
6 : :
7 : : #include "spdk/stdinc.h"
8 : :
9 : : #include "spdk_internal/cunit.h"
10 : :
11 : : #include "spdk/log.h"
12 : :
13 : : #include "common/lib/test_env.c"
14 : :
15 : : #include "nvme/nvme_ctrlr.c"
16 : : #include "nvme/nvme_quirks.c"
17 : :
18 : 3 : SPDK_LOG_REGISTER_COMPONENT(nvme)
19 : :
20 : : pid_t g_spdk_nvme_pid;
21 : :
22 : : struct nvme_driver _g_nvme_driver = {
23 : : .lock = PTHREAD_MUTEX_INITIALIZER,
24 : : };
25 : :
26 : : struct nvme_driver *g_spdk_nvme_driver = &_g_nvme_driver;
27 : :
28 : : struct spdk_nvme_registers g_ut_nvme_regs = {};
29 : : typedef void (*set_reg_cb)(void);
30 : : set_reg_cb g_set_reg_cb;
31 : :
32 : : __thread int nvme_thread_ioq_index = -1;
33 : :
34 : : uint32_t set_size = 1;
35 : :
36 : : int set_status_cpl = -1;
37 : :
38 : : #define UT_HOSTID "e53e9258-c93b-48b5-be1a-f025af6d232a"
39 : :
40 [ # # ]: 0 : DEFINE_STUB(nvme_ctrlr_cmd_set_host_id, int,
41 : : (struct spdk_nvme_ctrlr *ctrlr, void *host_id, uint32_t host_id_size,
42 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0);
43 : 63 : DEFINE_STUB_V(nvme_ns_set_identify_data, (struct spdk_nvme_ns *ns));
44 : 18 : DEFINE_STUB_V(nvme_ns_set_id_desc_list_data, (struct spdk_nvme_ns *ns));
45 : 12 : DEFINE_STUB_V(nvme_ns_free_iocs_specific_data, (struct spdk_nvme_ns *ns));
46 : 42 : DEFINE_STUB_V(nvme_qpair_abort_all_queued_reqs, (struct spdk_nvme_qpair *qpair));
47 [ # # ]: 0 : DEFINE_STUB(spdk_nvme_poll_group_remove, int, (struct spdk_nvme_poll_group *group,
48 : : struct spdk_nvme_qpair *qpair), 0);
49 : 15 : DEFINE_STUB_V(nvme_io_msg_ctrlr_update, (struct spdk_nvme_ctrlr *ctrlr));
50 [ - + ]: 3 : DEFINE_STUB(nvme_io_msg_process, int, (struct spdk_nvme_ctrlr *ctrlr), 0);
51 [ # # ]: 0 : DEFINE_STUB(nvme_transport_ctrlr_reserve_cmb, int, (struct spdk_nvme_ctrlr *ctrlr), 0);
52 [ # # ]: 0 : DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_receive, int, (struct spdk_nvme_ctrlr *ctrlr,
53 : : uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload,
54 : : uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0);
55 [ # # ]: 0 : DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_send, int, (struct spdk_nvme_ctrlr *ctrlr,
56 : : uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload,
57 : : uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0);
58 : 63 : DEFINE_STUB_V(nvme_qpair_abort_queued_reqs, (struct spdk_nvme_qpair *qpair));
59 [ # # ]: 0 : DEFINE_STUB(spdk_nvme_qpair_authenticate, int, (struct spdk_nvme_qpair *qpair,
60 : : spdk_nvme_authenticate_cb cb_fn, void *cb_ctx), 0);
61 [ # # ]: 0 : DEFINE_STUB(nvme_transport_ctrlr_enable_interrupts, int, (struct spdk_nvme_ctrlr *ctrlr), 0);
62 : :
63 : : int
64 : 3 : nvme_get_default_hostnqn(char *buf, int len)
65 : : {
66 : 3 : const char *nqn = "nqn.2014-08.org.nvmexpress:uuid:" UT_HOSTID;
67 : :
68 [ - + - + ]: 3 : SPDK_CU_ASSERT_FATAL(len >= (int)strlen(nqn));
69 [ - + - + : 3 : memcpy(buf, nqn, strlen(nqn));
- + ]
70 : :
71 : 3 : return 0;
72 : : }
73 : :
74 [ # # ]: 0 : DEFINE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains, int);
75 : : int
76 : 6 : nvme_transport_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
77 : : struct spdk_memory_domain **domains, int array_size)
78 : : {
79 [ - + + + : 6 : HANDLE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains);
+ - ]
80 : :
81 : 0 : return 0;
82 : : }
83 : :
84 [ # # ]: 0 : DEFINE_RETURN_MOCK(nvme_transport_ctrlr_ready, int);
85 : : int
86 : 51 : nvme_transport_ctrlr_ready(struct spdk_nvme_ctrlr *ctrlr)
87 : : {
88 [ - + + + : 51 : HANDLE_RETURN_MOCK(nvme_transport_ctrlr_ready);
+ + ]
89 : 48 : return 0;
90 : : }
91 : :
92 : 0 : struct spdk_nvme_ctrlr *nvme_transport_ctrlr_construct(const struct spdk_nvme_transport_id *trid,
93 : : const struct spdk_nvme_ctrlr_opts *opts,
94 : : void *devhandle)
95 : : {
96 : 0 : return NULL;
97 : : }
98 : :
99 : : int
100 : 141 : nvme_transport_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
101 : : {
102 : 141 : nvme_ctrlr_destruct_finish(ctrlr);
103 : :
104 : 141 : return 0;
105 : : }
106 : :
107 : : int
108 : 63 : nvme_transport_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
109 : : {
110 : 63 : return 0;
111 : : }
112 : :
113 : : int
114 : 165 : nvme_transport_ctrlr_set_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value)
115 : : {
116 [ - + ]: 165 : SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4);
117 : 165 : *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value;
118 [ + + ]: 165 : if (g_set_reg_cb) {
119 : 3 : g_set_reg_cb();
120 : : }
121 : 165 : return 0;
122 : : }
123 : :
124 : : int
125 : 0 : nvme_transport_ctrlr_set_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value)
126 : : {
127 [ # # ]: 0 : SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8);
128 : 0 : *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value;
129 [ # # ]: 0 : if (g_set_reg_cb) {
130 : 0 : g_set_reg_cb();
131 : : }
132 : 0 : return 0;
133 : : }
134 : :
135 : : int
136 : 471 : nvme_transport_ctrlr_get_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value)
137 : : {
138 [ - + ]: 471 : SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4);
139 : 471 : *value = *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset);
140 : 471 : return 0;
141 : : }
142 : :
143 : : int
144 : 63 : nvme_transport_ctrlr_get_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value)
145 : : {
146 [ - + ]: 63 : SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8);
147 : 63 : *value = *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset);
148 : 63 : return 0;
149 : : }
150 : :
151 : : int
152 : 165 : nvme_transport_ctrlr_set_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
153 : : uint32_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg)
154 : : {
155 : 165 : struct spdk_nvme_cpl cpl = {};
156 : :
157 : 165 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
158 : 165 : cpl.status.sc = SPDK_NVME_SC_SUCCESS;
159 : :
160 : 165 : nvme_transport_ctrlr_set_reg_4(ctrlr, offset, value);
161 : 165 : cb_fn(cb_arg, value, &cpl);
162 : 165 : return 0;
163 : : }
164 : :
165 : : int
166 : 0 : nvme_transport_ctrlr_set_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
167 : : uint64_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg)
168 : : {
169 : 0 : struct spdk_nvme_cpl cpl = {};
170 : :
171 : 0 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
172 : 0 : cpl.status.sc = SPDK_NVME_SC_SUCCESS;
173 : :
174 : 0 : nvme_transport_ctrlr_set_reg_8(ctrlr, offset, value);
175 : 0 : cb_fn(cb_arg, value, &cpl);
176 : 0 : return 0;
177 : : }
178 : :
179 : : int
180 : 468 : nvme_transport_ctrlr_get_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
181 : : spdk_nvme_reg_cb cb_fn, void *cb_arg)
182 : : {
183 : 468 : struct spdk_nvme_cpl cpl = {};
184 : 468 : uint32_t value;
185 : :
186 : 468 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
187 : 468 : cpl.status.sc = SPDK_NVME_SC_SUCCESS;
188 : :
189 : 468 : nvme_transport_ctrlr_get_reg_4(ctrlr, offset, &value);
190 : 468 : cb_fn(cb_arg, value, &cpl);
191 : 468 : return 0;
192 : : }
193 : :
194 : : int
195 : 63 : nvme_transport_ctrlr_get_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
196 : : spdk_nvme_reg_cb cb_fn, void *cb_arg)
197 : : {
198 : 63 : struct spdk_nvme_cpl cpl = {};
199 : 63 : uint64_t value;
200 : :
201 : 63 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
202 : 63 : cpl.status.sc = SPDK_NVME_SC_SUCCESS;
203 : :
204 : 63 : nvme_transport_ctrlr_get_reg_8(ctrlr, offset, &value);
205 : 63 : cb_fn(cb_arg, value, &cpl);
206 : 63 : return 0;
207 : : }
208 : :
209 : : uint32_t
210 : 48 : nvme_transport_ctrlr_get_max_xfer_size(struct spdk_nvme_ctrlr *ctrlr)
211 : : {
212 : 48 : return UINT32_MAX;
213 : : }
214 : :
215 : : uint16_t
216 : 0 : nvme_transport_ctrlr_get_max_sges(struct spdk_nvme_ctrlr *ctrlr)
217 : : {
218 : 0 : return 1;
219 : : }
220 : :
221 : : void *
222 : 0 : nvme_transport_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
223 : : {
224 : 0 : return NULL;
225 : : }
226 : :
227 : : int
228 : 0 : nvme_transport_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
229 : : {
230 : 0 : return 0;
231 : : }
232 : :
233 : : int
234 : 0 : nvme_transport_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
235 : : {
236 : 0 : return 0;
237 : : }
238 : :
239 : : int
240 : 0 : nvme_transport_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
241 : : {
242 : 0 : return 0;
243 : : }
244 : :
245 : : void *
246 : 0 : nvme_transport_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
247 : : {
248 : 0 : return NULL;
249 : : }
250 : :
251 : : int
252 : 0 : nvme_transport_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
253 : : {
254 : 0 : return 0;
255 : : }
256 : :
257 : : struct spdk_nvme_qpair *
258 : 45 : nvme_transport_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid,
259 : : const struct spdk_nvme_io_qpair_opts *opts)
260 : : {
261 : : struct spdk_nvme_qpair *qpair;
262 : :
263 : 45 : qpair = calloc(1, sizeof(*qpair));
264 [ - + ]: 45 : SPDK_CU_ASSERT_FATAL(qpair != NULL);
265 : :
266 : 45 : qpair->ctrlr = ctrlr;
267 : 45 : qpair->id = qid;
268 : 45 : qpair->qprio = opts->qprio;
269 : :
270 : 45 : return qpair;
271 : : }
272 : :
273 : : void
274 : 45 : nvme_transport_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
275 : : {
276 : 45 : free(qpair);
277 : 45 : }
278 : :
279 : : void
280 : 189 : nvme_transport_ctrlr_disconnect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
281 : : {
282 : 189 : }
283 : :
284 : : int
285 : 27 : nvme_transport_qpair_reset(struct spdk_nvme_qpair *qpair)
286 : : {
287 : 27 : return 0;
288 : : }
289 : :
290 : : void
291 : 144 : nvme_transport_admin_qpair_abort_aers(struct spdk_nvme_qpair *qpair)
292 : : {
293 : 144 : }
294 : :
295 : : void
296 : 0 : nvme_transport_qpair_abort_reqs(struct spdk_nvme_qpair *qpair)
297 : : {
298 : 0 : }
299 : :
300 : : int
301 : 6 : nvme_driver_init(void)
302 : : {
303 : 6 : return 0;
304 : : }
305 : :
306 : : int
307 : 0 : nvme_qpair_init(struct spdk_nvme_qpair *qpair, uint16_t id,
308 : : struct spdk_nvme_ctrlr *ctrlr,
309 : : enum spdk_nvme_qprio qprio,
310 : : uint32_t num_requests, bool async)
311 : : {
312 : 0 : qpair->id = id;
313 : 0 : qpair->qprio = qprio;
314 : 0 : qpair->ctrlr = ctrlr;
315 : 0 : qpair->async = async;
316 : :
317 : 0 : return 0;
318 : : }
319 : :
320 : : static struct spdk_nvme_cpl fake_cpl = {};
321 : : static enum spdk_nvme_generic_command_status_code set_status_code = SPDK_NVME_SC_SUCCESS;
322 : :
323 : : static void
324 : 381 : fake_cpl_sc(spdk_nvme_cmd_cb cb_fn, void *cb_arg)
325 : : {
326 : 381 : fake_cpl.status.sc = set_status_code;
327 : 381 : cb_fn(cb_arg, &fake_cpl);
328 : 381 : }
329 : :
330 : : static uint32_t g_ut_cdw11;
331 : :
332 : : int
333 : 6 : spdk_nvme_ctrlr_cmd_set_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature,
334 : : uint32_t cdw11, uint32_t cdw12, void *payload, uint32_t payload_size,
335 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
336 : : {
337 : 6 : g_ut_cdw11 = cdw11;
338 : 6 : fake_cpl_sc(cb_fn, cb_arg);
339 : 6 : return 0;
340 : : }
341 : :
342 : : int
343 : 9 : spdk_nvme_ctrlr_cmd_get_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature,
344 : : uint32_t cdw11, void *payload, uint32_t payload_size,
345 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
346 : : {
347 : 9 : fake_cpl_sc(cb_fn, cb_arg);
348 : 9 : return 0;
349 : : }
350 : :
351 : : struct spdk_nvme_ana_page *g_ana_hdr;
352 : : struct spdk_nvme_ana_group_descriptor **g_ana_descs;
353 : :
354 : : int
355 : 27 : spdk_nvme_ctrlr_cmd_get_log_page(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page,
356 : : uint32_t nsid, void *payload, uint32_t payload_size,
357 : : uint64_t offset, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
358 : : {
359 [ + + + + ]: 33 : if ((log_page == SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS) && g_ana_hdr) {
360 : : uint32_t i;
361 : 6 : uint8_t *ptr = payload;
362 : :
363 [ - + ]: 6 : memset(payload, 0, payload_size);
364 : 6 : memcpy(ptr, g_ana_hdr, sizeof(*g_ana_hdr));
365 : 6 : ptr += sizeof(*g_ana_hdr);
366 [ + + ]: 12 : for (i = 0; i < g_ana_hdr->num_ana_group_desc; ++i) {
367 : 6 : uint32_t desc_size = sizeof(**g_ana_descs) +
368 : 6 : g_ana_descs[i]->num_of_nsid * sizeof(uint32_t);
369 [ - + - + ]: 6 : memcpy(ptr, g_ana_descs[i], desc_size);
370 : 6 : ptr += desc_size;
371 : : }
372 [ + + ]: 21 : } else if (log_page == SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY) {
373 : 3 : struct spdk_nvme_intel_log_page_directory *log_page_directory = payload;
374 : 3 : log_page_directory->read_latency_log_len = true;
375 : 3 : log_page_directory->write_latency_log_len = true;
376 : 3 : log_page_directory->temperature_statistics_log_len = true;
377 : 3 : log_page_directory->smart_log_len = true;
378 : 3 : log_page_directory->marketing_description_log_len = true;
379 : : }
380 : :
381 : 27 : fake_cpl_sc(cb_fn, cb_arg);
382 : 27 : return 0;
383 : : }
384 : :
385 : : int
386 : 0 : spdk_nvme_ctrlr_cmd_get_log_page_ext(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page,
387 : : uint32_t nsid, void *payload, uint32_t payload_size,
388 : : uint64_t offset, uint32_t cdw10, uint32_t cdw11,
389 : : uint32_t cdw14, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
390 : : {
391 : 0 : fake_cpl_sc(cb_fn, cb_arg);
392 : 0 : return 0;
393 : : }
394 : :
395 : : int
396 : 72 : nvme_qpair_submit_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req)
397 : : {
398 : 72 : CU_ASSERT(req->cmd.opc == SPDK_NVME_OPC_ASYNC_EVENT_REQUEST);
399 [ + + ]: 72 : STAILQ_INSERT_HEAD(&qpair->free_req, req, stailq);
400 : :
401 : : /*
402 : : * For the purposes of this unit test, we don't need to bother emulating request submission.
403 : : */
404 : :
405 : 72 : return 0;
406 : : }
407 : :
408 : : static int32_t g_wait_for_completion_return_val;
409 : :
410 : : int32_t
411 : 267 : spdk_nvme_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_completions)
412 : : {
413 : 267 : return g_wait_for_completion_return_val;
414 : : }
415 : :
416 : : void
417 : 0 : nvme_qpair_complete_error_reqs(struct spdk_nvme_qpair *qpair)
418 : : {
419 : 0 : }
420 : :
421 : :
422 : : void
423 : 30 : nvme_completion_poll_cb(void *arg, const struct spdk_nvme_cpl *cpl)
424 : : {
425 : 30 : struct nvme_completion_poll_status *status = arg;
426 : : /* This should not happen it test env since this callback is always called
427 : : * before wait_for_completion_* while this field can only be set to true in
428 : : * wait_for_completion_* functions */
429 [ - + ]: 30 : CU_ASSERT(status->timed_out == false);
430 : :
431 : 30 : status->cpl = *cpl;
432 : 30 : status->done = true;
433 : 30 : }
434 : :
435 : : static struct nvme_completion_poll_status *g_failed_status;
436 : :
437 : : int
438 : 60 : nvme_wait_for_completion_robust_lock_timeout(
439 : : struct spdk_nvme_qpair *qpair,
440 : : struct nvme_completion_poll_status *status,
441 : : pthread_mutex_t *robust_mutex,
442 : : uint64_t timeout_in_usecs)
443 : : {
444 [ + + ]: 60 : if (spdk_nvme_qpair_process_completions(qpair, 0) < 0) {
445 : 3 : g_failed_status = status;
446 : 3 : status->timed_out = true;
447 : 3 : return -1;
448 : : }
449 : :
450 : 57 : status->done = true;
451 [ + + ]: 57 : if (set_status_cpl == 1) {
452 : 6 : status->cpl.status.sc = 1;
453 : : }
454 [ + + - + ]: 57 : return spdk_nvme_cpl_is_error(&status->cpl) ? -EIO : 0;
455 : : }
456 : :
457 : : int
458 : 33 : nvme_wait_for_completion_robust_lock(
459 : : struct spdk_nvme_qpair *qpair,
460 : : struct nvme_completion_poll_status *status,
461 : : pthread_mutex_t *robust_mutex)
462 : : {
463 : 33 : return nvme_wait_for_completion_robust_lock_timeout(qpair, status, robust_mutex, 0);
464 : : }
465 : :
466 : : int
467 : 0 : nvme_wait_for_completion(struct spdk_nvme_qpair *qpair,
468 : : struct nvme_completion_poll_status *status)
469 : : {
470 : 0 : return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, 0);
471 : : }
472 : :
473 : : int
474 : 15 : nvme_wait_for_completion_timeout(struct spdk_nvme_qpair *qpair,
475 : : struct nvme_completion_poll_status *status,
476 : : uint64_t timeout_in_usecs)
477 : : {
478 : 15 : return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, timeout_in_usecs);
479 : : }
480 : :
481 : : int
482 : 57 : nvme_ctrlr_cmd_set_async_event_config(struct spdk_nvme_ctrlr *ctrlr,
483 : : union spdk_nvme_feat_async_event_configuration config, spdk_nvme_cmd_cb cb_fn,
484 : : void *cb_arg)
485 : : {
486 : 57 : fake_cpl_sc(cb_fn, cb_arg);
487 : 57 : return 0;
488 : : }
489 : :
490 : : static uint32_t *g_active_ns_list = NULL;
491 : : static uint32_t g_active_ns_list_length = 0;
492 : : static struct spdk_nvme_ctrlr_data *g_cdata = NULL;
493 : : static bool g_fail_next_identify = false;
494 : :
495 : : int
496 : 225 : nvme_ctrlr_cmd_identify(struct spdk_nvme_ctrlr *ctrlr, uint8_t cns, uint16_t cntid, uint32_t nsid,
497 : : uint8_t csi, void *payload, size_t payload_size,
498 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
499 : : {
500 [ + + + + ]: 225 : if (g_fail_next_identify) {
501 : 3 : g_fail_next_identify = false;
502 : 3 : return 1;
503 : : }
504 : :
505 [ - + ]: 222 : memset(payload, 0, payload_size);
506 [ + + ]: 222 : if (cns == SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST) {
507 : 90 : uint32_t count = 0;
508 : 90 : uint32_t i = 0;
509 : 90 : struct spdk_nvme_ns_list *ns_list = (struct spdk_nvme_ns_list *)payload;
510 : :
511 [ + + ]: 90 : if (g_active_ns_list == NULL) {
512 [ + + ]: 9 : for (i = 1; i <= ctrlr->cdata.nn; i++) {
513 [ - + ]: 6 : if (i <= nsid) {
514 : 0 : continue;
515 : : }
516 : :
517 : 6 : ns_list->ns_list[count++] = i;
518 [ - + ]: 6 : if (count == SPDK_COUNTOF(ns_list->ns_list)) {
519 : 0 : break;
520 : : }
521 : : }
522 : : } else {
523 [ + + ]: 43179 : for (i = 0; i < g_active_ns_list_length; i++) {
524 : 43107 : uint32_t cur_nsid = g_active_ns_list[i];
525 [ + + ]: 43107 : if (cur_nsid <= nsid) {
526 : 18435 : continue;
527 : : }
528 : :
529 : 24672 : ns_list->ns_list[count++] = cur_nsid;
530 [ + + ]: 24672 : if (count == SPDK_COUNTOF(ns_list->ns_list)) {
531 : 15 : break;
532 : : }
533 : : }
534 : : }
535 [ + + ]: 132 : } else if (cns == SPDK_NVME_IDENTIFY_CTRLR) {
536 [ + + ]: 48 : if (g_cdata) {
537 [ - + - + ]: 21 : memcpy(payload, g_cdata, sizeof(*g_cdata));
538 : : }
539 [ + + ]: 84 : } else if (cns == SPDK_NVME_IDENTIFY_NS_IOCS) {
540 : 3 : return 0;
541 : : }
542 : :
543 : 219 : fake_cpl_sc(cb_fn, cb_arg);
544 : 219 : return 0;
545 : : }
546 : :
547 : : int
548 : 57 : nvme_ctrlr_cmd_set_num_queues(struct spdk_nvme_ctrlr *ctrlr,
549 : : uint32_t num_queues, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
550 : : {
551 : 57 : fake_cpl_sc(cb_fn, cb_arg);
552 : 57 : return 0;
553 : : }
554 : :
555 : : int
556 : 0 : nvme_ctrlr_cmd_get_num_queues(struct spdk_nvme_ctrlr *ctrlr,
557 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
558 : : {
559 : 0 : CU_ASSERT(0);
560 : 0 : return -1;
561 : : }
562 : :
563 : : int
564 : 3 : nvme_ctrlr_cmd_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
565 : : struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
566 : : {
567 : 3 : return 0;
568 : : }
569 : :
570 : : int
571 : 3 : nvme_ctrlr_cmd_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
572 : : struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
573 : : {
574 : 3 : return 0;
575 : : }
576 : :
577 : : int
578 : 3 : nvme_ctrlr_cmd_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload,
579 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
580 : : {
581 : 3 : fake_cpl_sc(cb_fn, cb_arg);
582 : 3 : return 0;
583 : : }
584 : :
585 : : int
586 : 3 : nvme_ctrlr_cmd_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, spdk_nvme_cmd_cb cb_fn,
587 : : void *cb_arg)
588 : : {
589 : 3 : return 0;
590 : : }
591 : :
592 : : int
593 : 0 : nvme_ctrlr_cmd_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, struct spdk_nvme_format *format,
594 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
595 : : {
596 : 0 : return 0;
597 : : }
598 : :
599 : : int
600 : 0 : spdk_nvme_ctrlr_cmd_directive_send(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
601 : : uint32_t doper, uint32_t dtype, uint32_t dspec,
602 : : void *payload, uint32_t payload_size, uint32_t cdw12,
603 : : uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
604 : : {
605 : 0 : return 0;
606 : : }
607 : :
608 : : int
609 : 0 : spdk_nvme_ctrlr_cmd_directive_receive(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
610 : : uint32_t doper, uint32_t dtype, uint32_t dspec,
611 : : void *payload, uint32_t payload_size, uint32_t cdw12,
612 : : uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
613 : : {
614 : 0 : return 0;
615 : : }
616 : :
617 : : int
618 : 9 : nvme_ctrlr_cmd_fw_commit(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_fw_commit *fw_commit,
619 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
620 : : {
621 : 9 : CU_ASSERT(fw_commit->ca == SPDK_NVME_FW_COMMIT_REPLACE_IMG);
622 [ + + ]: 9 : if (fw_commit->fs == 0) {
623 : 3 : return -1;
624 : : }
625 : 6 : set_status_cpl = 1;
626 [ + + + + ]: 6 : if (ctrlr->is_resetting == true) {
627 : 3 : set_status_cpl = 0;
628 : : }
629 : 6 : return 0;
630 : : }
631 : :
632 : : int
633 : 21 : nvme_ctrlr_cmd_fw_image_download(struct spdk_nvme_ctrlr *ctrlr,
634 : : uint32_t size, uint32_t offset, void *payload,
635 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
636 : : {
637 [ + + + + : 21 : if ((size != 0 && payload == NULL) || (size == 0 && payload != NULL)) {
+ + + - ]
638 : 6 : return -1;
639 : : }
640 : 15 : CU_ASSERT(offset == 0);
641 : 15 : return 0;
642 : : }
643 : :
644 : : bool
645 : 30 : nvme_ns_has_supported_iocs_specific_data(struct spdk_nvme_ns *ns)
646 : : {
647 [ + + - ]: 30 : switch (ns->csi) {
648 : 24 : case SPDK_NVME_CSI_NVM:
649 : : /*
650 : : * NVM Command Set Specific Identify Namespace data structure
651 : : * is currently all-zeroes, reserved for future use.
652 : : */
653 : 24 : return false;
654 : 6 : case SPDK_NVME_CSI_ZNS:
655 : 6 : return true;
656 : 0 : default:
657 : 0 : SPDK_WARNLOG("Unsupported CSI: %u for NSID: %u\n", ns->csi, ns->id);
658 : 0 : return false;
659 : : }
660 : : }
661 : :
662 : : void
663 : 18 : nvme_ns_free_zns_specific_data(struct spdk_nvme_ns *ns)
664 : : {
665 [ - + ]: 18 : if (!ns->id) {
666 : 0 : return;
667 : : }
668 : :
669 [ + + ]: 18 : if (ns->nsdata_zns) {
670 : 6 : spdk_free(ns->nsdata_zns);
671 : 6 : ns->nsdata_zns = NULL;
672 : : }
673 : : }
674 : :
675 : : void
676 : 0 : nvme_ns_free_nvm_specific_data(struct spdk_nvme_ns *ns)
677 : : {
678 [ # # ]: 0 : if (!ns->id) {
679 : 0 : return;
680 : : }
681 : :
682 [ # # ]: 0 : if (ns->nsdata_nvm) {
683 : 0 : spdk_free(ns->nsdata_nvm);
684 : 0 : ns->nsdata_nvm = NULL;
685 : : }
686 : : }
687 : :
688 : : void
689 : 55209 : nvme_ns_destruct(struct spdk_nvme_ns *ns)
690 : : {
691 : 55209 : }
692 : :
693 : : int
694 : 48 : nvme_ns_construct(struct spdk_nvme_ns *ns, uint32_t id,
695 : : struct spdk_nvme_ctrlr *ctrlr)
696 : : {
697 : 48 : return 0;
698 : : }
699 : :
700 : : void
701 : 3 : spdk_pci_device_detach(struct spdk_pci_device *device)
702 : : {
703 : 3 : }
704 : :
705 : : #define DECLARE_AND_CONSTRUCT_CTRLR() \
706 : : struct spdk_nvme_ctrlr ctrlr = {}; \
707 : : struct spdk_nvme_qpair adminq = {}; \
708 : : struct nvme_request req; \
709 : : \
710 : : STAILQ_INIT(&adminq.free_req); \
711 : : STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq); \
712 : : ctrlr.adminq = &adminq; \
713 : : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM;
714 : :
715 : : static void
716 : 3 : test_nvme_ctrlr_init_en_1_rdy_0(void)
717 : : {
718 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
719 : :
720 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
721 : :
722 : : /*
723 : : * Initial state: CC.EN = 1, CSTS.RDY = 0
724 : : */
725 : 3 : g_ut_nvme_regs.cc.bits.en = 1;
726 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
727 : :
728 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
729 : 3 : ctrlr.cdata.nn = 1;
730 : 3 : ctrlr.page_size = 0x1000;
731 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
732 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
733 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
734 : : }
735 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
736 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1);
737 : :
738 : : /*
739 : : * Transition to CSTS.RDY = 1.
740 : : * init() should set CC.EN = 0.
741 : : */
742 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
743 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
744 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_EN_0);
745 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
746 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
747 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
748 : :
749 : : /*
750 : : * Transition to CSTS.RDY = 0.
751 : : */
752 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
753 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
754 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
755 : :
756 : : /*
757 : : * Start enabling the controller.
758 : : */
759 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
760 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
761 : :
762 : : /*
763 : : * Transition to CC.EN = 1
764 : : */
765 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
766 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
767 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
768 : :
769 : : /*
770 : : * Transition to CSTS.RDY = 1.
771 : : */
772 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
773 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
774 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
775 : :
776 : : /*
777 : : * Transition to READY.
778 : : */
779 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
780 : 48 : nvme_ctrlr_process_init(&ctrlr);
781 : : }
782 : :
783 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
784 : 3 : nvme_ctrlr_destruct(&ctrlr);
785 : 3 : }
786 : :
787 : : static void
788 : 3 : test_nvme_ctrlr_init_en_1_rdy_1(void)
789 : : {
790 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
791 : :
792 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
793 : :
794 : : /*
795 : : * Initial state: CC.EN = 1, CSTS.RDY = 1
796 : : * init() should set CC.EN = 0.
797 : : */
798 : 3 : g_ut_nvme_regs.cc.bits.en = 1;
799 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
800 : :
801 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
802 : 3 : ctrlr.cdata.nn = 1;
803 : 3 : ctrlr.page_size = 0x1000;
804 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
805 [ + + ]: 21 : while (ctrlr.state != NVME_CTRLR_STATE_SET_EN_0) {
806 : 18 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
807 : : }
808 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
809 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
810 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
811 : :
812 : : /*
813 : : * Transition to CSTS.RDY = 0.
814 : : */
815 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
816 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
817 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
818 : :
819 : : /*
820 : : * Start enabling the controller.
821 : : */
822 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
823 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
824 : :
825 : : /*
826 : : * Transition to CC.EN = 1
827 : : */
828 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
829 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
830 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
831 : :
832 : : /*
833 : : * Transition to CSTS.RDY = 1.
834 : : */
835 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
836 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
837 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
838 : :
839 : : /*
840 : : * Transition to READY.
841 : : */
842 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
843 : 48 : nvme_ctrlr_process_init(&ctrlr);
844 : : }
845 : :
846 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
847 : 3 : nvme_ctrlr_destruct(&ctrlr);
848 : 3 : }
849 : :
850 : : static void
851 : 3 : test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void)
852 : : {
853 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
854 : :
855 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
856 : :
857 : : /*
858 : : * Initial state: CC.EN = 0, CSTS.RDY = 0
859 : : * init() should set CC.EN = 1.
860 : : */
861 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
862 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
863 : :
864 : : /*
865 : : * Default round robin enabled
866 : : */
867 : 3 : g_ut_nvme_regs.cap.bits.ams = 0x0;
868 : 3 : ctrlr.cap = g_ut_nvme_regs.cap;
869 : :
870 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
871 : 3 : ctrlr.cdata.nn = 1;
872 : 3 : ctrlr.page_size = 0x1000;
873 : : /*
874 : : * Case 1: default round robin arbitration mechanism selected
875 : : */
876 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
877 : :
878 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
879 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
880 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
881 : : }
882 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
883 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
884 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
885 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
886 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
887 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
888 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
889 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
890 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
891 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
892 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
893 : :
894 : : /*
895 : : * Complete and destroy the controller
896 : : */
897 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
898 : 3 : nvme_ctrlr_destruct(&ctrlr);
899 : :
900 : : /*
901 : : * Reset to initial state
902 : : */
903 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
904 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
905 : :
906 : : /*
907 : : * Case 2: weighted round robin arbitration mechanism selected
908 : : */
909 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
910 : 3 : ctrlr.cdata.nn = 1;
911 : 3 : ctrlr.page_size = 0x1000;
912 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
913 : :
914 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
915 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
916 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
917 : : }
918 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
919 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
920 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
921 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
922 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
923 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
924 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
925 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
926 : :
927 : : /*
928 : : * Complete and destroy the controller
929 : : */
930 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
931 : 3 : nvme_ctrlr_destruct(&ctrlr);
932 : :
933 : : /*
934 : : * Reset to initial state
935 : : */
936 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
937 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
938 : :
939 : : /*
940 : : * Case 3: vendor specific arbitration mechanism selected
941 : : */
942 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
943 : 3 : ctrlr.cdata.nn = 1;
944 : 3 : ctrlr.page_size = 0x1000;
945 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
946 : :
947 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
948 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
949 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
950 : : }
951 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
952 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
953 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
954 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
955 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
956 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
957 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
958 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
959 : :
960 : : /*
961 : : * Complete and destroy the controller
962 : : */
963 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
964 : 3 : nvme_ctrlr_destruct(&ctrlr);
965 : :
966 : : /*
967 : : * Reset to initial state
968 : : */
969 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
970 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
971 : :
972 : : /*
973 : : * Case 4: invalid arbitration mechanism selected
974 : : */
975 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
976 : 3 : ctrlr.cdata.nn = 1;
977 : 3 : ctrlr.page_size = 0x1000;
978 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;
979 : :
980 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
981 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
982 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
983 : : }
984 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
985 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
986 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
987 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
988 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
989 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
990 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
991 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
992 : :
993 : : /*
994 : : * Complete and destroy the controller
995 : : */
996 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
997 : 3 : nvme_ctrlr_destruct(&ctrlr);
998 : :
999 : : /*
1000 : : * Reset to initial state
1001 : : */
1002 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1003 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1004 : :
1005 : : /*
1006 : : * Case 5: reset to default round robin arbitration mechanism
1007 : : */
1008 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1009 : 3 : ctrlr.cdata.nn = 1;
1010 : 3 : ctrlr.page_size = 0x1000;
1011 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
1012 : :
1013 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1014 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1015 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1016 : : }
1017 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1018 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1019 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1020 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1021 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1022 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1023 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1024 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1025 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1026 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
1027 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
1028 : :
1029 : : /*
1030 : : * Transition to CSTS.RDY = 1.
1031 : : */
1032 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
1033 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1034 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1035 : :
1036 : : /*
1037 : : * Transition to READY.
1038 : : */
1039 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1040 : 48 : nvme_ctrlr_process_init(&ctrlr);
1041 : : }
1042 : :
1043 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1044 : 3 : nvme_ctrlr_destruct(&ctrlr);
1045 : 3 : }
1046 : :
1047 : : static void
1048 : 3 : test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void)
1049 : : {
1050 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
1051 : :
1052 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
1053 : :
1054 : : /*
1055 : : * Initial state: CC.EN = 0, CSTS.RDY = 0
1056 : : * init() should set CC.EN = 1.
1057 : : */
1058 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1059 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1060 : :
1061 : : /*
1062 : : * Weighted round robin enabled
1063 : : */
1064 : 3 : g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_WRR;
1065 : 3 : ctrlr.cap = g_ut_nvme_regs.cap;
1066 : :
1067 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1068 : 3 : ctrlr.cdata.nn = 1;
1069 : 3 : ctrlr.page_size = 0x1000;
1070 : : /*
1071 : : * Case 1: default round robin arbitration mechanism selected
1072 : : */
1073 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
1074 : :
1075 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1076 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1077 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1078 : : }
1079 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1080 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1081 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1082 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1083 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1084 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1085 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1086 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1087 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1088 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
1089 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
1090 : :
1091 : : /*
1092 : : * Complete and destroy the controller
1093 : : */
1094 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1095 : 3 : nvme_ctrlr_destruct(&ctrlr);
1096 : :
1097 : : /*
1098 : : * Reset to initial state
1099 : : */
1100 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1101 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1102 : :
1103 : : /*
1104 : : * Case 2: weighted round robin arbitration mechanism selected
1105 : : */
1106 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1107 : 3 : ctrlr.cdata.nn = 1;
1108 : 3 : ctrlr.page_size = 0x1000;
1109 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
1110 : :
1111 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1112 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1113 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1114 : : }
1115 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1116 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1117 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1118 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1119 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1120 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1121 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1122 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1123 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1124 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
1125 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR);
1126 : :
1127 : : /*
1128 : : * Complete and destroy the controller
1129 : : */
1130 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1131 : 3 : nvme_ctrlr_destruct(&ctrlr);
1132 : :
1133 : : /*
1134 : : * Reset to initial state
1135 : : */
1136 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1137 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1138 : :
1139 : : /*
1140 : : * Case 3: vendor specific arbitration mechanism selected
1141 : : */
1142 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1143 : 3 : ctrlr.cdata.nn = 1;
1144 : 3 : ctrlr.page_size = 0x1000;
1145 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
1146 : :
1147 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1148 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1149 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1150 : : }
1151 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1152 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1153 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1154 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1155 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1156 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1157 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
1158 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
1159 : :
1160 : : /*
1161 : : * Complete and destroy the controller
1162 : : */
1163 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1164 : 3 : nvme_ctrlr_destruct(&ctrlr);
1165 : :
1166 : : /*
1167 : : * Reset to initial state
1168 : : */
1169 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1170 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1171 : :
1172 : : /*
1173 : : * Case 4: invalid arbitration mechanism selected
1174 : : */
1175 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1176 : 3 : ctrlr.cdata.nn = 1;
1177 : 3 : ctrlr.page_size = 0x1000;
1178 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;
1179 : :
1180 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1181 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1182 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1183 : : }
1184 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1185 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1186 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1187 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1188 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1189 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1190 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
1191 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
1192 : :
1193 : : /*
1194 : : * Complete and destroy the controller
1195 : : */
1196 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1197 : 3 : nvme_ctrlr_destruct(&ctrlr);
1198 : :
1199 : : /*
1200 : : * Reset to initial state
1201 : : */
1202 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1203 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1204 : :
1205 : : /*
1206 : : * Case 5: reset to weighted round robin arbitration mechanism
1207 : : */
1208 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1209 : 3 : ctrlr.cdata.nn = 1;
1210 : 3 : ctrlr.page_size = 0x1000;
1211 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
1212 : :
1213 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1214 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1215 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1216 : : }
1217 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1218 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1219 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1220 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1221 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1222 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1223 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1224 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1225 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1226 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
1227 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR);
1228 : :
1229 : : /*
1230 : : * Transition to CSTS.RDY = 1.
1231 : : */
1232 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
1233 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1234 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1235 : :
1236 : : /*
1237 : : * Transition to READY.
1238 : : */
1239 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1240 : 48 : nvme_ctrlr_process_init(&ctrlr);
1241 : : }
1242 : :
1243 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1244 : 3 : nvme_ctrlr_destruct(&ctrlr);
1245 : 3 : }
1246 : : static void
1247 : 3 : test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void)
1248 : : {
1249 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
1250 : :
1251 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
1252 : :
1253 : : /*
1254 : : * Initial state: CC.EN = 0, CSTS.RDY = 0
1255 : : * init() should set CC.EN = 1.
1256 : : */
1257 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1258 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1259 : :
1260 : : /*
1261 : : * Default round robin enabled
1262 : : */
1263 : 3 : g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_VS;
1264 : 3 : ctrlr.cap = g_ut_nvme_regs.cap;
1265 : :
1266 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1267 : 3 : ctrlr.cdata.nn = 1;
1268 : 3 : ctrlr.page_size = 0x1000;
1269 : : /*
1270 : : * Case 1: default round robin arbitration mechanism selected
1271 : : */
1272 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
1273 : :
1274 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1275 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1276 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1277 : : }
1278 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1279 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1280 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1281 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1282 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1283 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1284 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1285 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1286 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1287 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
1288 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
1289 : :
1290 : : /*
1291 : : * Complete and destroy the controller
1292 : : */
1293 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1294 : 3 : nvme_ctrlr_destruct(&ctrlr);
1295 : :
1296 : : /*
1297 : : * Reset to initial state
1298 : : */
1299 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1300 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1301 : :
1302 : : /*
1303 : : * Case 2: weighted round robin arbitration mechanism selected
1304 : : */
1305 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1306 : 3 : ctrlr.cdata.nn = 1;
1307 : 3 : ctrlr.page_size = 0x1000;
1308 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
1309 : :
1310 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1311 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1312 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1313 : : }
1314 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1315 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1316 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1317 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1318 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1319 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1320 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
1321 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
1322 : :
1323 : : /*
1324 : : * Complete and destroy the controller
1325 : : */
1326 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1327 : 3 : nvme_ctrlr_destruct(&ctrlr);
1328 : :
1329 : : /*
1330 : : * Reset to initial state
1331 : : */
1332 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1333 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1334 : :
1335 : : /*
1336 : : * Case 3: vendor specific arbitration mechanism selected
1337 : : */
1338 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1339 : 3 : ctrlr.cdata.nn = 1;
1340 : 3 : ctrlr.page_size = 0x1000;
1341 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
1342 : :
1343 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1344 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1345 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1346 : : }
1347 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1348 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1349 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1350 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1351 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1352 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1353 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1354 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1355 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1356 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
1357 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS);
1358 : :
1359 : : /*
1360 : : * Complete and destroy the controller
1361 : : */
1362 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1363 : 3 : nvme_ctrlr_destruct(&ctrlr);
1364 : :
1365 : : /*
1366 : : * Reset to initial state
1367 : : */
1368 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1369 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1370 : :
1371 : : /*
1372 : : * Case 4: invalid arbitration mechanism selected
1373 : : */
1374 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1375 : 3 : ctrlr.cdata.nn = 1;
1376 : 3 : ctrlr.page_size = 0x1000;
1377 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;
1378 : :
1379 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1380 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1381 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1382 : : }
1383 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1384 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1385 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1386 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1387 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1388 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1389 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
1390 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
1391 : :
1392 : : /*
1393 : : * Complete and destroy the controller
1394 : : */
1395 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1396 : 3 : nvme_ctrlr_destruct(&ctrlr);
1397 : :
1398 : : /*
1399 : : * Reset to initial state
1400 : : */
1401 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1402 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1403 : :
1404 : : /*
1405 : : * Case 5: reset to vendor specific arbitration mechanism
1406 : : */
1407 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1408 : 3 : ctrlr.cdata.nn = 1;
1409 : 3 : ctrlr.page_size = 0x1000;
1410 : 3 : ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
1411 : :
1412 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1413 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1414 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1415 : : }
1416 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1417 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1418 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1419 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1420 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1421 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1422 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1423 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1424 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1425 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
1426 : 3 : CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS);
1427 : :
1428 : : /*
1429 : : * Transition to CSTS.RDY = 1.
1430 : : */
1431 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
1432 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1433 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1434 : :
1435 : : /*
1436 : : * Transition to READY.
1437 : : */
1438 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1439 : 48 : nvme_ctrlr_process_init(&ctrlr);
1440 : : }
1441 : :
1442 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1443 : 3 : nvme_ctrlr_destruct(&ctrlr);
1444 : 3 : }
1445 : :
1446 : : static void
1447 : 3 : test_nvme_ctrlr_init_en_0_rdy_0(void)
1448 : : {
1449 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
1450 : :
1451 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
1452 : :
1453 : : /*
1454 : : * Initial state: CC.EN = 0, CSTS.RDY = 0
1455 : : * init() should set CC.EN = 1.
1456 : : */
1457 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1458 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1459 : :
1460 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1461 : 3 : ctrlr.cdata.nn = 1;
1462 : 3 : ctrlr.page_size = 0x1000;
1463 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1464 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1465 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1466 : : }
1467 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1468 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1469 : :
1470 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1471 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1472 : :
1473 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1474 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1475 : :
1476 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1477 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1478 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1479 : :
1480 : : /*
1481 : : * Transition to CSTS.RDY = 1.
1482 : : */
1483 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
1484 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1485 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1486 : :
1487 : : /*
1488 : : * Transition to READY.
1489 : : */
1490 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1491 : 48 : nvme_ctrlr_process_init(&ctrlr);
1492 : : }
1493 : :
1494 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1495 : 3 : nvme_ctrlr_destruct(&ctrlr);
1496 : 3 : }
1497 : :
1498 : : static void
1499 : 3 : test_nvme_ctrlr_init_en_0_rdy_1(void)
1500 : : {
1501 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
1502 : :
1503 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
1504 : :
1505 : : /*
1506 : : * Initial state: CC.EN = 0, CSTS.RDY = 1
1507 : : */
1508 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
1509 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
1510 : :
1511 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1512 : 3 : ctrlr.cdata.nn = 1;
1513 : 3 : ctrlr.page_size = 0x1000;
1514 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1515 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1516 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1517 : : }
1518 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1519 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1520 : :
1521 : : /*
1522 : : * Transition to CSTS.RDY = 0.
1523 : : */
1524 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
1525 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1526 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1527 : :
1528 : : /*
1529 : : * Start enabling the controller.
1530 : : */
1531 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1532 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1533 : :
1534 : : /*
1535 : : * Transition to CC.EN = 1
1536 : : */
1537 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1538 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1539 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
1540 : :
1541 : : /*
1542 : : * Transition to CSTS.RDY = 1.
1543 : : */
1544 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
1545 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1546 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1547 : :
1548 : : /*
1549 : : * Transition to READY.
1550 : : */
1551 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1552 : 48 : nvme_ctrlr_process_init(&ctrlr);
1553 : : }
1554 : :
1555 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
1556 : 3 : nvme_ctrlr_destruct(&ctrlr);
1557 : 3 : }
1558 : :
1559 : : static void
1560 : 12 : setup_qpairs(struct spdk_nvme_ctrlr *ctrlr, uint32_t num_io_queues)
1561 : : {
1562 : : uint32_t i;
1563 : :
1564 [ - + ]: 12 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(ctrlr) == 0);
1565 : :
1566 : 12 : ctrlr->page_size = 0x1000;
1567 : 12 : ctrlr->opts.num_io_queues = num_io_queues;
1568 : 12 : ctrlr->free_io_qids = spdk_bit_array_create(num_io_queues + 1);
1569 : 12 : ctrlr->state = NVME_CTRLR_STATE_READY;
1570 [ - + ]: 12 : SPDK_CU_ASSERT_FATAL(ctrlr->free_io_qids != NULL);
1571 : :
1572 : 12 : spdk_bit_array_clear(ctrlr->free_io_qids, 0);
1573 [ + + ]: 36 : for (i = 1; i <= num_io_queues; i++) {
1574 : 24 : spdk_bit_array_set(ctrlr->free_io_qids, i);
1575 : : }
1576 : 12 : }
1577 : :
1578 : : static void
1579 : 12 : cleanup_qpairs(struct spdk_nvme_ctrlr *ctrlr)
1580 : : {
1581 : 12 : nvme_ctrlr_destruct(ctrlr);
1582 : 12 : }
1583 : :
1584 : : static void
1585 : 3 : test_alloc_io_qpair_rr_1(void)
1586 : : {
1587 : 3 : struct spdk_nvme_io_qpair_opts opts;
1588 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
1589 : : struct spdk_nvme_qpair *q0;
1590 : :
1591 : 3 : setup_qpairs(&ctrlr, 1);
1592 : :
1593 : : /*
1594 : : * Fake to simulate the controller with default round robin
1595 : : * arbitration mechanism.
1596 : : */
1597 : 3 : g_ut_nvme_regs.cc.bits.ams = SPDK_NVME_CC_AMS_RR;
1598 : :
1599 : 3 : spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
1600 : :
1601 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0);
1602 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 != NULL);
1603 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
1604 : : /* Only 1 I/O qpair was allocated, so this should fail */
1605 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0) == NULL);
1606 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
1607 : :
1608 : : /*
1609 : : * Now that the qpair has been returned to the free list,
1610 : : * we should be able to allocate it again.
1611 : : */
1612 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0);
1613 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 != NULL);
1614 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
1615 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
1616 : :
1617 : : /* Only 0 qprio is acceptable for default round robin arbitration mechanism */
1618 : 3 : opts.qprio = 1;
1619 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1620 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 == NULL);
1621 : :
1622 : 3 : opts.qprio = 2;
1623 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1624 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 == NULL);
1625 : :
1626 : 3 : opts.qprio = 3;
1627 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1628 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 == NULL);
1629 : :
1630 : : /* Only 0 ~ 3 qprio is acceptable */
1631 : 3 : opts.qprio = 4;
1632 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL);
1633 : 3 : opts.qprio = 0;
1634 : :
1635 : : /* IO qpair can only be created when ctrlr is in READY state */
1636 : 3 : ctrlr.state = NVME_CTRLR_STATE_ENABLE;
1637 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1638 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 == NULL);
1639 : 3 : ctrlr.state = NVME_CTRLR_STATE_READY;
1640 : :
1641 : 3 : cleanup_qpairs(&ctrlr);
1642 : 3 : }
1643 : :
1644 : : static void
1645 : 3 : test_alloc_io_qpair_wrr_1(void)
1646 : : {
1647 : 3 : struct spdk_nvme_io_qpair_opts opts;
1648 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
1649 : : struct spdk_nvme_qpair *q0, *q1;
1650 : :
1651 : 3 : setup_qpairs(&ctrlr, 2);
1652 : :
1653 : : /*
1654 : : * Fake to simulate the controller with weighted round robin
1655 : : * arbitration mechanism.
1656 : : */
1657 : 3 : ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR;
1658 : :
1659 : 3 : spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
1660 : :
1661 : : /*
1662 : : * Allocate 2 qpairs and free them
1663 : : */
1664 : 3 : opts.qprio = 0;
1665 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1666 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 != NULL);
1667 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
1668 : :
1669 : 3 : opts.qprio = 1;
1670 : 3 : q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1671 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1 != NULL);
1672 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1->qprio == 1);
1673 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
1674 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
1675 : :
1676 : : /*
1677 : : * Allocate 2 qpairs and free them in the reverse order
1678 : : */
1679 : 3 : opts.qprio = 2;
1680 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1681 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 != NULL);
1682 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0->qprio == 2);
1683 : :
1684 : 3 : opts.qprio = 3;
1685 : 3 : q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1686 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1 != NULL);
1687 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1->qprio == 3);
1688 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
1689 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
1690 : :
1691 : : /* Only 0 ~ 3 qprio is acceptable */
1692 : 3 : opts.qprio = 4;
1693 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL);
1694 : :
1695 : 3 : cleanup_qpairs(&ctrlr);
1696 : 3 : }
1697 : :
1698 : : static void
1699 : 3 : test_alloc_io_qpair_wrr_2(void)
1700 : : {
1701 : 3 : struct spdk_nvme_io_qpair_opts opts;
1702 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
1703 : : struct spdk_nvme_qpair *q0, *q1, *q2, *q3;
1704 : :
1705 : 3 : setup_qpairs(&ctrlr, 4);
1706 : :
1707 : : /*
1708 : : * Fake to simulate the controller with weighted round robin
1709 : : * arbitration mechanism.
1710 : : */
1711 : 3 : ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR;
1712 : :
1713 : 3 : spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
1714 : :
1715 : 3 : opts.qprio = 0;
1716 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1717 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 != NULL);
1718 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
1719 : :
1720 : 3 : opts.qprio = 1;
1721 : 3 : q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1722 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1 != NULL);
1723 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1->qprio == 1);
1724 : :
1725 : 3 : opts.qprio = 2;
1726 : 3 : q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1727 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q2 != NULL);
1728 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q2->qprio == 2);
1729 : :
1730 : 3 : opts.qprio = 3;
1731 : 3 : q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1732 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q3 != NULL);
1733 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q3->qprio == 3);
1734 : :
1735 : : /* Only 4 I/O qpairs was allocated, so this should fail */
1736 : 3 : opts.qprio = 0;
1737 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL);
1738 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0);
1739 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0);
1740 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
1741 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
1742 : :
1743 : : /*
1744 : : * Now that the qpair has been returned to the free list,
1745 : : * we should be able to allocate it again.
1746 : : *
1747 : : * Allocate 4 I/O qpairs and half of them with same qprio.
1748 : : */
1749 : 3 : opts.qprio = 1;
1750 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1751 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 != NULL);
1752 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0->qprio == 1);
1753 : :
1754 : 3 : opts.qprio = 1;
1755 : 3 : q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1756 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1 != NULL);
1757 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q1->qprio == 1);
1758 : :
1759 : 3 : opts.qprio = 3;
1760 : 3 : q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1761 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q2 != NULL);
1762 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q2->qprio == 3);
1763 : :
1764 : 3 : opts.qprio = 3;
1765 : 3 : q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
1766 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q3 != NULL);
1767 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q3->qprio == 3);
1768 : :
1769 : : /*
1770 : : * Free all I/O qpairs in reverse order
1771 : : */
1772 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
1773 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
1774 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0);
1775 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0);
1776 : :
1777 : 3 : cleanup_qpairs(&ctrlr);
1778 : 3 : }
1779 : :
1780 : : bool g_connect_qpair_called = false;
1781 : : int g_connect_qpair_return_code = 0;
1782 : : int
1783 : 111 : nvme_transport_ctrlr_connect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
1784 : : {
1785 : 111 : g_connect_qpair_called = true;
1786 : 111 : qpair->state = NVME_QPAIR_CONNECTED;
1787 : 111 : return g_connect_qpair_return_code;
1788 : : }
1789 : :
1790 : : static void
1791 : 3 : test_spdk_nvme_ctrlr_reconnect_io_qpair(void)
1792 : : {
1793 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
1794 : 3 : struct spdk_nvme_qpair qpair = {};
1795 : : int rc;
1796 : :
1797 [ - + ]: 3 : CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
1798 : :
1799 : : /* Various states of controller disconnect. */
1800 : 3 : qpair.id = 1;
1801 : 3 : qpair.ctrlr = &ctrlr;
1802 : 3 : ctrlr.is_removed = 1;
1803 : 3 : ctrlr.is_failed = 0;
1804 : 3 : ctrlr.is_resetting = 0;
1805 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1806 : 3 : CU_ASSERT(rc == -ENODEV)
1807 : :
1808 : 3 : ctrlr.is_removed = 0;
1809 : 3 : ctrlr.is_failed = 1;
1810 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1811 : 3 : CU_ASSERT(rc == -ENXIO)
1812 : :
1813 : 3 : ctrlr.is_failed = 0;
1814 : 3 : ctrlr.is_resetting = 1;
1815 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1816 : 3 : CU_ASSERT(rc == -EAGAIN)
1817 : :
1818 : : /* Confirm precedence for controller states: removed > resetting > failed */
1819 : 3 : ctrlr.is_removed = 1;
1820 : 3 : ctrlr.is_failed = 1;
1821 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1822 : 3 : CU_ASSERT(rc == -ENODEV)
1823 : :
1824 : 3 : ctrlr.is_removed = 0;
1825 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1826 : 3 : CU_ASSERT(rc == -EAGAIN)
1827 : :
1828 : 3 : ctrlr.is_resetting = 0;
1829 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1830 : 3 : CU_ASSERT(rc == -ENXIO)
1831 : :
1832 : : /* qpair not failed. Make sure we don't call down to the transport */
1833 : 3 : ctrlr.is_failed = 0;
1834 : 3 : qpair.state = NVME_QPAIR_CONNECTED;
1835 : 3 : g_connect_qpair_called = false;
1836 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1837 [ - + ]: 3 : CU_ASSERT(g_connect_qpair_called == false);
1838 : 3 : CU_ASSERT(rc == 0)
1839 : :
1840 : : /* transport qpair is failed. make sure we call down to the transport */
1841 : 3 : qpair.state = NVME_QPAIR_DISCONNECTED;
1842 : 3 : rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
1843 [ - + ]: 3 : CU_ASSERT(g_connect_qpair_called == true);
1844 : 3 : CU_ASSERT(rc == 0)
1845 : :
1846 [ - + ]: 3 : CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
1847 : 3 : }
1848 : :
1849 : : static void
1850 : 3 : test_nvme_ctrlr_fail(void)
1851 : : {
1852 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
1853 : :
1854 : 3 : ctrlr.opts.num_io_queues = 0;
1855 : 3 : nvme_ctrlr_fail(&ctrlr, false);
1856 : :
1857 [ - + ]: 3 : CU_ASSERT(ctrlr.is_failed == true);
1858 : 3 : }
1859 : :
1860 : : static void
1861 : 3 : test_nvme_ctrlr_construct_intel_support_log_page_list(void)
1862 : : {
1863 : : bool res;
1864 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
1865 : 3 : struct spdk_nvme_intel_log_page_directory payload = {};
1866 : 3 : struct spdk_pci_id pci_id = {};
1867 : :
1868 : : /* Get quirks for a device with all 0 vendor/device id */
1869 : 3 : ctrlr.quirks = nvme_get_quirks(&pci_id);
1870 : 3 : CU_ASSERT(ctrlr.quirks == 0);
1871 : :
1872 : : /* Set the vendor to Intel, but provide no device id */
1873 : 3 : pci_id.class_id = SPDK_PCI_CLASS_NVME;
1874 : 3 : ctrlr.cdata.vid = pci_id.vendor_id = SPDK_PCI_VID_INTEL;
1875 : 3 : payload.temperature_statistics_log_len = 1;
1876 : 3 : ctrlr.quirks = nvme_get_quirks(&pci_id);
1877 [ - + ]: 3 : memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
1878 : :
1879 : 3 : nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
1880 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY);
1881 : 3 : CU_ASSERT(res == true);
1882 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE);
1883 : 3 : CU_ASSERT(res == true);
1884 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY);
1885 : 3 : CU_ASSERT(res == false);
1886 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART);
1887 : 3 : CU_ASSERT(res == false);
1888 : :
1889 : : /* set valid vendor id, device id and sub device id */
1890 : 3 : ctrlr.cdata.vid = SPDK_PCI_VID_INTEL;
1891 : 3 : payload.temperature_statistics_log_len = 0;
1892 : 3 : pci_id.vendor_id = SPDK_PCI_VID_INTEL;
1893 : 3 : pci_id.device_id = 0x0953;
1894 : 3 : pci_id.subvendor_id = SPDK_PCI_VID_INTEL;
1895 : 3 : pci_id.subdevice_id = 0x3702;
1896 : 3 : ctrlr.quirks = nvme_get_quirks(&pci_id);
1897 [ - + ]: 3 : memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
1898 : :
1899 : 3 : nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
1900 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY);
1901 : 3 : CU_ASSERT(res == true);
1902 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE);
1903 : 3 : CU_ASSERT(res == false);
1904 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY);
1905 : 3 : CU_ASSERT(res == true);
1906 : 3 : res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART);
1907 : 3 : CU_ASSERT(res == false);
1908 : 3 : }
1909 : :
1910 : : static void
1911 : 3 : test_nvme_ctrlr_set_supported_features(void)
1912 : : {
1913 : : bool res;
1914 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
1915 : :
1916 : : /* set a invalid vendor id */
1917 : 3 : ctrlr.cdata.vid = 0xFFFF;
1918 : 3 : nvme_ctrlr_set_supported_features(&ctrlr);
1919 : 3 : res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION);
1920 : 3 : CU_ASSERT(res == true);
1921 : 3 : res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA);
1922 : 3 : CU_ASSERT(res == false);
1923 : :
1924 : 3 : ctrlr.cdata.vid = SPDK_PCI_VID_INTEL;
1925 : 3 : nvme_ctrlr_set_supported_features(&ctrlr);
1926 : 3 : res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION);
1927 : 3 : CU_ASSERT(res == true);
1928 : 3 : res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA);
1929 : 3 : CU_ASSERT(res == true);
1930 : 3 : }
1931 : :
1932 : : static void
1933 : 3 : test_nvme_ctrlr_set_host_feature(void)
1934 : : {
1935 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
1936 : :
1937 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
1938 : :
1939 : 3 : ctrlr.cdata.ctratt.bits.elbas = 0;
1940 : 3 : ctrlr.state = NVME_CTRLR_STATE_SET_HOST_FEATURE;
1941 : :
1942 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1943 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_DB_BUF_CFG);
1944 : :
1945 : 3 : ctrlr.cdata.ctratt.bits.elbas = 1;
1946 : 3 : ctrlr.state = NVME_CTRLR_STATE_SET_HOST_FEATURE;
1947 : :
1948 [ + + ]: 6 : while (ctrlr.state != NVME_CTRLR_STATE_SET_DB_BUF_CFG) {
1949 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
1950 : : }
1951 : :
1952 : 3 : CU_ASSERT(ctrlr.tmp_ptr == NULL);
1953 [ - + ]: 3 : CU_ASSERT(ctrlr.feature_supported[SPDK_NVME_FEAT_HOST_BEHAVIOR_SUPPORT] == true);
1954 : :
1955 : 3 : nvme_ctrlr_destruct(&ctrlr);
1956 : 3 : }
1957 : :
1958 : : static void
1959 : 3 : test_ctrlr_get_default_ctrlr_opts(void)
1960 : : {
1961 : 3 : struct spdk_nvme_ctrlr_opts opts = {};
1962 : :
1963 : 3 : CU_ASSERT(spdk_uuid_parse(&g_spdk_nvme_driver->default_extended_host_id, UT_HOSTID) == 0);
1964 : :
1965 : 3 : memset(&opts, 0, sizeof(opts));
1966 : :
1967 : : /* set a smaller opts_size */
1968 : 3 : CU_ASSERT(sizeof(opts) > 8);
1969 : 3 : spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, 8);
1970 : 3 : CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES);
1971 [ - + ]: 3 : CU_ASSERT_FALSE(opts.use_cmb_sqs);
1972 : : /* check below fields are not initialized by default value */
1973 : 3 : CU_ASSERT_EQUAL(opts.arb_mechanism, 0);
1974 : 3 : CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 0);
1975 : 3 : CU_ASSERT_EQUAL(opts.io_queue_size, 0);
1976 : 3 : CU_ASSERT_EQUAL(opts.io_queue_requests, 0);
1977 [ + + ]: 27 : for (int i = 0; i < 8; i++) {
1978 : 24 : CU_ASSERT(opts.host_id[i] == 0);
1979 : : }
1980 [ + + ]: 51 : for (int i = 0; i < 16; i++) {
1981 : 48 : CU_ASSERT(opts.extended_host_id[i] == 0);
1982 : : }
1983 : 3 : CU_ASSERT(strlen(opts.hostnqn) == 0);
1984 : 3 : CU_ASSERT(strlen(opts.src_addr) == 0);
1985 : 3 : CU_ASSERT(strlen(opts.src_svcid) == 0);
1986 : 3 : CU_ASSERT_EQUAL(opts.admin_timeout_ms, 0);
1987 : :
1988 : : /* set a consistent opts_size */
1989 : 3 : spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, sizeof(opts));
1990 : 3 : CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES);
1991 [ - + ]: 3 : CU_ASSERT_FALSE(opts.use_cmb_sqs);
1992 : 3 : CU_ASSERT_EQUAL(opts.arb_mechanism, SPDK_NVME_CC_AMS_RR);
1993 : 3 : CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 10 * 1000);
1994 : 3 : CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE);
1995 : 3 : CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
1996 [ + + ]: 27 : for (int i = 0; i < 8; i++) {
1997 : 24 : CU_ASSERT(opts.host_id[i] == 0);
1998 : : }
1999 : 3 : CU_ASSERT_STRING_EQUAL(opts.hostnqn,
2000 : : "nqn.2014-08.org.nvmexpress:uuid:e53e9258-c93b-48b5-be1a-f025af6d232a");
2001 [ - + ]: 3 : CU_ASSERT(memcmp(opts.extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
2002 : : sizeof(opts.extended_host_id)) == 0);
2003 : 3 : CU_ASSERT(strlen(opts.src_addr) == 0);
2004 : 3 : CU_ASSERT(strlen(opts.src_svcid) == 0);
2005 : 3 : CU_ASSERT_EQUAL(opts.admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
2006 : 3 : }
2007 : :
2008 : : static void
2009 : 3 : test_ctrlr_get_default_io_qpair_opts(void)
2010 : : {
2011 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2012 : 3 : struct spdk_nvme_io_qpair_opts opts = {};
2013 : :
2014 [ - + ]: 3 : memset(&opts, 0, sizeof(opts));
2015 : :
2016 : : /* set a smaller opts_size */
2017 : 3 : ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE;
2018 : 3 : CU_ASSERT(sizeof(opts) > 8);
2019 : 3 : spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, 8);
2020 : 3 : CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT);
2021 : 3 : CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE);
2022 : : /* check below field is not initialized by default value */
2023 : 3 : CU_ASSERT_EQUAL(opts.io_queue_requests, 0);
2024 : :
2025 : : /* set a consistent opts_size */
2026 : 3 : ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE;
2027 : 3 : ctrlr.opts.io_queue_requests = DEFAULT_IO_QUEUE_REQUESTS;
2028 : 3 : spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
2029 : 3 : CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT);
2030 : 3 : CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE);
2031 : 3 : CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
2032 [ - + ]: 3 : CU_ASSERT_EQUAL(opts.delay_cmd_submit, false);
2033 : 3 : CU_ASSERT_EQUAL(opts.sq.vaddr, NULL);
2034 : 3 : CU_ASSERT_EQUAL(opts.sq.paddr, 0);
2035 : 3 : CU_ASSERT_EQUAL(opts.sq.buffer_size, 0);
2036 : 3 : CU_ASSERT_EQUAL(opts.cq.vaddr, NULL);
2037 : 3 : CU_ASSERT_EQUAL(opts.cq.paddr, 0);
2038 : 3 : CU_ASSERT_EQUAL(opts.cq.buffer_size, 0);
2039 [ - + ]: 3 : CU_ASSERT_EQUAL(opts.create_only, false);
2040 [ - + ]: 3 : CU_ASSERT_EQUAL(opts.async_mode, false);
2041 [ - + ]: 3 : CU_ASSERT_EQUAL(opts.disable_pcie_sgl_merge, false);
2042 : 3 : CU_ASSERT_EQUAL(opts.opts_size, sizeof(opts));
2043 : 3 : }
2044 : :
2045 : : #if 0 /* TODO: move to PCIe-specific unit test */
2046 : : static void
2047 : : test_nvme_ctrlr_alloc_cmb(void)
2048 : : {
2049 : : int rc;
2050 : : uint64_t offset;
2051 : : struct spdk_nvme_ctrlr ctrlr = {};
2052 : :
2053 : : ctrlr.cmb_size = 0x1000000;
2054 : : ctrlr.cmb_current_offset = 0x100;
2055 : : rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x200, 0x1000, &offset);
2056 : : CU_ASSERT(rc == 0);
2057 : : CU_ASSERT(offset == 0x1000);
2058 : : CU_ASSERT(ctrlr.cmb_current_offset == 0x1200);
2059 : :
2060 : : rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800, 0x1000, &offset);
2061 : : CU_ASSERT(rc == 0);
2062 : : CU_ASSERT(offset == 0x2000);
2063 : : CU_ASSERT(ctrlr.cmb_current_offset == 0x2800);
2064 : :
2065 : : rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800000, 0x100000, &offset);
2066 : : CU_ASSERT(rc == 0);
2067 : : CU_ASSERT(offset == 0x100000);
2068 : : CU_ASSERT(ctrlr.cmb_current_offset == 0x900000);
2069 : :
2070 : : rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x8000000, 0x1000, &offset);
2071 : : CU_ASSERT(rc == -1);
2072 : : }
2073 : : #endif
2074 : :
2075 : : static void
2076 : 3 : test_spdk_nvme_ctrlr_update_firmware(void)
2077 : : {
2078 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2079 : 3 : void *payload = NULL;
2080 : 3 : int point_payload = 1;
2081 : 3 : int slot = 0;
2082 : 3 : int ret = 0;
2083 : 3 : struct spdk_nvme_status status;
2084 : 3 : enum spdk_nvme_fw_commit_action commit_action = SPDK_NVME_FW_COMMIT_REPLACE_IMG;
2085 : :
2086 [ - + ]: 3 : CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
2087 : :
2088 : : /* Set invalid size check function return value */
2089 : 3 : set_size = 5;
2090 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2091 : 3 : CU_ASSERT(ret == -1);
2092 : :
2093 : : /* When payload is NULL but set_size < min_page_size */
2094 : 3 : set_size = 4;
2095 : 3 : ctrlr.min_page_size = 5;
2096 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2097 : 3 : CU_ASSERT(ret == -1);
2098 : :
2099 : : /* When payload not NULL but min_page_size is 0 */
2100 : 3 : set_size = 4;
2101 : 3 : ctrlr.min_page_size = 0;
2102 : 3 : payload = &point_payload;
2103 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2104 : 3 : CU_ASSERT(ret == -1);
2105 : :
2106 : : /* Check firmware image download when payload not NULL and min_page_size not 0 , status.cpl value is 1 */
2107 : 3 : set_status_cpl = 1;
2108 : 3 : set_size = 4;
2109 : 3 : ctrlr.min_page_size = 5;
2110 : 3 : payload = &point_payload;
2111 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2112 : 3 : CU_ASSERT(ret == -ENXIO);
2113 : :
2114 : : /* Check firmware image download and set status.cpl value is 0 */
2115 : 3 : set_status_cpl = 0;
2116 : 3 : set_size = 4;
2117 : 3 : ctrlr.min_page_size = 5;
2118 : 3 : payload = &point_payload;
2119 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2120 : 3 : CU_ASSERT(ret == -1);
2121 : :
2122 : : /* Check firmware commit */
2123 : 3 : ctrlr.is_resetting = false;
2124 : 3 : set_status_cpl = 0;
2125 : 3 : slot = 1;
2126 : 3 : set_size = 4;
2127 : 3 : ctrlr.min_page_size = 5;
2128 : 3 : payload = &point_payload;
2129 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2130 : 3 : CU_ASSERT(ret == -ENXIO);
2131 : :
2132 : : /* Set size check firmware download and firmware commit */
2133 : 3 : ctrlr.is_resetting = true;
2134 : 3 : set_status_cpl = 0;
2135 : 3 : slot = 1;
2136 : 3 : set_size = 4;
2137 : 3 : ctrlr.min_page_size = 5;
2138 : 3 : payload = &point_payload;
2139 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2140 : 3 : CU_ASSERT(ret == 0);
2141 : :
2142 : : /* nvme_wait_for_completion returns an error */
2143 : 3 : g_wait_for_completion_return_val = -1;
2144 : 3 : ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
2145 : 3 : CU_ASSERT(ret == -ENXIO);
2146 : 3 : CU_ASSERT(g_failed_status != NULL);
2147 [ - + ]: 3 : CU_ASSERT(g_failed_status->timed_out == true);
2148 : : /* status should be freed by callback, which is not triggered in test env.
2149 : : Store status to global variable and free it manually.
2150 : : If spdk_nvme_ctrlr_update_firmware changes its behaviour and frees the status
2151 : : itself, we'll get a double free here.. */
2152 : 3 : free(g_failed_status);
2153 : 3 : g_failed_status = NULL;
2154 : 3 : g_wait_for_completion_return_val = 0;
2155 : :
2156 [ - + ]: 3 : CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
2157 : 3 : set_status_cpl = 0;
2158 : 3 : }
2159 : :
2160 : : int
2161 : 3 : nvme_ctrlr_cmd_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr, uint64_t prp1, uint64_t prp2,
2162 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
2163 : : {
2164 : 3 : fake_cpl_sc(cb_fn, cb_arg);
2165 : 3 : return 0;
2166 : : }
2167 : :
2168 : : static void
2169 : 3 : test_spdk_nvme_ctrlr_doorbell_buffer_config(void)
2170 : : {
2171 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2172 : 3 : int ret = -1;
2173 : :
2174 : 3 : ctrlr.cdata.oacs.doorbell_buffer_config = 1;
2175 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
2176 : 3 : ctrlr.page_size = 0x1000;
2177 [ - - - + ]: 3 : MOCK_CLEAR(spdk_malloc);
2178 [ - - - + ]: 3 : MOCK_CLEAR(spdk_zmalloc);
2179 : 3 : ret = nvme_ctrlr_set_doorbell_buffer_config(&ctrlr);
2180 : 3 : CU_ASSERT(ret == 0);
2181 : 3 : nvme_ctrlr_free_doorbell_buffer(&ctrlr);
2182 : 3 : }
2183 : :
2184 : : static void
2185 : 3 : test_nvme_ctrlr_test_active_ns(void)
2186 : : {
2187 : : uint32_t nsid, minor;
2188 : : size_t ns_id_count;
2189 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2190 : 3 : uint32_t active_ns_list[1531];
2191 : :
2192 [ + + ]: 4596 : for (nsid = 1; nsid <= 1531; nsid++) {
2193 : 4593 : active_ns_list[nsid - 1] = nsid;
2194 : : }
2195 : :
2196 : 3 : g_active_ns_list = active_ns_list;
2197 : :
2198 : 3 : ctrlr.page_size = 0x1000;
2199 : :
2200 [ + + ]: 12 : for (minor = 0; minor <= 2; minor++) {
2201 [ - + ]: 9 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2202 : 9 : ctrlr.state = NVME_CTRLR_STATE_READY;
2203 : :
2204 : 9 : ctrlr.vs.bits.mjr = 1;
2205 : 9 : ctrlr.vs.bits.mnr = minor;
2206 : 9 : ctrlr.vs.bits.ter = 0;
2207 : 9 : ctrlr.cdata.nn = 1531;
2208 : :
2209 : 9 : RB_INIT(&ctrlr.ns);
2210 : :
2211 : 9 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2212 : 9 : nvme_ctrlr_identify_active_ns(&ctrlr);
2213 : :
2214 [ + + ]: 13788 : for (nsid = 1; nsid <= ctrlr.cdata.nn; nsid++) {
2215 : 13779 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true);
2216 : : }
2217 : :
2218 [ + + ]: 261 : for (; nsid <= 1559; nsid++) {
2219 : 252 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == false);
2220 : : }
2221 : :
2222 : 9 : g_active_ns_list_length = 0;
2223 [ + + ]: 9 : if (minor <= 1) {
2224 : 6 : ctrlr.cdata.nn = 0;
2225 : : }
2226 : 9 : nvme_ctrlr_identify_active_ns(&ctrlr);
2227 : 9 : CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0);
2228 : :
2229 : 9 : g_active_ns_list_length = 1;
2230 [ + + ]: 9 : if (minor <= 1) {
2231 : 6 : ctrlr.cdata.nn = 1;
2232 : : }
2233 : 9 : nvme_ctrlr_identify_active_ns(&ctrlr);
2234 : 9 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true);
2235 : 9 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false);
2236 : 9 : nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr);
2237 : 9 : CU_ASSERT(nsid == 1);
2238 : :
2239 [ + + ]: 9 : if (minor >= 2) {
2240 : : /* For NVMe 1.2 and newer, the namespace list can have "holes" where
2241 : : * some namespaces are not active. Test this. */
2242 : 3 : g_active_ns_list_length = 2;
2243 : 3 : g_active_ns_list[1] = 3;
2244 : 3 : nvme_ctrlr_identify_active_ns(&ctrlr);
2245 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true);
2246 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false);
2247 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3) == true);
2248 : 3 : nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid);
2249 : 3 : CU_ASSERT(nsid == 3);
2250 : 3 : nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid);
2251 : 3 : CU_ASSERT(nsid == 0);
2252 : :
2253 : : /* Reset the active namespace list array */
2254 : 3 : g_active_ns_list[1] = 2;
2255 : : }
2256 : :
2257 : 9 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2258 [ + + ]: 9 : if (minor <= 1) {
2259 : 6 : ctrlr.cdata.nn = 1531;
2260 : : }
2261 : 9 : nvme_ctrlr_identify_active_ns(&ctrlr);
2262 : :
2263 : 9 : ns_id_count = 0;
2264 : 9 : for (nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr);
2265 [ + + ]: 13788 : nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid)) {
2266 : 13779 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true);
2267 : 13779 : ns_id_count++;
2268 : : }
2269 : 9 : CU_ASSERT(ns_id_count == ctrlr.cdata.nn);
2270 : :
2271 : 9 : nvme_ctrlr_destruct(&ctrlr);
2272 : : }
2273 : :
2274 : 3 : g_active_ns_list = NULL;
2275 : 3 : g_active_ns_list_length = 0;
2276 : 3 : }
2277 : :
2278 : : static void
2279 : 3 : test_nvme_ctrlr_test_active_ns_error_case(void)
2280 : : {
2281 : : int rc;
2282 : 3 : struct spdk_nvme_ctrlr ctrlr = {.state = NVME_CTRLR_STATE_READY};
2283 : :
2284 : 3 : ctrlr.page_size = 0x1000;
2285 : 3 : ctrlr.vs.bits.mjr = 1;
2286 : 3 : ctrlr.vs.bits.mnr = 2;
2287 : 3 : ctrlr.vs.bits.ter = 0;
2288 : 3 : ctrlr.cdata.nn = 2;
2289 : :
2290 : 3 : set_status_code = SPDK_NVME_SC_INVALID_FIELD;
2291 : 3 : rc = nvme_ctrlr_identify_active_ns(&ctrlr);
2292 : 3 : CU_ASSERT(rc == -ENXIO);
2293 : 3 : set_status_code = SPDK_NVME_SC_SUCCESS;
2294 : 3 : }
2295 : :
2296 : : static void
2297 : 3 : test_nvme_ctrlr_init_delay(void)
2298 : : {
2299 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2300 : :
2301 [ - + ]: 3 : memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
2302 : :
2303 : : /*
2304 : : * Initial state: CC.EN = 0, CSTS.RDY = 0
2305 : : * init() should set CC.EN = 1.
2306 : : */
2307 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
2308 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
2309 : :
2310 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2311 : : /* Test that the initialization delay works correctly. We only
2312 : : * do the initialization delay on SSDs that require it, so
2313 : : * set that quirk here.
2314 : : */
2315 : 3 : ctrlr.quirks = NVME_QUIRK_DELAY_BEFORE_INIT;
2316 : 3 : ctrlr.cdata.nn = 1;
2317 : 3 : ctrlr.page_size = 0x1000;
2318 : 3 : ctrlr.state = NVME_CTRLR_STATE_INIT_DELAY;
2319 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2320 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
2321 : 3 : CU_ASSERT(ctrlr.sleep_timeout_tsc != 0);
2322 : :
2323 : : /* delay 1s, just return as sleep time isn't enough */
2324 : 3 : spdk_delay_us(1 * spdk_get_ticks_hz());
2325 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2326 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
2327 : 3 : CU_ASSERT(ctrlr.sleep_timeout_tsc != 0);
2328 : :
2329 : : /* sleep timeout, start to initialize */
2330 : 3 : spdk_delay_us(2 * spdk_get_ticks_hz());
2331 [ + + ]: 15 : while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
2332 : 12 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2333 : : }
2334 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2335 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
2336 : :
2337 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2338 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
2339 : :
2340 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2341 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
2342 : :
2343 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2344 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
2345 : 3 : CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
2346 : :
2347 : : /*
2348 : : * Transition to CSTS.RDY = 1.
2349 : : */
2350 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
2351 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2352 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
2353 : :
2354 : : /*
2355 : : * Transition to READY.
2356 : : */
2357 [ + + ]: 51 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
2358 : 48 : nvme_ctrlr_process_init(&ctrlr);
2359 : : }
2360 : :
2361 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
2362 : 3 : nvme_ctrlr_destruct(&ctrlr);
2363 : 3 : }
2364 : :
2365 : : static void
2366 : 3 : test_spdk_nvme_ctrlr_set_trid(void)
2367 : : {
2368 : 3 : struct spdk_nvme_ctrlr ctrlr = {{0}};
2369 : 3 : struct spdk_nvme_transport_id new_trid = {{0}};
2370 : :
2371 : 3 : CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
2372 : :
2373 : 3 : ctrlr.is_failed = false;
2374 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA;
2375 : 3 : snprintf(ctrlr.trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1");
2376 : 3 : snprintf(ctrlr.trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.8");
2377 : 3 : snprintf(ctrlr.trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4420");
2378 : 3 : CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EPERM);
2379 : :
2380 : 3 : ctrlr.is_failed = true;
2381 : 3 : new_trid.trtype = SPDK_NVME_TRANSPORT_TCP;
2382 : 3 : CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL);
2383 : 3 : CU_ASSERT(ctrlr.trid.trtype == SPDK_NVME_TRANSPORT_RDMA);
2384 : :
2385 : 3 : new_trid.trtype = SPDK_NVME_TRANSPORT_RDMA;
2386 : 3 : snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode2");
2387 : 3 : CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL);
2388 : 3 : CU_ASSERT(strncmp(ctrlr.trid.subnqn, "nqn.2016-06.io.spdk:cnode1", SPDK_NVMF_NQN_MAX_LEN) == 0);
2389 : :
2390 : :
2391 : 3 : snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1");
2392 : 3 : snprintf(new_trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.9");
2393 : 3 : snprintf(new_trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4421");
2394 : 3 : CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == 0);
2395 : 3 : CU_ASSERT(strncmp(ctrlr.trid.traddr, "192.168.100.9", SPDK_NVMF_TRADDR_MAX_LEN) == 0);
2396 : 3 : CU_ASSERT(strncmp(ctrlr.trid.trsvcid, "4421", SPDK_NVMF_TRSVCID_MAX_LEN) == 0);
2397 : :
2398 : 3 : CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
2399 : 3 : }
2400 : :
2401 : : static void
2402 : 3 : test_nvme_ctrlr_init_set_nvmf_ioccsz(void)
2403 : : {
2404 : 3 : struct spdk_nvme_ctrlr_data cdata = {};
2405 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2406 : : /* equivalent of 4096 bytes */
2407 : 3 : cdata.nvmf_specific.ioccsz = 260;
2408 : 3 : cdata.nvmf_specific.icdoff = 1;
2409 : 3 : g_cdata = &cdata;
2410 : :
2411 : : /* Check PCI trtype, */
2412 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2413 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
2414 : :
2415 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2416 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2417 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2418 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2419 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2420 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2421 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2422 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2423 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2424 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2425 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2426 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2427 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2428 : :
2429 : 3 : CU_ASSERT(ctrlr.ioccsz_bytes == 0);
2430 : 3 : CU_ASSERT(ctrlr.icdoff == 0);
2431 : :
2432 : 3 : nvme_ctrlr_destruct(&ctrlr);
2433 : :
2434 : : /* Check RDMA trtype, */
2435 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2436 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA;
2437 : :
2438 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2439 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2440 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2441 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2442 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2443 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2444 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2445 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2446 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2447 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2448 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2449 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2450 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2451 : :
2452 : 3 : CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
2453 : 3 : CU_ASSERT(ctrlr.icdoff == 1);
2454 : 3 : ctrlr.ioccsz_bytes = 0;
2455 : 3 : ctrlr.icdoff = 0;
2456 : :
2457 : 3 : nvme_ctrlr_destruct(&ctrlr);
2458 : :
2459 : : /* Check TCP trtype, */
2460 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2461 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_TCP;
2462 : :
2463 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2464 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2465 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2466 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2467 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2468 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2469 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2470 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2471 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2472 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2473 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2474 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2475 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2476 : :
2477 : 3 : CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
2478 : 3 : CU_ASSERT(ctrlr.icdoff == 1);
2479 : 3 : ctrlr.ioccsz_bytes = 0;
2480 : 3 : ctrlr.icdoff = 0;
2481 : :
2482 : 3 : nvme_ctrlr_destruct(&ctrlr);
2483 : :
2484 : : /* Check FC trtype, */
2485 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2486 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_FC;
2487 : :
2488 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2489 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2490 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2491 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2492 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2493 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2494 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2495 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2496 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2497 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2498 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2499 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2500 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2501 : :
2502 : 3 : CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
2503 : 3 : CU_ASSERT(ctrlr.icdoff == 1);
2504 : 3 : ctrlr.ioccsz_bytes = 0;
2505 : 3 : ctrlr.icdoff = 0;
2506 : :
2507 : 3 : nvme_ctrlr_destruct(&ctrlr);
2508 : :
2509 : : /* Check CUSTOM trtype, */
2510 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2511 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM;
2512 : :
2513 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2514 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2515 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2516 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2517 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2518 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2519 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2520 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2521 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2522 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2523 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2524 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2525 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2526 : :
2527 : 3 : CU_ASSERT(ctrlr.ioccsz_bytes == 0);
2528 : 3 : CU_ASSERT(ctrlr.icdoff == 0);
2529 : :
2530 : 3 : nvme_ctrlr_destruct(&ctrlr);
2531 : :
2532 : : /* Check CUSTOM_FABRICS trtype, */
2533 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2534 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM_FABRICS;
2535 : :
2536 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2537 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2538 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2539 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2540 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2541 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2542 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2543 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2544 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2545 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2546 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2547 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2548 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2549 : :
2550 : 3 : CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
2551 : 3 : CU_ASSERT(ctrlr.icdoff == 1);
2552 : 3 : ctrlr.ioccsz_bytes = 0;
2553 : 3 : ctrlr.icdoff = 0;
2554 : :
2555 : 3 : nvme_ctrlr_destruct(&ctrlr);
2556 : :
2557 : 3 : g_cdata = NULL;
2558 : 3 : }
2559 : :
2560 : : static void
2561 : 3 : test_nvme_ctrlr_init_set_num_queues(void)
2562 : : {
2563 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2564 : :
2565 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2566 : :
2567 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2568 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2569 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2570 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2571 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2572 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2573 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2574 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
2575 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2576 : :
2577 : 3 : ctrlr.opts.num_io_queues = 64;
2578 : : /* Num queues is zero-based. So, use 31 to get 32 queues */
2579 : 3 : fake_cpl.cdw0 = 31 + (31 << 16);
2580 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_ACTIVE_NS */
2581 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2582 : 3 : CU_ASSERT(ctrlr.opts.num_io_queues == 32);
2583 : 3 : fake_cpl.cdw0 = 0;
2584 : :
2585 : 3 : nvme_ctrlr_destruct(&ctrlr);
2586 : 3 : }
2587 : :
2588 : : static void
2589 : 3 : test_nvme_ctrlr_init_set_keep_alive_timeout(void)
2590 : : {
2591 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2592 : :
2593 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2594 : :
2595 : 3 : ctrlr.opts.keep_alive_timeout_ms = 60000;
2596 : 3 : ctrlr.cdata.kas = 1;
2597 : 3 : ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
2598 : 3 : fake_cpl.cdw0 = 120000;
2599 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */
2600 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2601 : 3 : CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 120000);
2602 : 3 : fake_cpl.cdw0 = 0;
2603 : :
2604 : : /* Target does not support Get Feature "Keep Alive Timer" */
2605 : 3 : ctrlr.opts.keep_alive_timeout_ms = 60000;
2606 : 3 : ctrlr.cdata.kas = 1;
2607 : 3 : ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
2608 : 3 : set_status_code = SPDK_NVME_SC_INVALID_FIELD;
2609 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */
2610 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2611 : 3 : CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 60000);
2612 : 3 : set_status_code = SPDK_NVME_SC_SUCCESS;
2613 : :
2614 : : /* Target fails Get Feature "Keep Alive Timer" for another reason */
2615 : 3 : ctrlr.opts.keep_alive_timeout_ms = 60000;
2616 : 3 : ctrlr.cdata.kas = 1;
2617 : 3 : ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
2618 : 3 : set_status_code = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR;
2619 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> ERROR */
2620 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
2621 : 3 : set_status_code = SPDK_NVME_SC_SUCCESS;
2622 : :
2623 : 3 : nvme_ctrlr_destruct(&ctrlr);
2624 : 3 : }
2625 : :
2626 : : static void
2627 : 3 : test_alloc_io_qpair_fail(void)
2628 : : {
2629 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2630 : : struct spdk_nvme_qpair *q0;
2631 : :
2632 : 3 : setup_qpairs(&ctrlr, 1);
2633 : :
2634 : : /* Modify the connect_qpair return code to inject a failure */
2635 : 3 : g_connect_qpair_return_code = 1;
2636 : :
2637 : : /* Attempt to allocate a qpair, this should fail */
2638 : 3 : q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0);
2639 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(q0 == NULL);
2640 : :
2641 : : /* Verify that the qpair is removed from the lists */
2642 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(TAILQ_EMPTY(&ctrlr.active_io_qpairs));
2643 : :
2644 : 3 : g_connect_qpair_return_code = 0;
2645 : 3 : cleanup_qpairs(&ctrlr);
2646 : 3 : }
2647 : :
2648 : : static void
2649 : 3 : test_nvme_ctrlr_add_remove_process(void)
2650 : : {
2651 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2652 : 3 : void *devhandle = (void *)0xDEADBEEF;
2653 : 3 : struct spdk_nvme_ctrlr_process *proc = NULL;
2654 : : int rc;
2655 : :
2656 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
2657 : 3 : TAILQ_INIT(&ctrlr.active_procs);
2658 : :
2659 : 3 : rc = nvme_ctrlr_add_process(&ctrlr, devhandle);
2660 : 3 : CU_ASSERT(rc == 0);
2661 : 3 : proc = TAILQ_FIRST(&ctrlr.active_procs);
2662 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(proc != NULL);
2663 [ - + ]: 3 : CU_ASSERT(proc->is_primary == true);
2664 : 3 : CU_ASSERT(proc->pid == getpid());
2665 : 3 : CU_ASSERT(proc->devhandle == (void *)0xDEADBEEF);
2666 : 3 : CU_ASSERT(proc->ref == 0);
2667 : :
2668 : 3 : nvme_ctrlr_remove_process(&ctrlr, proc);
2669 : 3 : CU_ASSERT(TAILQ_EMPTY(&ctrlr.active_procs));
2670 : 3 : }
2671 : :
2672 : : static void
2673 : 3 : test_nvme_ctrlr_set_arbitration_feature(void)
2674 : : {
2675 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2676 : :
2677 : 3 : ctrlr.opts.arbitration_burst = 6;
2678 : 3 : ctrlr.flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
2679 : 3 : ctrlr.opts.low_priority_weight = 1;
2680 : 3 : ctrlr.opts.medium_priority_weight = 2;
2681 : 3 : ctrlr.opts.high_priority_weight = 3;
2682 : : /* g_ut_cdw11 used to record value command feature set. */
2683 : 3 : g_ut_cdw11 = 0;
2684 : :
2685 : : /* arbitration_burst count available. */
2686 : 3 : nvme_ctrlr_set_arbitration_feature(&ctrlr);
2687 : 3 : CU_ASSERT((uint8_t)g_ut_cdw11 == 6);
2688 : 3 : CU_ASSERT((uint8_t)(g_ut_cdw11 >> 8) == 1);
2689 : 3 : CU_ASSERT((uint8_t)(g_ut_cdw11 >> 16) == 2);
2690 : 3 : CU_ASSERT((uint8_t)(g_ut_cdw11 >> 24) == 3);
2691 : :
2692 : : /* arbitration_burst unavailable. */
2693 : 3 : g_ut_cdw11 = 0;
2694 : 3 : ctrlr.opts.arbitration_burst = 8;
2695 : :
2696 : 3 : nvme_ctrlr_set_arbitration_feature(&ctrlr);
2697 : 3 : CU_ASSERT(g_ut_cdw11 == 0);
2698 : 3 : }
2699 : :
2700 : : static void
2701 : 3 : test_nvme_ctrlr_set_state(void)
2702 : : {
2703 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
2704 : 3 : MOCK_SET(spdk_get_ticks, 0);
2705 : :
2706 : 3 : nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000);
2707 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2708 : 3 : CU_ASSERT(ctrlr.state_timeout_tsc == 1000000);
2709 : :
2710 : 3 : nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 0);
2711 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2712 : 3 : CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
2713 : :
2714 : : /* Time out ticks causes integer overflow. */
2715 : 3 : MOCK_SET(spdk_get_ticks, UINT64_MAX);
2716 : :
2717 : 3 : nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000);
2718 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2719 : 3 : CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
2720 [ - - - + ]: 3 : MOCK_CLEAR(spdk_get_ticks);
2721 : 3 : }
2722 : :
2723 : : static void
2724 : 3 : test_nvme_ctrlr_active_ns_list_v0(void)
2725 : : {
2726 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2727 : :
2728 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2729 : :
2730 : 3 : ctrlr.vs.bits.mjr = 1;
2731 : 3 : ctrlr.vs.bits.mnr = 0;
2732 : 3 : ctrlr.vs.bits.ter = 0;
2733 : 3 : ctrlr.cdata.nn = 1024;
2734 : :
2735 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2736 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
2737 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2738 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
2739 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
2740 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
2741 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1);
2742 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024);
2743 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
2744 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0);
2745 : :
2746 : 3 : nvme_ctrlr_destruct(&ctrlr);
2747 : 3 : }
2748 : :
2749 : : static void
2750 : 3 : test_nvme_ctrlr_active_ns_list_v2(void)
2751 : : {
2752 : : uint32_t i;
2753 : 3 : uint32_t active_ns_list[1024];
2754 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2755 : :
2756 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2757 : :
2758 : 3 : ctrlr.vs.bits.mjr = 1;
2759 : 3 : ctrlr.vs.bits.mnr = 2;
2760 : 3 : ctrlr.vs.bits.ter = 0;
2761 : 3 : ctrlr.cdata.nn = 4096;
2762 : :
2763 : 3 : g_active_ns_list = active_ns_list;
2764 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2765 : :
2766 : : /* No active namespaces */
2767 [ - + ]: 3 : memset(active_ns_list, 0, sizeof(active_ns_list));
2768 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2769 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
2770 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2771 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
2772 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
2773 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
2774 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0);
2775 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
2776 : :
2777 : 3 : nvme_ctrlr_destruct(&ctrlr);
2778 : :
2779 : : /* 1024 active namespaces - one full page */
2780 [ - + ]: 3 : memset(active_ns_list, 0, sizeof(active_ns_list));
2781 [ + + ]: 3075 : for (i = 0; i < 1024; ++i) {
2782 : 3072 : active_ns_list[i] = i + 1;
2783 : : }
2784 : :
2785 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2786 : :
2787 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2788 : 3 : g_active_ns_list = active_ns_list;
2789 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2790 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
2791 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2792 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
2793 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
2794 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
2795 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1);
2796 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024);
2797 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
2798 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0);
2799 : :
2800 : 3 : nvme_ctrlr_destruct(&ctrlr);
2801 : :
2802 : : /* 1023 active namespaces - full page minus one */
2803 [ - + ]: 3 : memset(active_ns_list, 0, sizeof(active_ns_list));
2804 [ + + ]: 3072 : for (i = 0; i < 1023; ++i) {
2805 : 3069 : active_ns_list[i] = i + 1;
2806 : : }
2807 : :
2808 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2809 : :
2810 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2811 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
2812 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2813 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
2814 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1023));
2815 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
2816 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
2817 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1);
2818 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 0);
2819 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
2820 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0);
2821 : :
2822 : 3 : nvme_ctrlr_destruct(&ctrlr);
2823 : :
2824 : 3 : g_active_ns_list = NULL;
2825 : 3 : g_active_ns_list_length = 0;
2826 : 3 : }
2827 : :
2828 : : static void
2829 : 3 : test_nvme_ctrlr_ns_mgmt(void)
2830 : : {
2831 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2832 : 3 : uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
2833 : 3 : uint32_t active_ns_list2[] = { 1, 2, 3, 100, 1024 };
2834 : 3 : struct spdk_nvme_ns_data nsdata = {};
2835 : 3 : struct spdk_nvme_ctrlr_list ctrlr_list = {};
2836 : : uint32_t nsid;
2837 : :
2838 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2839 : :
2840 : 3 : ctrlr.vs.bits.mjr = 1;
2841 : 3 : ctrlr.vs.bits.mnr = 2;
2842 : 3 : ctrlr.vs.bits.ter = 0;
2843 : 3 : ctrlr.cdata.nn = 4096;
2844 : :
2845 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2846 : 3 : g_active_ns_list = active_ns_list;
2847 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2848 [ + + ]: 33 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
2849 [ - + ]: 30 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
2850 : : }
2851 : :
2852 : 3 : fake_cpl.cdw0 = 3;
2853 : 3 : nsid = spdk_nvme_ctrlr_create_ns(&ctrlr, &nsdata);
2854 : 3 : fake_cpl.cdw0 = 0;
2855 : 3 : CU_ASSERT(nsid == 3);
2856 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
2857 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
2858 : :
2859 : 3 : g_active_ns_list = active_ns_list2;
2860 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2);
2861 : 3 : CU_ASSERT(spdk_nvme_ctrlr_attach_ns(&ctrlr, 3, &ctrlr_list) == 0);
2862 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
2863 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
2864 : :
2865 : 3 : g_active_ns_list = active_ns_list;
2866 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2867 : 3 : CU_ASSERT(spdk_nvme_ctrlr_detach_ns(&ctrlr, 3, &ctrlr_list) == 0);
2868 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
2869 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
2870 : :
2871 : 3 : CU_ASSERT(spdk_nvme_ctrlr_delete_ns(&ctrlr, 3) == 0);
2872 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
2873 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
2874 : 3 : g_active_ns_list = NULL;
2875 : 3 : g_active_ns_list_length = 0;
2876 : :
2877 : 3 : nvme_ctrlr_destruct(&ctrlr);
2878 : 3 : }
2879 : :
2880 : : static void
2881 : 3 : check_en_set_rdy(void)
2882 : : {
2883 [ + - ]: 3 : if (g_ut_nvme_regs.cc.bits.en == 1) {
2884 : 3 : g_ut_nvme_regs.csts.bits.rdy = 1;
2885 : : }
2886 : 3 : }
2887 : :
2888 : : static void
2889 : 3 : test_nvme_ctrlr_reset(void)
2890 : : {
2891 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2892 : 3 : struct spdk_nvme_ctrlr_data cdata = { .nn = 4096 };
2893 : 3 : uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
2894 : 3 : uint32_t active_ns_list2[] = { 1, 100, 1024 };
2895 : :
2896 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2897 : :
2898 : 3 : g_ut_nvme_regs.vs.bits.mjr = 1;
2899 : 3 : g_ut_nvme_regs.vs.bits.mnr = 2;
2900 : 3 : g_ut_nvme_regs.vs.bits.ter = 0;
2901 : 3 : nvme_ctrlr_get_vs(&ctrlr, &ctrlr.vs);
2902 : 3 : ctrlr.cdata.nn = 2048;
2903 : :
2904 : 3 : ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2905 : 3 : g_active_ns_list = active_ns_list;
2906 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2907 [ + + ]: 33 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
2908 [ - + ]: 30 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
2909 : : }
2910 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 2048);
2911 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL);
2912 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2));
2913 : :
2914 : : /* Reset controller with changed number of namespaces */
2915 : 3 : g_cdata = &cdata;
2916 : 3 : g_active_ns_list = active_ns_list2;
2917 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2);
2918 [ - + ]: 3 : STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq);
2919 : 3 : g_ut_nvme_regs.cc.raw = 0;
2920 : 3 : g_ut_nvme_regs.csts.raw = 0;
2921 : 3 : g_set_reg_cb = check_en_set_rdy;
2922 : 3 : g_wait_for_completion_return_val = -ENXIO;
2923 : 3 : CU_ASSERT(spdk_nvme_ctrlr_reset(&ctrlr) == 0);
2924 : 3 : g_set_reg_cb = NULL;
2925 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
2926 : 3 : g_cdata = NULL;
2927 : 3 : g_active_ns_list = NULL;
2928 : 3 : g_active_ns_list_length = 0;
2929 : :
2930 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 4096);
2931 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL);
2932 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2));
2933 : :
2934 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
2935 : 3 : nvme_ctrlr_destruct(&ctrlr);
2936 : :
2937 : 3 : g_wait_for_completion_return_val = 0;
2938 : 3 : }
2939 : :
2940 : : static uint32_t g_aer_cb_counter;
2941 : :
2942 : : static void
2943 : 9 : aer_cb(void *aer_cb_arg, const struct spdk_nvme_cpl *cpl)
2944 : : {
2945 : 9 : g_aer_cb_counter++;
2946 : 9 : }
2947 : :
2948 : : static void
2949 : 3 : test_nvme_ctrlr_aer_callback(void)
2950 : : {
2951 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2952 : 3 : uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
2953 : 3 : union spdk_nvme_async_event_completion aer_event = {
2954 : : .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE,
2955 : : .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED
2956 : : };
2957 : 3 : struct spdk_nvme_cpl aer_cpl = {
2958 : : .status.sct = SPDK_NVME_SCT_GENERIC,
2959 : : .status.sc = SPDK_NVME_SC_SUCCESS,
2960 : 3 : .cdw0 = aer_event.raw
2961 : : };
2962 : :
2963 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
2964 : :
2965 : 3 : ctrlr.vs.bits.mjr = 1;
2966 : 3 : ctrlr.vs.bits.mnr = 2;
2967 : 3 : ctrlr.vs.bits.ter = 0;
2968 : 3 : ctrlr.cdata.nn = 4096;
2969 : :
2970 : 3 : ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
2971 : 3 : g_active_ns_list = active_ns_list;
2972 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
2973 [ + + ]: 45 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
2974 [ - + ]: 42 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
2975 : : }
2976 : :
2977 : 3 : CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0);
2978 : 3 : spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL);
2979 : :
2980 : : /* Async event */
2981 : 3 : g_aer_cb_counter = 0;
2982 : 3 : nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
2983 : 3 : nvme_ctrlr_complete_queued_async_events(&ctrlr);
2984 : 3 : CU_ASSERT(g_aer_cb_counter == 1);
2985 : 3 : g_active_ns_list = NULL;
2986 : 3 : g_active_ns_list_length = 0;
2987 : :
2988 : 3 : nvme_ctrlr_free_processes(&ctrlr);
2989 : 3 : nvme_ctrlr_destruct(&ctrlr);
2990 : 3 : }
2991 : :
2992 : : static void
2993 : 3 : test_nvme_ctrlr_ns_attr_changed(void)
2994 : : {
2995 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
2996 : 3 : uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
2997 : 3 : uint32_t active_ns_list2[] = { 1, 2, 1024 };
2998 : 3 : uint32_t active_ns_list3[] = { 1, 2, 101, 1024 };
2999 : 3 : union spdk_nvme_async_event_completion aer_event = {
3000 : : .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE,
3001 : : .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED
3002 : : };
3003 : 3 : struct spdk_nvme_cpl aer_cpl = {
3004 : : .status.sct = SPDK_NVME_SCT_GENERIC,
3005 : : .status.sc = SPDK_NVME_SC_SUCCESS,
3006 : 3 : .cdw0 = aer_event.raw
3007 : : };
3008 : :
3009 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
3010 : :
3011 : 3 : ctrlr.vs.bits.mjr = 1;
3012 : 3 : ctrlr.vs.bits.mnr = 3;
3013 : 3 : ctrlr.vs.bits.ter = 0;
3014 : 3 : ctrlr.cap.bits.css |= SPDK_NVME_CAP_CSS_IOCS;
3015 : 3 : ctrlr.cdata.nn = 4096;
3016 : :
3017 : 3 : ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
3018 : 3 : g_active_ns_list = active_ns_list;
3019 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
3020 : :
3021 [ + + ]: 45 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
3022 [ - + ]: 42 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
3023 : : }
3024 : :
3025 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100));
3026 : :
3027 : 3 : CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0);
3028 : 3 : spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL);
3029 : :
3030 : : /* Remove NS 100 */
3031 : 3 : g_aer_cb_counter = 0;
3032 : 3 : g_active_ns_list = active_ns_list2;
3033 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2);
3034 : 3 : nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
3035 : 3 : nvme_ctrlr_complete_queued_async_events(&ctrlr);
3036 : 3 : CU_ASSERT(g_aer_cb_counter == 1);
3037 : 3 : CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100));
3038 : :
3039 : : /* Add NS 101 */
3040 : 3 : g_active_ns_list = active_ns_list3;
3041 : 3 : g_active_ns_list_length = SPDK_COUNTOF(active_ns_list3);
3042 : 3 : nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
3043 : 3 : nvme_ctrlr_complete_queued_async_events(&ctrlr);
3044 : 3 : CU_ASSERT(g_aer_cb_counter == 2);
3045 : 3 : CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 101));
3046 : :
3047 : 3 : g_active_ns_list = NULL;
3048 : 3 : g_active_ns_list_length = 0;
3049 : 3 : nvme_ctrlr_free_processes(&ctrlr);
3050 : 3 : nvme_ctrlr_destruct(&ctrlr);
3051 : 3 : }
3052 : :
3053 : : static void
3054 : 3 : test_nvme_ctrlr_identify_namespaces_iocs_specific_next(void)
3055 : : {
3056 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
3057 : : uint32_t prev_nsid;
3058 : 3 : struct spdk_nvme_ns ns[5] = {};
3059 : 3 : struct spdk_nvme_ctrlr ns_ctrlr[5] = {};
3060 : 3 : int rc = 0;
3061 : : int i;
3062 : :
3063 : 3 : RB_INIT(&ctrlr.ns);
3064 [ + + ]: 18 : for (i = 0; i < 5; i++) {
3065 : 15 : ns[i].id = i + 1;
3066 : 15 : ns[i].active = true;
3067 : : }
3068 : :
3069 [ - + ]: 3 : CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
3070 : :
3071 : 3 : ctrlr.cdata.nn = 5;
3072 : : /* case 1: No first/next active NS, move on to the next state, expect: pass */
3073 : 3 : prev_nsid = 0;
3074 : 3 : ctrlr.active_ns_count = 0;
3075 : 3 : ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
3076 : 3 : rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
3077 : 3 : CU_ASSERT(rc == 0);
3078 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES);
3079 : 3 : CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
3080 : :
3081 : : /* case 2: move on to the next active NS, and no namespace with (supported) iocs specific data found , expect: pass */
3082 : 1 : memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
3083 : 1 : memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc));
3084 : 3 : prev_nsid = 1;
3085 [ + + ]: 18 : for (i = 0; i < 5; i++) {
3086 : 15 : RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]);
3087 : : }
3088 : 3 : ctrlr.active_ns_count = 5;
3089 : 3 : ns[1].csi = SPDK_NVME_CSI_NVM;
3090 : 3 : ns[1].id = 2;
3091 : 3 : rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
3092 : 3 : CU_ASSERT(rc == 0);
3093 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES);
3094 : 3 : CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
3095 : :
3096 : : /* case 3: ns.csi is SPDK_NVME_CSI_ZNS, do not loop, expect: pass */
3097 : 1 : memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
3098 : 1 : memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc));
3099 : 3 : ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
3100 : 3 : prev_nsid = 0;
3101 : 3 : ctrlr.active_ns_count = 5;
3102 : :
3103 [ + + ]: 18 : for (int i = 0; i < 5; i++) {
3104 : 15 : ns[i].csi = SPDK_NVME_CSI_NVM;
3105 : 15 : ns[i].id = i + 1;
3106 : 15 : ns[i].ctrlr = &ns_ctrlr[i];
3107 : : }
3108 : 3 : ns[4].csi = SPDK_NVME_CSI_ZNS;
3109 : 3 : ns_ctrlr[4].opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
3110 : :
3111 : 3 : rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
3112 : 3 : CU_ASSERT(rc == 0);
3113 : 3 : CU_ASSERT(ctrlr.state == 0);
3114 : 3 : CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
3115 : 3 : CU_ASSERT(ns_ctrlr[4].state == NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC);
3116 : 3 : CU_ASSERT(ns_ctrlr[4].state_timeout_tsc == NVME_TIMEOUT_INFINITE);
3117 : :
3118 [ + + ]: 18 : for (int i = 0; i < 5; i++) {
3119 : 15 : nvme_ns_free_zns_specific_data(&ns[i]);
3120 : : }
3121 : :
3122 : : /* case 4: nvme_ctrlr_identify_ns_iocs_specific_async return 1, expect: false */
3123 : 1 : memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
3124 : 1 : memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc));
3125 : 3 : prev_nsid = 1;
3126 : 3 : ctrlr.active_ns_count = 5;
3127 : 3 : ns[1].csi = SPDK_NVME_CSI_ZNS;
3128 : 3 : g_fail_next_identify = true;
3129 : 3 : rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
3130 : 3 : CU_ASSERT(rc == 1);
3131 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
3132 : 3 : CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
3133 : :
3134 [ - + ]: 3 : CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
3135 : 3 : }
3136 : :
3137 : : static void
3138 : 3 : test_nvme_ctrlr_set_supported_log_pages(void)
3139 : : {
3140 : : int rc;
3141 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
3142 : :
3143 : : /* ana supported */
3144 [ - + ]: 3 : memset(&ctrlr, 0, sizeof(ctrlr));
3145 : 3 : ctrlr.cdata.cmic.ana_reporting = true;
3146 : 3 : ctrlr.cdata.lpa.celp = 1;
3147 : 3 : ctrlr.cdata.nanagrpid = 1;
3148 : 3 : ctrlr.active_ns_count = 1;
3149 : :
3150 : 3 : rc = nvme_ctrlr_set_supported_log_pages(&ctrlr);
3151 : 3 : CU_ASSERT(rc == 0);
3152 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true);
3153 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true);
3154 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true);
3155 : 3 : CU_ASSERT(ctrlr.ana_log_page_size == sizeof(struct spdk_nvme_ana_page) +
3156 : : sizeof(struct spdk_nvme_ana_group_descriptor) * 1 + sizeof(uint32_t) * 1);
3157 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] == true);
3158 : 3 : free(ctrlr.ana_log_page);
3159 : 3 : free(ctrlr.copied_ana_desc);
3160 : 3 : }
3161 : :
3162 : : static void
3163 : 3 : test_nvme_ctrlr_set_intel_supported_log_pages(void)
3164 : : {
3165 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
3166 : :
3167 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
3168 : :
3169 : 3 : ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
3170 : 3 : ctrlr.cdata.vid = SPDK_PCI_VID_INTEL;
3171 : 3 : ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
3172 : 3 : ctrlr.state = NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES;
3173 : :
3174 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
3175 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES);
3176 : :
3177 : 3 : set_status_code = SPDK_NVME_SC_SUCCESS;
3178 : 3 : CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
3179 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES);
3180 : :
3181 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true);
3182 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true);
3183 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true);
3184 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] == true);
3185 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] == true);
3186 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] == true);
3187 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_SMART] == true);
3188 [ - + ]: 3 : CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] == true);
3189 : :
3190 : 3 : nvme_ctrlr_destruct(&ctrlr);
3191 : 3 : }
3192 : :
3193 : : #define UT_ANA_DESC_SIZE (sizeof(struct spdk_nvme_ana_group_descriptor) + \
3194 : : sizeof(uint32_t))
3195 : : static void
3196 : 3 : test_nvme_ctrlr_parse_ana_log_page(void)
3197 : : {
3198 : : int rc, i;
3199 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
3200 : 3 : struct spdk_nvme_ns ns[3] = {};
3201 : 3 : struct spdk_nvme_ana_page ana_hdr;
3202 : 3 : char _ana_desc[UT_ANA_DESC_SIZE];
3203 : : struct spdk_nvme_ana_group_descriptor *ana_desc;
3204 : : uint32_t offset;
3205 : :
3206 : 3 : RB_INIT(&ctrlr.ns);
3207 [ + + ]: 12 : for (i = 0; i < 3; i++) {
3208 : 9 : ns[i].id = i + 1;
3209 : 9 : ns[i].active = true;
3210 : 9 : RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]);
3211 : : }
3212 : :
3213 [ - + ]: 3 : CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
3214 : :
3215 : 3 : ctrlr.cdata.nn = 3;
3216 : 3 : ctrlr.cdata.nanagrpid = 3;
3217 : 3 : ctrlr.active_ns_count = 3;
3218 : :
3219 : 3 : rc = nvme_ctrlr_update_ana_log_page(&ctrlr);
3220 : 3 : CU_ASSERT(rc == 0);
3221 : 3 : CU_ASSERT(ctrlr.ana_log_page != NULL);
3222 : 3 : CU_ASSERT(ctrlr.copied_ana_desc != NULL);
3223 : :
3224 : : /*
3225 : : * Create ANA log page data - There are three ANA groups.
3226 : : * Each ANA group has a namespace and has a different ANA state.
3227 : : */
3228 [ - + ]: 3 : memset(&ana_hdr, 0, sizeof(ana_hdr));
3229 : 3 : ana_hdr.num_ana_group_desc = 3;
3230 : :
3231 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(sizeof(ana_hdr) <= ctrlr.ana_log_page_size);
3232 : 3 : memcpy((char *)ctrlr.ana_log_page, (char *)&ana_hdr, sizeof(ana_hdr));
3233 : 3 : offset = sizeof(ana_hdr);
3234 : :
3235 : 3 : ana_desc = (struct spdk_nvme_ana_group_descriptor *)_ana_desc;
3236 [ - + ]: 3 : memset(ana_desc, 0, UT_ANA_DESC_SIZE);
3237 : 3 : ana_desc->num_of_nsid = 1;
3238 : :
3239 : 3 : ana_desc->ana_group_id = 1;
3240 : 3 : ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE;
3241 : 3 : ana_desc->nsid[0] = 3;
3242 : :
3243 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size);
3244 [ - + - + ]: 3 : memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE);
3245 : 3 : offset += UT_ANA_DESC_SIZE;
3246 : :
3247 : 3 : ana_desc->ana_group_id = 2;
3248 : 3 : ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE;
3249 : 3 : ana_desc->nsid[0] = 2;
3250 : :
3251 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size);
3252 [ - + - + ]: 3 : memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE);
3253 : 3 : offset += UT_ANA_DESC_SIZE;
3254 : :
3255 : 3 : ana_desc->ana_group_id = 3;
3256 : 3 : ana_desc->ana_state = SPDK_NVME_ANA_INACCESSIBLE_STATE;
3257 : 3 : ana_desc->nsid[0] = 1;
3258 : :
3259 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size);
3260 [ - + - + ]: 3 : memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE);
3261 : :
3262 : : /* Parse the created ANA log page data, and update ANA states. */
3263 : 3 : rc = nvme_ctrlr_parse_ana_log_page(&ctrlr, nvme_ctrlr_update_ns_ana_states,
3264 : : &ctrlr);
3265 : 3 : CU_ASSERT(rc == 0);
3266 : 3 : CU_ASSERT(ns[0].ana_group_id == 3);
3267 : 3 : CU_ASSERT(ns[0].ana_state == SPDK_NVME_ANA_INACCESSIBLE_STATE);
3268 : 3 : CU_ASSERT(ns[1].ana_group_id == 2);
3269 : 3 : CU_ASSERT(ns[1].ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE);
3270 : 3 : CU_ASSERT(ns[2].ana_group_id == 1);
3271 : 3 : CU_ASSERT(ns[2].ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE);
3272 : :
3273 [ - + ]: 3 : CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
3274 : :
3275 : 3 : free(ctrlr.ana_log_page);
3276 : 3 : free(ctrlr.copied_ana_desc);
3277 : 3 : }
3278 : :
3279 : : static void
3280 : 3 : test_nvme_ctrlr_ana_resize(void)
3281 : : {
3282 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
3283 : 3 : uint32_t active_ns_list[] = { 1, 2, 3, 4 };
3284 : 3 : struct spdk_nvme_ana_page ana_hdr = {
3285 : : .change_count = 0,
3286 : : .num_ana_group_desc = 1
3287 : : };
3288 : 3 : uint8_t ana_desc_buf[sizeof(struct spdk_nvme_ana_group_descriptor) + 4 * sizeof(uint32_t)] = {};
3289 : 3 : struct spdk_nvme_ana_group_descriptor *ana_desc =
3290 : : (struct spdk_nvme_ana_group_descriptor *)ana_desc_buf;
3291 : : struct spdk_nvme_ns *ns;
3292 : 3 : union spdk_nvme_async_event_completion aer_event = {
3293 : : .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE,
3294 : : .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED
3295 : : };
3296 : 3 : struct spdk_nvme_cpl aer_cpl = {
3297 : : .status.sct = SPDK_NVME_SCT_GENERIC,
3298 : : .status.sc = SPDK_NVME_SC_SUCCESS,
3299 : 3 : .cdw0 = aer_event.raw
3300 : : };
3301 : : uint32_t i;
3302 : :
3303 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
3304 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_add_process(&ctrlr, NULL) == 0);
3305 : :
3306 : 3 : ctrlr.vs.bits.mjr = 1;
3307 : 3 : ctrlr.vs.bits.mnr = 4;
3308 : 3 : ctrlr.vs.bits.ter = 0;
3309 : 3 : ctrlr.cdata.nn = 4096;
3310 : 3 : ctrlr.cdata.cmic.ana_reporting = true;
3311 : 3 : ctrlr.cdata.nanagrpid = 1;
3312 : :
3313 : 3 : ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
3314 : : /* Start with 2 active namespaces */
3315 : 3 : g_active_ns_list = active_ns_list;
3316 : 3 : g_active_ns_list_length = 2;
3317 : 3 : g_ana_hdr = &ana_hdr;
3318 : 3 : g_ana_descs = &ana_desc;
3319 : 3 : ana_desc->ana_group_id = 1;
3320 : 3 : ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE;
3321 : 3 : ana_desc->num_of_nsid = 2;
3322 [ + + ]: 9 : for (i = 0; i < ana_desc->num_of_nsid; ++i) {
3323 : 6 : ana_desc->nsid[i] = i + 1;
3324 : : }
3325 : :
3326 : : /* Bring controller to ready state */
3327 [ + + ]: 45 : while (ctrlr.state != NVME_CTRLR_STATE_READY) {
3328 [ - + ]: 42 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
3329 : : }
3330 : :
3331 [ + + ]: 9 : for (i = 0; i < ana_desc->num_of_nsid; ++i) {
3332 : 6 : ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1);
3333 : 6 : CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE);
3334 : : }
3335 : :
3336 : : /* Add more namespaces */
3337 : 3 : g_active_ns_list_length = 4;
3338 : 3 : nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
3339 : 3 : nvme_ctrlr_complete_queued_async_events(&ctrlr);
3340 : :
3341 : : /* Update ANA log with new namespaces */
3342 : 3 : ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE;
3343 : 3 : ana_desc->num_of_nsid = 4;
3344 [ + + ]: 15 : for (i = 0; i < ana_desc->num_of_nsid; ++i) {
3345 : 12 : ana_desc->nsid[i] = i + 1;
3346 : : }
3347 : 3 : aer_event.bits.async_event_info = SPDK_NVME_ASYNC_EVENT_ANA_CHANGE;
3348 : 3 : aer_cpl.cdw0 = aer_event.raw;
3349 : 3 : nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
3350 : 3 : nvme_ctrlr_complete_queued_async_events(&ctrlr);
3351 : :
3352 [ + + ]: 15 : for (i = 0; i < ana_desc->num_of_nsid; ++i) {
3353 : 12 : ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1);
3354 : 12 : CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE);
3355 : : }
3356 : :
3357 : 3 : g_active_ns_list = NULL;
3358 : 3 : g_active_ns_list_length = 0;
3359 : 3 : g_ana_hdr = NULL;
3360 : 3 : g_ana_descs = NULL;
3361 : 3 : nvme_ctrlr_free_processes(&ctrlr);
3362 : 3 : nvme_ctrlr_destruct(&ctrlr);
3363 : 3 : }
3364 : :
3365 : : static void
3366 : 3 : test_nvme_ctrlr_get_memory_domains(void)
3367 : : {
3368 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
3369 : :
3370 : 3 : MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 1);
3371 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 1);
3372 : :
3373 : 3 : MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 0);
3374 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 0);
3375 : :
3376 [ - - - + ]: 3 : MOCK_CLEAR(nvme_transport_ctrlr_get_memory_domains);
3377 : 3 : }
3378 : :
3379 : : static void
3380 : 3 : test_nvme_transport_ctrlr_ready(void)
3381 : : {
3382 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
3383 : :
3384 : : /* Transport init succeeded */
3385 : 3 : ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
3386 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
3387 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
3388 : :
3389 : : /* Transport init failed */
3390 : 3 : ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
3391 : 3 : MOCK_SET(nvme_transport_ctrlr_ready, -1);
3392 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == -1);
3393 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
3394 [ - - - + ]: 3 : MOCK_CLEAR(nvme_transport_ctrlr_ready);
3395 : 3 : }
3396 : :
3397 : : static void
3398 : 3 : test_nvme_ctrlr_disable(void)
3399 : : {
3400 [ + - ]: 3 : DECLARE_AND_CONSTRUCT_CTRLR();
3401 : : int rc;
3402 : :
3403 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
3404 : :
3405 : 3 : ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
3406 [ - + ]: 3 : SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
3407 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
3408 : :
3409 : : /* Start a Controller Level Reset. */
3410 : 3 : ctrlr.is_disconnecting = true;
3411 : 3 : nvme_ctrlr_disable(&ctrlr);
3412 : :
3413 : 3 : g_ut_nvme_regs.cc.bits.en = 0;
3414 : :
3415 : 3 : rc = nvme_ctrlr_disable_poll(&ctrlr);
3416 : 3 : CU_ASSERT(rc == -EAGAIN);
3417 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
3418 : :
3419 : 3 : g_ut_nvme_regs.csts.bits.rdy = 0;
3420 : :
3421 : 3 : rc = nvme_ctrlr_disable_poll(&ctrlr);
3422 : 3 : CU_ASSERT(rc == 0);
3423 : 3 : CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
3424 : :
3425 : 3 : g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
3426 : 3 : nvme_ctrlr_destruct(&ctrlr);
3427 : 3 : }
3428 : :
3429 : : static void
3430 : 3 : test_nvme_numa_id(void)
3431 : : {
3432 : 3 : struct spdk_nvme_ctrlr ctrlr = {};
3433 : :
3434 : 3 : ctrlr.numa.id = 3;
3435 : 3 : ctrlr.numa.id_valid = 0;
3436 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_numa_id(&ctrlr) == SPDK_ENV_NUMA_ID_ANY);
3437 : :
3438 : 3 : ctrlr.numa.id_valid = 1;
3439 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_numa_id(&ctrlr) == 3);
3440 : :
3441 : 3 : ctrlr.numa.id = SPDK_ENV_NUMA_ID_ANY;
3442 : 3 : CU_ASSERT(spdk_nvme_ctrlr_get_numa_id(&ctrlr) == SPDK_ENV_NUMA_ID_ANY);
3443 : 3 : }
3444 : :
3445 : : int
3446 : 3 : main(int argc, char **argv)
3447 : : {
3448 : 3 : CU_pSuite suite = NULL;
3449 : : unsigned int num_failures;
3450 : :
3451 : 3 : CU_initialize_registry();
3452 : :
3453 : 3 : suite = CU_add_suite("nvme_ctrlr", NULL, NULL);
3454 : :
3455 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_0);
3456 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_1);
3457 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0);
3458 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_1);
3459 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_rr);
3460 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr);
3461 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_vs);
3462 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_delay);
3463 : 3 : CU_ADD_TEST(suite, test_alloc_io_qpair_rr_1);
3464 : 3 : CU_ADD_TEST(suite, test_ctrlr_get_default_ctrlr_opts);
3465 : 3 : CU_ADD_TEST(suite, test_ctrlr_get_default_io_qpair_opts);
3466 : 3 : CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_1);
3467 : 3 : CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_2);
3468 : 3 : CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_update_firmware);
3469 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_fail);
3470 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_construct_intel_support_log_page_list);
3471 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_features);
3472 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_set_host_feature);
3473 : 3 : CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_doorbell_buffer_config);
3474 : : #if 0 /* TODO: move to PCIe-specific unit test */
3475 : : CU_ADD_TEST(suite, test_nvme_ctrlr_alloc_cmb);
3476 : : #endif
3477 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns);
3478 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns_error_case);
3479 : 3 : CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_reconnect_io_qpair);
3480 : 3 : CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_set_trid);
3481 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_nvmf_ioccsz);
3482 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_num_queues);
3483 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_keep_alive_timeout);
3484 : 3 : CU_ADD_TEST(suite, test_alloc_io_qpair_fail);
3485 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_add_remove_process);
3486 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_set_arbitration_feature);
3487 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_set_state);
3488 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v0);
3489 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v2);
3490 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_ns_mgmt);
3491 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_reset);
3492 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_aer_callback);
3493 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_ns_attr_changed);
3494 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_identify_namespaces_iocs_specific_next);
3495 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_log_pages);
3496 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_set_intel_supported_log_pages);
3497 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_parse_ana_log_page);
3498 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_ana_resize);
3499 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_get_memory_domains);
3500 : 3 : CU_ADD_TEST(suite, test_nvme_transport_ctrlr_ready);
3501 : 3 : CU_ADD_TEST(suite, test_nvme_ctrlr_disable);
3502 : 3 : CU_ADD_TEST(suite, test_nvme_numa_id);
3503 : :
3504 : 3 : num_failures = spdk_ut_run_tests(argc, argv, NULL);
3505 : 3 : CU_cleanup_registry();
3506 : 3 : return num_failures;
3507 : : }
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