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1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (C) 2015 Intel Corporation. All rights reserved.
3 : : * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.
4 : : * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 : : */
6 : :
7 : : #include "spdk/stdinc.h"
8 : :
9 : : #include "nvme_internal.h"
10 : : #include "nvme_io_msg.h"
11 : :
12 : : #include "spdk/env.h"
13 : : #include "spdk/string.h"
14 : : #include "spdk/endian.h"
15 : :
16 : : struct nvme_active_ns_ctx;
17 : :
18 : : static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
19 : : struct nvme_async_event_request *aer);
20 : : static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx);
21 : : static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns);
22 : : static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns);
23 : : static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns);
24 : : static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr);
25 : : static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
26 : : uint64_t timeout_in_ms);
27 : :
28 : : static int
29 : 1930483 : nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2)
30 : : {
31 [ + + ]: 1930483 : if (ns1->id < ns2->id) {
32 : 659786 : return -1;
33 [ + + ]: 1270697 : } else if (ns1->id > ns2->id) {
34 : 1105357 : return 1;
35 : : } else {
36 : 165340 : return 0;
37 : : }
38 : : }
39 : :
40 [ + + + + : 2472363 : RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp);
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41 : :
42 : : #define CTRLR_STRING(ctrlr) \
43 : : ((ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP || ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA) ? \
44 : : ctrlr->trid.subnqn : ctrlr->trid.traddr)
45 : :
46 : : #define NVME_CTRLR_ERRLOG(ctrlr, format, ...) \
47 : : SPDK_ERRLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
48 : :
49 : : #define NVME_CTRLR_WARNLOG(ctrlr, format, ...) \
50 : : SPDK_WARNLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
51 : :
52 : : #define NVME_CTRLR_NOTICELOG(ctrlr, format, ...) \
53 : : SPDK_NOTICELOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
54 : :
55 : : #define NVME_CTRLR_INFOLOG(ctrlr, format, ...) \
56 : : SPDK_INFOLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
57 : :
58 : : #ifdef DEBUG
59 : : #define NVME_CTRLR_DEBUGLOG(ctrlr, format, ...) \
60 : : SPDK_DEBUGLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
61 : : #else
62 : : #define NVME_CTRLR_DEBUGLOG(ctrlr, ...) do { } while (0)
63 : : #endif
64 : :
65 : : #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \
66 : : nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \
67 : : offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg)
68 : :
69 : : #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \
70 : : nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \
71 : : offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg)
72 : :
73 : : #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \
74 : : nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg)
75 : :
76 : : #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \
77 : : nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg)
78 : :
79 : : #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \
80 : : nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg)
81 : :
82 : : #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \
83 : : nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg)
84 : :
85 : : #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \
86 : : nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg)
87 : :
88 : : static int
89 : 0 : nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
90 : : {
91 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
92 : : &cc->raw);
93 : : }
94 : :
95 : : static int
96 : 20434 : nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
97 : : {
98 : 20434 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
99 : : &csts->raw);
100 : : }
101 : :
102 : : int
103 : 578 : nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
104 : : {
105 : 578 : return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
106 : : &cap->raw);
107 : : }
108 : :
109 : : int
110 : 4 : nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
111 : : {
112 : 4 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
113 : : &vs->raw);
114 : : }
115 : :
116 : : int
117 : 8 : nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz)
118 : : {
119 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
120 : : &cmbsz->raw);
121 : : }
122 : :
123 : : int
124 : 8 : nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap)
125 : : {
126 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
127 : : &pmrcap->raw);
128 : : }
129 : :
130 : : int
131 : 0 : nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo)
132 : : {
133 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw),
134 : : &bpinfo->raw);
135 : : }
136 : :
137 : : int
138 : 0 : nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel)
139 : : {
140 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw),
141 : : bprsel->raw);
142 : : }
143 : :
144 : : int
145 : 0 : nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value)
146 : : {
147 : 0 : return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl),
148 : : bpmbl_value);
149 : : }
150 : :
151 : : static int
152 : 0 : nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
153 : : {
154 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr),
155 : : nssr_value);
156 : : }
157 : :
158 : : bool
159 : 4371 : nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr)
160 : : {
161 [ + + ]: 6013 : return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS &&
162 [ + + ]: 1642 : ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS;
163 : : }
164 : :
165 : : /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please
166 : : * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c
167 : : */
168 : : void
169 : 3726 : spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size)
170 : : {
171 : 551 : char host_id_str[SPDK_UUID_STRING_LEN];
172 : :
173 [ - + ]: 3726 : assert(opts);
174 : :
175 : 3726 : opts->opts_size = opts_size;
176 : :
177 : : #define FIELD_OK(field) \
178 : : offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size
179 : :
180 : : #define SET_FIELD(field, value) \
181 : : if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \
182 : : opts->field = value; \
183 : : } \
184 : :
185 [ + - ]: 3726 : SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES);
186 [ + - ]: 3726 : SET_FIELD(use_cmb_sqs, false);
187 [ + - ]: 3726 : SET_FIELD(no_shn_notification, false);
188 [ + + ]: 3726 : SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR);
189 [ + + ]: 3726 : SET_FIELD(arbitration_burst, 0);
190 [ + + ]: 3726 : SET_FIELD(low_priority_weight, 0);
191 [ + + ]: 3726 : SET_FIELD(medium_priority_weight, 0);
192 [ + + ]: 3726 : SET_FIELD(high_priority_weight, 0);
193 [ + + ]: 3726 : SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS);
194 [ + + ]: 3726 : SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT);
195 [ + + ]: 3726 : SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE);
196 : :
197 [ + - ]: 3726 : if (nvme_driver_init() == 0) {
198 [ + + ]: 3726 : if (FIELD_OK(hostnqn)) {
199 : 3722 : spdk_uuid_fmt_lower(host_id_str, sizeof(host_id_str),
200 : 3722 : &g_spdk_nvme_driver->default_extended_host_id);
201 [ - + ]: 3722 : snprintf(opts->hostnqn, sizeof(opts->hostnqn),
202 : : "nqn.2014-08.org.nvmexpress:uuid:%s", host_id_str);
203 : : }
204 : :
205 [ + + ]: 3726 : if (FIELD_OK(extended_host_id)) {
206 : 3722 : memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
207 : : sizeof(opts->extended_host_id));
208 : : }
209 : :
210 : : }
211 : :
212 [ + + ]: 3726 : SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
213 : :
214 [ + + ]: 3726 : if (FIELD_OK(src_addr)) {
215 [ - + ]: 3722 : memset(opts->src_addr, 0, sizeof(opts->src_addr));
216 : : }
217 : :
218 [ + + ]: 3726 : if (FIELD_OK(src_svcid)) {
219 [ - + ]: 3722 : memset(opts->src_svcid, 0, sizeof(opts->src_svcid));
220 : : }
221 : :
222 [ + + ]: 3726 : if (FIELD_OK(host_id)) {
223 [ - + ]: 3722 : memset(opts->host_id, 0, sizeof(opts->host_id));
224 : : }
225 : :
226 [ + + ]: 3726 : SET_FIELD(command_set, CHAR_BIT);
227 [ + + ]: 3726 : SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
228 [ + + ]: 3726 : SET_FIELD(header_digest, false);
229 [ + + ]: 3726 : SET_FIELD(data_digest, false);
230 [ + + ]: 3726 : SET_FIELD(disable_error_logging, false);
231 [ + + ]: 3726 : SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT);
232 [ + + ]: 3726 : SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE);
233 [ + + ]: 3726 : SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT);
234 [ + + ]: 3726 : SET_FIELD(disable_read_ana_log_page, false);
235 [ + + ]: 3726 : SET_FIELD(disable_read_changed_ns_list_log_page, false);
236 [ + + ]: 3726 : SET_FIELD(tls_psk, NULL);
237 [ + + ]: 3726 : SET_FIELD(dhchap_key, NULL);
238 [ + + ]: 3726 : SET_FIELD(dhchap_ctrlr_key, NULL);
239 [ + + ]: 3726 : SET_FIELD(dhchap_digests,
240 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA256) |
241 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA384) |
242 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA512));
243 [ + + ]: 3726 : SET_FIELD(dhchap_dhgroups,
244 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_NULL) |
245 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_2048) |
246 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_3072) |
247 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_4096) |
248 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_6144) |
249 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_8192));
250 : :
251 [ + + ]: 3726 : if (FIELD_OK(psk)) {
252 [ - + ]: 3722 : memset(opts->psk, 0, sizeof(opts->psk));
253 : : }
254 : :
255 : : #undef FIELD_OK
256 : : #undef SET_FIELD
257 : 3726 : }
258 : :
259 : : const struct spdk_nvme_ctrlr_opts *
260 : 2092 : spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr)
261 : : {
262 : 2092 : return &ctrlr->opts;
263 : : }
264 : :
265 : : /**
266 : : * This function will be called when the process allocates the IO qpair.
267 : : * Note: the ctrlr_lock must be held when calling this function.
268 : : */
269 : : static void
270 : 4263 : nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair)
271 : : {
272 : : struct spdk_nvme_ctrlr_process *active_proc;
273 : 4263 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
274 : :
275 : 4263 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
276 [ + + ]: 4263 : if (active_proc) {
277 : 4203 : TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq);
278 : 4203 : qpair->active_proc = active_proc;
279 : : }
280 : 4263 : }
281 : :
282 : : /**
283 : : * This function will be called when the process frees the IO qpair.
284 : : * Note: the ctrlr_lock must be held when calling this function.
285 : : */
286 : : static void
287 : 4263 : nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair)
288 : : {
289 : : struct spdk_nvme_ctrlr_process *active_proc;
290 : 4263 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
291 : : struct spdk_nvme_qpair *active_qpair, *tmp_qpair;
292 : :
293 : 4263 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
294 [ + + ]: 4263 : if (!active_proc) {
295 : 60 : return;
296 : : }
297 : :
298 [ + - ]: 4451 : TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs,
299 : : per_process_tailq, tmp_qpair) {
300 [ + + ]: 4451 : if (active_qpair == qpair) {
301 [ + + ]: 4203 : TAILQ_REMOVE(&active_proc->allocated_io_qpairs,
302 : : active_qpair, per_process_tailq);
303 : :
304 : 4203 : break;
305 : : }
306 : : }
307 : : }
308 : :
309 : : void
310 : 6530 : spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr,
311 : : struct spdk_nvme_io_qpair_opts *opts,
312 : : size_t opts_size)
313 : : {
314 [ - + ]: 6530 : assert(ctrlr);
315 : :
316 [ - + ]: 6530 : assert(opts);
317 : :
318 [ - + ]: 6530 : memset(opts, 0, opts_size);
319 : :
320 : : #define FIELD_OK(field) \
321 : : offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size
322 : :
323 [ + - ]: 6530 : if (FIELD_OK(qprio)) {
324 : 6530 : opts->qprio = SPDK_NVME_QPRIO_URGENT;
325 : : }
326 : :
327 [ + - ]: 6530 : if (FIELD_OK(io_queue_size)) {
328 : 6530 : opts->io_queue_size = ctrlr->opts.io_queue_size;
329 : : }
330 : :
331 [ + + ]: 6530 : if (FIELD_OK(io_queue_requests)) {
332 : 6526 : opts->io_queue_requests = ctrlr->opts.io_queue_requests;
333 : : }
334 : :
335 [ + + ]: 6530 : if (FIELD_OK(delay_cmd_submit)) {
336 : 6526 : opts->delay_cmd_submit = false;
337 : : }
338 : :
339 [ + + ]: 6530 : if (FIELD_OK(sq.vaddr)) {
340 : 6526 : opts->sq.vaddr = NULL;
341 : : }
342 : :
343 [ + + ]: 6530 : if (FIELD_OK(sq.paddr)) {
344 : 6526 : opts->sq.paddr = 0;
345 : : }
346 : :
347 [ + + ]: 6530 : if (FIELD_OK(sq.buffer_size)) {
348 : 6526 : opts->sq.buffer_size = 0;
349 : : }
350 : :
351 [ + + ]: 6530 : if (FIELD_OK(cq.vaddr)) {
352 : 6526 : opts->cq.vaddr = NULL;
353 : : }
354 : :
355 [ + + ]: 6530 : if (FIELD_OK(cq.paddr)) {
356 : 6526 : opts->cq.paddr = 0;
357 : : }
358 : :
359 [ + + ]: 6530 : if (FIELD_OK(cq.buffer_size)) {
360 : 6526 : opts->cq.buffer_size = 0;
361 : : }
362 : :
363 [ + + ]: 6530 : if (FIELD_OK(create_only)) {
364 : 6526 : opts->create_only = false;
365 : : }
366 : :
367 [ + + ]: 6530 : if (FIELD_OK(async_mode)) {
368 : 6526 : opts->async_mode = false;
369 : : }
370 : :
371 : : #undef FIELD_OK
372 : 6530 : }
373 : :
374 : : static struct spdk_nvme_qpair *
375 : 4292 : nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
376 : : const struct spdk_nvme_io_qpair_opts *opts)
377 : : {
378 : : int32_t qid;
379 : : struct spdk_nvme_qpair *qpair;
380 : : union spdk_nvme_cc_register cc;
381 : :
382 [ - + ]: 4292 : if (!ctrlr) {
383 : 0 : return NULL;
384 : : }
385 : :
386 : 4292 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
387 : 4292 : cc.raw = ctrlr->process_init_cc.raw;
388 : :
389 [ + + ]: 4292 : if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) {
390 : 8 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
391 : 8 : return NULL;
392 : : }
393 : :
394 : : /*
395 : : * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
396 : : * default round robin arbitration method.
397 : : */
398 [ + + + + ]: 4284 : if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) {
399 [ + - - + ]: 12 : NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n");
400 : 12 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
401 : 12 : return NULL;
402 : : }
403 : :
404 : 4272 : qid = spdk_nvme_ctrlr_alloc_qid(ctrlr);
405 [ + + ]: 4272 : if (qid < 0) {
406 : 9 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
407 : 9 : return NULL;
408 : : }
409 : :
410 : 4263 : qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts);
411 [ - + ]: 4263 : if (qpair == NULL) {
412 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n");
413 : 0 : spdk_nvme_ctrlr_free_qid(ctrlr, qid);
414 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
415 : 0 : return NULL;
416 : : }
417 : :
418 : 4263 : TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
419 : :
420 : 4263 : nvme_ctrlr_proc_add_io_qpair(qpair);
421 : :
422 : 4263 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
423 : :
424 : 4263 : return qpair;
425 : : }
426 : :
427 : : int
428 : 4263 : spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
429 : : {
430 : : int rc;
431 : :
432 [ - + ]: 4263 : if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) {
433 : 0 : return -EISCONN;
434 : : }
435 : :
436 : 4263 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
437 : 4263 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
438 : 4263 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
439 : :
440 [ - + ]: 4263 : if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
441 : 0 : spdk_delay_us(100);
442 : : }
443 : :
444 : 4263 : return rc;
445 : : }
446 : :
447 : : void
448 : 1790 : spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair)
449 : : {
450 : 1790 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
451 : :
452 : 1790 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
453 : 1790 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
454 : 1790 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
455 : 1790 : }
456 : :
457 : : struct spdk_nvme_qpair *
458 : 4296 : spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
459 : : const struct spdk_nvme_io_qpair_opts *user_opts,
460 : : size_t opts_size)
461 : : {
462 : :
463 : 4296 : struct spdk_nvme_qpair *qpair = NULL;
464 : 597 : struct spdk_nvme_io_qpair_opts opts;
465 : : int rc;
466 : :
467 : 4296 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
468 : :
469 [ + + ]: 4296 : if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) {
470 : : /* When controller is resetting or initializing, free_io_qids is deleted or not created yet.
471 : : * We can't create IO qpair in that case */
472 : 4 : goto unlock;
473 : : }
474 : :
475 : : /*
476 : : * Get the default options, then overwrite them with the user-provided options
477 : : * up to opts_size.
478 : : *
479 : : * This allows for extensions of the opts structure without breaking
480 : : * ABI compatibility.
481 : : */
482 : 4292 : spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts));
483 [ + + ]: 4292 : if (user_opts) {
484 [ - + ]: 2303 : memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size));
485 : :
486 : : /* If user passes buffers, make sure they're big enough for the requested queue size */
487 [ - + ]: 2303 : if (opts.sq.vaddr) {
488 [ # # ]: 0 : if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) {
489 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n",
490 : : opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd)));
491 : 0 : goto unlock;
492 : : }
493 : : }
494 [ - + ]: 2303 : if (opts.cq.vaddr) {
495 [ # # ]: 0 : if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) {
496 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n",
497 : : opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl)));
498 : 0 : goto unlock;
499 : : }
500 : : }
501 : : }
502 : :
503 : 4292 : qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts);
504 : :
505 [ + + + + : 4292 : if (qpair == NULL || opts.create_only == true) {
+ + ]
506 : 2016 : goto unlock;
507 : : }
508 : :
509 : 2276 : rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair);
510 [ + + ]: 2276 : if (rc != 0) {
511 [ + - - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n");
512 : 4 : nvme_ctrlr_proc_remove_io_qpair(qpair);
513 [ - + ]: 4 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
514 : 4 : spdk_bit_array_set(ctrlr->free_io_qids, qpair->id);
515 : 4 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
516 : 4 : qpair = NULL;
517 : 4 : goto unlock;
518 : : }
519 : :
520 : 2762 : unlock:
521 : 4296 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
522 : :
523 : 4296 : return qpair;
524 : : }
525 : :
526 : : int
527 : 2477197 : spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair)
528 : : {
529 : : struct spdk_nvme_ctrlr *ctrlr;
530 : : enum nvme_qpair_state qpair_state;
531 : : int rc;
532 : :
533 [ - + ]: 2477197 : assert(qpair != NULL);
534 [ - + ]: 2477197 : assert(nvme_qpair_is_admin_queue(qpair) == false);
535 [ - + ]: 2477197 : assert(qpair->ctrlr != NULL);
536 : :
537 : 2477197 : ctrlr = qpair->ctrlr;
538 : 2477197 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
539 : 2477197 : qpair_state = nvme_qpair_get_state(qpair);
540 : :
541 [ + + + + ]: 2477197 : if (ctrlr->is_removed) {
542 : 8 : rc = -ENODEV;
543 : 8 : goto out;
544 : : }
545 : :
546 [ + + + + : 2477189 : if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) {
- + ]
547 : 11 : rc = -EAGAIN;
548 : 11 : goto out;
549 : : }
550 : :
551 [ + + + + : 2477178 : if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) {
- + ]
552 : 2461999 : rc = -ENXIO;
553 : 2461999 : goto out;
554 : : }
555 : :
556 [ + + ]: 15179 : if (qpair_state != NVME_QPAIR_DISCONNECTED) {
557 : 4 : rc = 0;
558 : 4 : goto out;
559 : : }
560 : :
561 : 15175 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
562 [ + + ]: 15175 : if (rc) {
563 : 15163 : rc = -EAGAIN;
564 : 15163 : goto out;
565 : : }
566 : :
567 : 12 : out:
568 : 2477197 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
569 : 2477197 : return rc;
570 : : }
571 : :
572 : : spdk_nvme_qp_failure_reason
573 : 692837 : spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr)
574 : : {
575 : 692837 : return ctrlr->adminq->transport_failure_reason;
576 : : }
577 : :
578 : : /*
579 : : * This internal function will attempt to take the controller
580 : : * lock before calling disconnect on a controller qpair.
581 : : * Functions already holding the controller lock should
582 : : * call nvme_transport_ctrlr_disconnect_qpair directly.
583 : : */
584 : : void
585 : 23204 : nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair)
586 : : {
587 : 23204 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
588 : :
589 [ - + ]: 23204 : assert(ctrlr != NULL);
590 : 23204 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
591 : 23204 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
592 : 23204 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
593 : 23204 : }
594 : :
595 : : int
596 : 4259 : spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
597 : : {
598 : : struct spdk_nvme_ctrlr *ctrlr;
599 : :
600 [ - + ]: 4259 : if (qpair == NULL) {
601 : 0 : return 0;
602 : : }
603 : :
604 : 4259 : ctrlr = qpair->ctrlr;
605 : :
606 [ - + ]: 4259 : if (qpair->in_completion_context) {
607 : : /*
608 : : * There are many cases where it is convenient to delete an io qpair in the context
609 : : * of that qpair's completion routine. To handle this properly, set a flag here
610 : : * so that the completion routine will perform an actual delete after the context
611 : : * unwinds.
612 : : */
613 : 0 : qpair->delete_after_completion_context = 1;
614 : 0 : return 0;
615 : : }
616 : :
617 : 4259 : qpair->destroy_in_progress = 1;
618 : :
619 : 4259 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
620 : :
621 [ + + + - ]: 4259 : if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) {
622 : 1987 : spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair);
623 : : }
624 : :
625 : : /* Do not retry. */
626 : 4259 : nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING);
627 : :
628 : : /* In the multi-process case, a process may call this function on a foreign
629 : : * I/O qpair (i.e. one that this process did not create) when that qpairs process
630 : : * exits unexpectedly. In that case, we must not try to abort any reqs associated
631 : : * with that qpair, since the callbacks will also be foreign to this process.
632 : : */
633 [ + - ]: 4259 : if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) {
634 : 4259 : nvme_qpair_abort_all_queued_reqs(qpair);
635 : : }
636 : :
637 : 4259 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
638 : :
639 : 4259 : nvme_ctrlr_proc_remove_io_qpair(qpair);
640 : :
641 [ + + ]: 4259 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
642 : 4259 : spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id);
643 : :
644 : 4259 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
645 : 4259 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
646 : 4259 : return 0;
647 : : }
648 : :
649 : : static void
650 : 106 : nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
651 : : struct spdk_nvme_intel_log_page_directory *log_page_directory)
652 : : {
653 [ - + ]: 106 : if (log_page_directory == NULL) {
654 : 0 : return;
655 : : }
656 : :
657 [ - + ]: 106 : assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL);
658 : :
659 : 106 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
660 : :
661 [ + + ]: 106 : if (log_page_directory->read_latency_log_len ||
662 [ + + ]: 8 : (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) {
663 : 102 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
664 : : }
665 [ + + ]: 106 : if (log_page_directory->write_latency_log_len ||
666 [ + + ]: 8 : (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) {
667 : 102 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
668 : : }
669 [ + + ]: 106 : if (log_page_directory->temperature_statistics_log_len) {
670 : 102 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
671 : : }
672 [ + + ]: 106 : if (log_page_directory->smart_log_len) {
673 : 98 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
674 : : }
675 [ + + ]: 106 : if (log_page_directory->marketing_description_log_len) {
676 : 98 : ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
677 : : }
678 : : }
679 : :
680 : : struct intel_log_pages_ctx {
681 : : struct spdk_nvme_intel_log_page_directory log_page_directory;
682 : : struct spdk_nvme_ctrlr *ctrlr;
683 : : };
684 : :
685 : : static void
686 : 98 : nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl)
687 : : {
688 : 98 : struct intel_log_pages_ctx *ctx = arg;
689 : 98 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
690 : :
691 [ + - + - ]: 98 : if (!spdk_nvme_cpl_is_error(cpl)) {
692 : 98 : nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory);
693 : : }
694 : :
695 : 98 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
696 : 98 : ctrlr->opts.admin_timeout_ms);
697 : 98 : free(ctx);
698 : 98 : }
699 : :
700 : : static int
701 : 98 : nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
702 : : {
703 : 98 : int rc = 0;
704 : : struct intel_log_pages_ctx *ctx;
705 : :
706 : 98 : ctx = calloc(1, sizeof(*ctx));
707 [ - + ]: 98 : if (!ctx) {
708 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
709 : 0 : ctrlr->opts.admin_timeout_ms);
710 : 0 : return 0;
711 : : }
712 : :
713 : 98 : ctx->ctrlr = ctrlr;
714 : :
715 : 98 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY,
716 : 98 : SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory,
717 : : sizeof(struct spdk_nvme_intel_log_page_directory),
718 : : 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx);
719 [ - + ]: 98 : if (rc != 0) {
720 : 0 : free(ctx);
721 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
722 : 0 : ctrlr->opts.admin_timeout_ms);
723 : 0 : return 0;
724 : : }
725 : :
726 : 98 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES,
727 : 98 : ctrlr->opts.admin_timeout_ms);
728 : :
729 : 98 : return 0;
730 : : }
731 : :
732 : : static int
733 : 29 : nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
734 : : {
735 : : uint32_t ana_log_page_size;
736 : :
737 : 29 : ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid *
738 : 29 : sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count *
739 : : sizeof(uint32_t);
740 : :
741 : : /* Number of active namespaces may have changed.
742 : : * Check if ANA log page fits into existing buffer.
743 : : */
744 [ + - ]: 29 : if (ana_log_page_size > ctrlr->ana_log_page_size) {
745 : : void *new_buffer;
746 : :
747 [ + + ]: 29 : if (ctrlr->ana_log_page) {
748 : 4 : new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size);
749 : : } else {
750 : 25 : new_buffer = calloc(1, ana_log_page_size);
751 : : }
752 : :
753 [ - + ]: 29 : if (!new_buffer) {
754 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n",
755 : : ana_log_page_size);
756 : 0 : return -ENXIO;
757 : : }
758 : :
759 : 29 : ctrlr->ana_log_page = new_buffer;
760 [ + + ]: 29 : if (ctrlr->copied_ana_desc) {
761 : 4 : new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size);
762 : : } else {
763 : 25 : new_buffer = calloc(1, ana_log_page_size);
764 : : }
765 : :
766 [ - + ]: 29 : if (!new_buffer) {
767 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n",
768 : : ana_log_page_size);
769 : 0 : return -ENOMEM;
770 : : }
771 : :
772 : 29 : ctrlr->copied_ana_desc = new_buffer;
773 : 29 : ctrlr->ana_log_page_size = ana_log_page_size;
774 : : }
775 : :
776 : 29 : return 0;
777 : : }
778 : :
779 : : static int
780 : 29 : nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
781 : : {
782 : : struct nvme_completion_poll_status *status;
783 : : int rc;
784 : :
785 : 29 : rc = nvme_ctrlr_alloc_ana_log_page(ctrlr);
786 [ - + ]: 29 : if (rc != 0) {
787 : 0 : return rc;
788 : : }
789 : :
790 : 29 : status = calloc(1, sizeof(*status));
791 [ - + ]: 29 : if (status == NULL) {
792 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
793 : 0 : return -ENOMEM;
794 : : }
795 : :
796 : 29 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS,
797 : 29 : SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page,
798 : : ctrlr->ana_log_page_size, 0,
799 : : nvme_completion_poll_cb, status);
800 [ - + ]: 29 : if (rc != 0) {
801 : 0 : free(status);
802 : 0 : return rc;
803 : : }
804 : :
805 [ - + ]: 29 : if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock,
806 : 29 : ctrlr->opts.admin_timeout_ms * 1000)) {
807 [ # # # # ]: 0 : if (!status->timed_out) {
808 : 0 : free(status);
809 : : }
810 : 0 : return -EIO;
811 : : }
812 : :
813 : 29 : free(status);
814 : 29 : return 0;
815 : : }
816 : :
817 : : static int
818 : 33 : nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc,
819 : : void *cb_arg)
820 : : {
821 : 33 : struct spdk_nvme_ctrlr *ctrlr = cb_arg;
822 : : struct spdk_nvme_ns *ns;
823 : : uint32_t i, nsid;
824 : :
825 [ + + ]: 82 : for (i = 0; i < desc->num_of_nsid; i++) {
826 : 49 : nsid = desc->nsid[i];
827 [ + - - + ]: 49 : if (nsid == 0 || nsid > ctrlr->cdata.nn) {
828 : 0 : continue;
829 : : }
830 : :
831 : 49 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
832 [ - + ]: 49 : assert(ns != NULL);
833 : :
834 : 49 : ns->ana_group_id = desc->ana_group_id;
835 : 49 : ns->ana_state = desc->ana_state;
836 : : }
837 : :
838 : 33 : return 0;
839 : : }
840 : :
841 : : int
842 : 29 : nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr,
843 : : spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg)
844 : : {
845 : : struct spdk_nvme_ana_group_descriptor *copied_desc;
846 : : uint8_t *orig_desc;
847 : : uint32_t i, desc_size, copy_len;
848 : 29 : int rc = 0;
849 : :
850 [ - + ]: 29 : if (ctrlr->ana_log_page == NULL) {
851 : 0 : return -EINVAL;
852 : : }
853 : :
854 : 29 : copied_desc = ctrlr->copied_ana_desc;
855 : :
856 : 29 : orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page);
857 : 29 : copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page);
858 : :
859 [ + + ]: 62 : for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) {
860 [ - + - + ]: 33 : memcpy(copied_desc, orig_desc, copy_len);
861 : :
862 : 33 : rc = cb_fn(copied_desc, cb_arg);
863 [ - + ]: 33 : if (rc != 0) {
864 : 0 : break;
865 : : }
866 : :
867 : 33 : desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) +
868 : 33 : copied_desc->num_of_nsid * sizeof(uint32_t);
869 : 33 : orig_desc += desc_size;
870 : 33 : copy_len -= desc_size;
871 : : }
872 : :
873 : 29 : return rc;
874 : : }
875 : :
876 : : static int
877 : 2106 : nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
878 : : {
879 : 2106 : int rc = 0;
880 : :
881 [ - + ]: 2106 : memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
882 : : /* Mandatory pages */
883 : 2106 : ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
884 : 2106 : ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
885 : 2106 : ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
886 [ + + ]: 2106 : if (ctrlr->cdata.lpa.celp) {
887 : 2046 : ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
888 : : }
889 : :
890 [ + + ]: 2106 : if (ctrlr->cdata.cmic.ana_reporting) {
891 : 339 : ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true;
892 [ + + + + ]: 339 : if (!ctrlr->opts.disable_read_ana_log_page) {
893 : 21 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
894 [ + - ]: 21 : if (rc == 0) {
895 : 21 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
896 : : ctrlr);
897 : : }
898 : : }
899 : : }
900 : :
901 [ - + ]: 2106 : if (ctrlr->cdata.ctratt.bits.fdps) {
902 : 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true;
903 : 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true;
904 : 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true;
905 : 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true;
906 : : }
907 : :
908 [ + + ]: 2106 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL &&
909 [ + + ]: 1183 : ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE &&
910 [ + - ]: 98 : !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) {
911 : 98 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES,
912 : 98 : ctrlr->opts.admin_timeout_ms);
913 : :
914 : : } else {
915 : 2008 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
916 : 2008 : ctrlr->opts.admin_timeout_ms);
917 : :
918 : : }
919 : :
920 : 2106 : return rc;
921 : : }
922 : :
923 : : static void
924 : 1183 : nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
925 : : {
926 : 1183 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
927 : 1183 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
928 : 1183 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
929 : 1183 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
930 : 1183 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
931 : 1183 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
932 : 1183 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
933 : 1183 : }
934 : :
935 : : static void
936 : 2114 : nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr)
937 : : {
938 : : uint32_t cdw11;
939 : : struct nvme_completion_poll_status *status;
940 : :
941 [ + + ]: 2114 : if (ctrlr->opts.arbitration_burst == 0) {
942 : 2106 : return;
943 : : }
944 : :
945 [ + + ]: 8 : if (ctrlr->opts.arbitration_burst > 7) {
946 [ + - - + ]: 4 : NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n");
947 : 4 : return;
948 : : }
949 : :
950 : 4 : status = calloc(1, sizeof(*status));
951 [ - + ]: 4 : if (!status) {
952 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
953 : 0 : return;
954 : : }
955 : :
956 : 4 : cdw11 = ctrlr->opts.arbitration_burst;
957 : :
958 [ + - ]: 4 : if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) {
959 : 4 : cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8;
960 : 4 : cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16;
961 : 4 : cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24;
962 : : }
963 : :
964 [ - + ]: 4 : if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION,
965 : : cdw11, 0, NULL, 0,
966 : : nvme_completion_poll_cb, status) < 0) {
967 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n");
968 : 0 : free(status);
969 : 0 : return;
970 : : }
971 : :
972 [ - + ]: 4 : if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
973 : 4 : ctrlr->opts.admin_timeout_ms * 1000)) {
974 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n");
975 : : }
976 : :
977 [ + + + - ]: 4 : if (!status->timed_out) {
978 : 4 : free(status);
979 : : }
980 : : }
981 : :
982 : : static void
983 : 2106 : nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
984 : : {
985 [ - + ]: 2106 : memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
986 : : /* Mandatory features */
987 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
988 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
989 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
990 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
991 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
992 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
993 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
994 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
995 : 2106 : ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
996 : : /* Optional features */
997 [ + + ]: 2106 : if (ctrlr->cdata.vwc.present) {
998 : 1937 : ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
999 : : }
1000 [ - + ]: 2106 : if (ctrlr->cdata.apsta.supported) {
1001 : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
1002 : : }
1003 [ - + ]: 2106 : if (ctrlr->cdata.hmpre) {
1004 : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
1005 : : }
1006 [ + + ]: 2106 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
1007 : 1183 : nvme_ctrlr_set_intel_supported_features(ctrlr);
1008 : : }
1009 : :
1010 : 2106 : nvme_ctrlr_set_arbitration_feature(ctrlr);
1011 : 2106 : }
1012 : :
1013 : : bool
1014 : 71897 : spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr)
1015 : : {
1016 [ - + ]: 71897 : return ctrlr->is_failed;
1017 : : }
1018 : :
1019 : : void
1020 : 567 : nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
1021 : : {
1022 : : /*
1023 : : * Set the flag here and leave the work failure of qpairs to
1024 : : * spdk_nvme_qpair_process_completions().
1025 : : */
1026 [ + + ]: 567 : if (hot_remove) {
1027 : 57 : ctrlr->is_removed = true;
1028 : : }
1029 : :
1030 [ - + + + ]: 567 : if (ctrlr->is_failed) {
1031 [ + + + + ]: 55 : NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n");
1032 : 55 : return;
1033 : : }
1034 : :
1035 [ - + + + ]: 512 : if (ctrlr->is_disconnecting) {
1036 [ - + - + : 9 : NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n");
- - - - ]
1037 : 9 : return;
1038 : : }
1039 : :
1040 : 503 : ctrlr->is_failed = true;
1041 : 503 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1042 [ + + + + ]: 503 : NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n");
1043 : : }
1044 : :
1045 : : /**
1046 : : * This public API function will try to take the controller lock.
1047 : : * Any private functions being called from a thread already holding
1048 : : * the ctrlr lock should call nvme_ctrlr_fail directly.
1049 : : */
1050 : : void
1051 : 20 : spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
1052 : : {
1053 : 20 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1054 : 20 : nvme_ctrlr_fail(ctrlr, false);
1055 : 20 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1056 : 20 : }
1057 : :
1058 : : static void
1059 : 2094 : nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1060 : : {
1061 : 2094 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1062 : 2094 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1063 : :
1064 [ + - - + ]: 2094 : if (spdk_nvme_cpl_is_error(cpl)) {
1065 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1066 : 0 : ctx->shutdown_complete = true;
1067 : 0 : return;
1068 : : }
1069 : :
1070 [ - + - + ]: 2094 : if (ctrlr->opts.no_shn_notification) {
1071 : 0 : ctx->shutdown_complete = true;
1072 : 0 : return;
1073 : : }
1074 : :
1075 : : /*
1076 : : * The NVMe specification defines RTD3E to be the time between
1077 : : * setting SHN = 1 until the controller will set SHST = 10b.
1078 : : * If the device doesn't report RTD3 entry latency, or if it
1079 : : * reports RTD3 entry latency less than 10 seconds, pick
1080 : : * 10 seconds as a reasonable amount of time to
1081 : : * wait before proceeding.
1082 : : */
1083 [ - + + + : 2094 : NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e);
+ + + + ]
1084 : 2094 : ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000);
1085 : 2094 : ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000);
1086 [ - + + + : 2094 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms);
+ + + + ]
1087 : :
1088 : 2094 : ctx->shutdown_start_tsc = spdk_get_ticks();
1089 : 2094 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1090 : : }
1091 : :
1092 : : static void
1093 : 2094 : nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1094 : : {
1095 : 2094 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1096 : 2094 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1097 : : union spdk_nvme_cc_register cc;
1098 : : int rc;
1099 : :
1100 [ + - - + ]: 2094 : if (spdk_nvme_cpl_is_error(cpl)) {
1101 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1102 : 0 : ctx->shutdown_complete = true;
1103 : 0 : return;
1104 : : }
1105 : :
1106 [ - + ]: 2094 : assert(value <= UINT32_MAX);
1107 : 2094 : cc.raw = (uint32_t)value;
1108 : :
1109 [ - + - + ]: 2094 : if (ctrlr->opts.no_shn_notification) {
1110 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n");
# # # # ]
1111 [ # # ]: 0 : if (cc.bits.en == 0) {
1112 : 0 : ctx->shutdown_complete = true;
1113 : 0 : return;
1114 : : }
1115 : :
1116 : 0 : cc.bits.en = 0;
1117 : : } else {
1118 : 2094 : cc.bits.shn = SPDK_NVME_SHN_NORMAL;
1119 : : }
1120 : :
1121 : 2094 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx);
1122 [ - + ]: 2094 : if (rc != 0) {
1123 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1124 : 0 : ctx->shutdown_complete = true;
1125 : : }
1126 : : }
1127 : :
1128 : : static void
1129 : 2263 : nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr,
1130 : : struct nvme_ctrlr_detach_ctx *ctx)
1131 : : {
1132 : : int rc;
1133 : :
1134 [ + + + + ]: 2263 : if (ctrlr->is_removed) {
1135 : 54 : ctx->shutdown_complete = true;
1136 : 54 : return;
1137 : : }
1138 : :
1139 [ + + ]: 2209 : if (ctrlr->adminq == NULL ||
1140 [ + + ]: 2181 : ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) {
1141 [ - + - + : 112 : NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n");
- - - - ]
1142 : 112 : ctx->shutdown_complete = true;
1143 : 112 : return;
1144 : : }
1145 : :
1146 : 2097 : ctx->state = NVME_CTRLR_DETACH_SET_CC;
1147 : 2097 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx);
1148 [ + + ]: 2097 : if (rc != 0) {
1149 [ - + - - ]: 3 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1150 : 3 : ctx->shutdown_complete = true;
1151 : : }
1152 : : }
1153 : :
1154 : : static void
1155 : 5243460 : nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1156 : : {
1157 : 5243460 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1158 : :
1159 [ + - - + ]: 5243460 : if (spdk_nvme_cpl_is_error(cpl)) {
1160 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n");
1161 : 0 : ctx->shutdown_complete = true;
1162 : 0 : return;
1163 : : }
1164 : :
1165 [ - + ]: 5243460 : assert(value <= UINT32_MAX);
1166 : 5243460 : ctx->csts.raw = (uint32_t)value;
1167 : 5243460 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE;
1168 : : }
1169 : :
1170 : : static int
1171 : 16525247 : nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr,
1172 : : struct nvme_ctrlr_detach_ctx *ctx)
1173 : : {
1174 : : union spdk_nvme_csts_register csts;
1175 : : uint32_t ms_waited;
1176 : :
1177 [ + + + - ]: 16525247 : switch (ctx->state) {
1178 : 6038327 : case NVME_CTRLR_DETACH_SET_CC:
1179 : : case NVME_CTRLR_DETACH_GET_CSTS:
1180 : : /* We're still waiting for the register operation to complete */
1181 : 6038327 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
1182 : 6038327 : return -EAGAIN;
1183 : :
1184 : 5243460 : case NVME_CTRLR_DETACH_CHECK_CSTS:
1185 : 5243460 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS;
1186 [ - + ]: 5243460 : if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) {
1187 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
1188 : 0 : return -EIO;
1189 : : }
1190 : 5243460 : return -EAGAIN;
1191 : :
1192 : 5243460 : case NVME_CTRLR_DETACH_GET_CSTS_DONE:
1193 : 5243460 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1194 : 5243460 : break;
1195 : :
1196 : 0 : default:
1197 : 0 : assert(0 && "Should never happen");
1198 : : return -EINVAL;
1199 : : }
1200 : :
1201 [ - + ]: 5243460 : ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz();
1202 : 5243460 : csts.raw = ctx->csts.raw;
1203 : :
1204 [ + + ]: 5243460 : if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
1205 [ - + + + : 2094 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited);
+ + + + ]
1206 : 2094 : return 0;
1207 : : }
1208 : :
1209 [ + - ]: 5241366 : if (ms_waited < ctx->shutdown_timeout_ms) {
1210 : 5241366 : return -EAGAIN;
1211 : : }
1212 : :
1213 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n",
1214 : : ctx->shutdown_timeout_ms);
1215 [ # # ]: 0 : if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) {
1216 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n");
1217 : : }
1218 : :
1219 : 0 : return 0;
1220 : : }
1221 : :
1222 : : static inline uint64_t
1223 : 4939399 : nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr)
1224 : : {
1225 : 4939399 : return ctrlr->cap.bits.to * 500;
1226 : : }
1227 : :
1228 : : static void
1229 : 2190 : nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1230 : : {
1231 : 2190 : struct spdk_nvme_ctrlr *ctrlr = ctx;
1232 : :
1233 [ + - - + ]: 2190 : if (spdk_nvme_cpl_is_error(cpl)) {
1234 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n");
1235 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1236 : 0 : return;
1237 : : }
1238 : :
1239 : 2190 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
1240 : : nvme_ctrlr_get_ready_timeout(ctrlr));
1241 : : }
1242 : :
1243 : : static int
1244 : 2218 : nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
1245 : : {
1246 : : union spdk_nvme_cc_register cc;
1247 : : int rc;
1248 : :
1249 : 2218 : rc = nvme_transport_ctrlr_enable(ctrlr);
1250 [ - + ]: 2218 : if (rc != 0) {
1251 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n");
1252 : 0 : return rc;
1253 : : }
1254 : :
1255 : 2218 : cc.raw = ctrlr->process_init_cc.raw;
1256 [ - + ]: 2218 : if (cc.bits.en != 0) {
1257 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n");
1258 : 0 : return -EINVAL;
1259 : : }
1260 : :
1261 : 2218 : cc.bits.en = 1;
1262 : 2218 : cc.bits.css = 0;
1263 : 2218 : cc.bits.shn = 0;
1264 : 2218 : cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
1265 : 2218 : cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
1266 : :
1267 : : /* Page size is 2 ^ (12 + mps). */
1268 : 2218 : cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12;
1269 : :
1270 : : /*
1271 : : * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS.
1272 : : * A controller that does not have any bit set in CAP.CSS is not spec compliant.
1273 : : * Try to support such a controller regardless.
1274 : : */
1275 [ + + ]: 2218 : if (ctrlr->cap.bits.css == 0) {
1276 [ - + - + : 84 : NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n");
- - - - ]
1277 : 84 : ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM;
1278 : : }
1279 : :
1280 : : /*
1281 : : * If the user did not explicitly request a command set, or supplied a value larger than
1282 : : * what can be saved in CC.CSS, use the most reasonable default.
1283 : : */
1284 [ + + ]: 2218 : if (ctrlr->opts.command_set >= CHAR_BIT) {
1285 [ + + ]: 2028 : if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) {
1286 : 771 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS;
1287 [ + - ]: 1257 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) {
1288 : 1257 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1289 [ # # ]: 0 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) {
1290 : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NOIO;
1291 : : } else {
1292 : : /* Invalid supported bits detected, falling back to NVM. */
1293 : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1294 : : }
1295 : : }
1296 : :
1297 : : /* Verify that the selected command set is supported by the controller. */
1298 [ - + - + ]: 2218 : if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) {
1299 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n",
# # # # ]
1300 : : ctrlr->opts.command_set, ctrlr->cap.bits.css);
1301 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n");
# # # # ]
1302 : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1303 : : }
1304 : :
1305 : 2218 : cc.bits.css = ctrlr->opts.command_set;
1306 : :
1307 [ + + + + ]: 2218 : switch (ctrlr->opts.arb_mechanism) {
1308 : 2174 : case SPDK_NVME_CC_AMS_RR:
1309 : 2174 : break;
1310 : 16 : case SPDK_NVME_CC_AMS_WRR:
1311 [ + + ]: 16 : if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) {
1312 : 8 : break;
1313 : : }
1314 : 8 : return -EINVAL;
1315 : 16 : case SPDK_NVME_CC_AMS_VS:
1316 [ + + ]: 16 : if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) {
1317 : 8 : break;
1318 : : }
1319 : 8 : return -EINVAL;
1320 : 12 : default:
1321 : 12 : return -EINVAL;
1322 : : }
1323 : :
1324 : 2190 : cc.bits.ams = ctrlr->opts.arb_mechanism;
1325 : 2190 : ctrlr->process_init_cc.raw = cc.raw;
1326 : :
1327 [ - + ]: 2190 : if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) {
1328 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
1329 : 0 : return -EIO;
1330 : : }
1331 : :
1332 : 2190 : return 0;
1333 : : }
1334 : :
1335 : : static const char *
1336 : 304 : nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
1337 : : {
1338 [ - + + + : 304 : switch (state) {
+ + + + +
- - - - +
- + + + +
- + + + +
+ + + + -
- - + + +
+ + + + +
+ - + - -
+ + - + -
+ + + -
- ]
1339 : 0 : case NVME_CTRLR_STATE_INIT_DELAY:
1340 : 0 : return "delay init";
1341 : 10 : case NVME_CTRLR_STATE_CONNECT_ADMINQ:
1342 : 10 : return "connect adminq";
1343 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
1344 : 10 : return "wait for connect adminq";
1345 : 10 : case NVME_CTRLR_STATE_READ_VS:
1346 : 10 : return "read vs";
1347 : 10 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
1348 : 10 : return "read vs wait for vs";
1349 : 10 : case NVME_CTRLR_STATE_READ_CAP:
1350 : 10 : return "read cap";
1351 : 10 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
1352 : 10 : return "read cap wait for cap";
1353 : 10 : case NVME_CTRLR_STATE_CHECK_EN:
1354 : 10 : return "check en";
1355 : 10 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
1356 : 10 : return "check en wait for cc";
1357 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
1358 : 0 : return "disable and wait for CSTS.RDY = 1";
1359 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1360 : 0 : return "disable and wait for CSTS.RDY = 1 reg";
1361 : 0 : case NVME_CTRLR_STATE_SET_EN_0:
1362 : 0 : return "set CC.EN = 0";
1363 : 0 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
1364 : 0 : return "set CC.EN = 0 wait for cc";
1365 : 10 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
1366 : 10 : return "disable and wait for CSTS.RDY = 0";
1367 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
1368 : 0 : return "disable and wait for CSTS.RDY = 0 reg";
1369 : 10 : case NVME_CTRLR_STATE_DISABLED:
1370 : 10 : return "controller is disabled";
1371 : 10 : case NVME_CTRLR_STATE_ENABLE:
1372 : 10 : return "enable controller by writing CC.EN = 1";
1373 : 10 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
1374 : 10 : return "enable controller by writing CC.EN = 1 reg";
1375 : 10 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
1376 : 10 : return "wait for CSTS.RDY = 1";
1377 : 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1378 : 0 : return "wait for CSTS.RDY = 1 reg";
1379 : 10 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
1380 : 10 : return "reset admin queue";
1381 : 10 : case NVME_CTRLR_STATE_IDENTIFY:
1382 : 10 : return "identify controller";
1383 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
1384 : 10 : return "wait for identify controller";
1385 : 10 : case NVME_CTRLR_STATE_CONFIGURE_AER:
1386 : 10 : return "configure AER";
1387 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
1388 : 10 : return "wait for configure aer";
1389 : 10 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
1390 : 10 : return "set keep alive timeout";
1391 : 10 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
1392 : 10 : return "wait for set keep alive timeout";
1393 : 6 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
1394 : 6 : return "identify controller iocs specific";
1395 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
1396 : 0 : return "wait for identify controller iocs specific";
1397 : 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
1398 : 0 : return "get zns cmd and effects log page";
1399 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
1400 : 0 : return "wait for get zns cmd and effects log page";
1401 : 6 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
1402 : 6 : return "set number of queues";
1403 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
1404 : 6 : return "wait for set number of queues";
1405 : 6 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
1406 : 6 : return "identify active ns";
1407 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
1408 : 6 : return "wait for identify active ns";
1409 : 6 : case NVME_CTRLR_STATE_IDENTIFY_NS:
1410 : 6 : return "identify ns";
1411 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
1412 : 6 : return "wait for identify ns";
1413 : 6 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
1414 : 6 : return "identify namespace id descriptors";
1415 : 6 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
1416 : 6 : return "wait for identify namespace id descriptors";
1417 : 6 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
1418 : 6 : return "identify ns iocs specific";
1419 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
1420 : 0 : return "wait for identify ns iocs specific";
1421 : 6 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
1422 : 6 : return "set supported log pages";
1423 : 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
1424 : 0 : return "set supported INTEL log pages";
1425 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
1426 : 0 : return "wait for supported INTEL log pages";
1427 : 6 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
1428 : 6 : return "set supported features";
1429 : 6 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
1430 : 6 : return "set doorbell buffer config";
1431 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
1432 : 0 : return "wait for doorbell buffer config";
1433 : 6 : case NVME_CTRLR_STATE_SET_HOST_ID:
1434 : 6 : return "set host ID";
1435 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
1436 : 0 : return "wait for set host ID";
1437 : 6 : case NVME_CTRLR_STATE_TRANSPORT_READY:
1438 : 6 : return "transport ready";
1439 : 10 : case NVME_CTRLR_STATE_READY:
1440 : 10 : return "ready";
1441 : 4 : case NVME_CTRLR_STATE_ERROR:
1442 : 4 : return "error";
1443 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
1444 : 0 : return "disconnected";
1445 : : }
1446 : 0 : return "unknown";
1447 : : };
1448 : :
1449 : : static void
1450 : 146672 : _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1451 : : uint64_t timeout_in_ms, bool quiet)
1452 : : {
1453 : : uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
1454 : :
1455 : 146672 : ctrlr->state = state;
1456 [ + + ]: 146672 : if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) {
1457 [ - + ]: 62291 : if (!quiet) {
1458 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n",
# # # # ]
1459 : : nvme_ctrlr_state_string(ctrlr->state));
1460 : : }
1461 : 62291 : return;
1462 : : }
1463 : :
1464 [ + + ]: 84381 : if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
1465 : 24279 : goto inf;
1466 : : }
1467 : :
1468 : 60102 : ticks_per_ms = spdk_get_ticks_hz() / 1000;
1469 [ - + - + ]: 60102 : if (timeout_in_ms > UINT64_MAX / ticks_per_ms) {
1470 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr,
1471 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1472 : 0 : goto inf;
1473 : : }
1474 : :
1475 : 60102 : now_ticks = spdk_get_ticks();
1476 : 60102 : timeout_in_ticks = timeout_in_ms * ticks_per_ms;
1477 [ + + ]: 60102 : if (timeout_in_ticks > UINT64_MAX - now_ticks) {
1478 [ + - - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr,
1479 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1480 : 4 : goto inf;
1481 : : }
1482 : :
1483 : 60098 : ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
1484 [ + - ]: 60098 : if (!quiet) {
1485 [ - + + + : 60098 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n",
+ + + + ]
1486 : : nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
1487 : : }
1488 : 60098 : return;
1489 : 24283 : inf:
1490 [ + - ]: 24283 : if (!quiet) {
1491 [ - + + + : 24283 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n",
+ + + + ]
1492 : : nvme_ctrlr_state_string(ctrlr->state));
1493 : : }
1494 : 24283 : ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
1495 : : }
1496 : :
1497 : : static void
1498 : 84381 : nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1499 : : uint64_t timeout_in_ms)
1500 : : {
1501 : 84381 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false);
1502 : 84381 : }
1503 : :
1504 : : static void
1505 : 62291 : nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1506 : : uint64_t timeout_in_ms)
1507 : : {
1508 : 62291 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true);
1509 : 62291 : }
1510 : :
1511 : : static void
1512 : 2745 : nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1513 : : {
1514 : 2745 : spdk_free(ctrlr->cdata_zns);
1515 : 2745 : ctrlr->cdata_zns = NULL;
1516 : 2745 : }
1517 : :
1518 : : static void
1519 : 2745 : nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1520 : : {
1521 : 2745 : nvme_ctrlr_free_zns_specific_data(ctrlr);
1522 : 2745 : }
1523 : :
1524 : : static void
1525 : 2749 : nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr)
1526 : : {
1527 [ + + ]: 2749 : if (ctrlr->shadow_doorbell) {
1528 : 500 : spdk_free(ctrlr->shadow_doorbell);
1529 : 500 : ctrlr->shadow_doorbell = NULL;
1530 : : }
1531 : :
1532 [ + + ]: 2749 : if (ctrlr->eventidx) {
1533 : 500 : spdk_free(ctrlr->eventidx);
1534 : 500 : ctrlr->eventidx = NULL;
1535 : : }
1536 : 2749 : }
1537 : :
1538 : : static void
1539 : 504 : nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl)
1540 : : {
1541 : 504 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1542 : :
1543 [ + - - + ]: 504 : if (spdk_nvme_cpl_is_error(cpl)) {
1544 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n");
1545 : : } else {
1546 [ - + - + : 504 : NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n");
- - - - ]
1547 : : }
1548 : 504 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1549 : 504 : ctrlr->opts.admin_timeout_ms);
1550 : 504 : }
1551 : :
1552 : : static int
1553 : 2102 : nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr)
1554 : : {
1555 : 2102 : int rc = 0;
1556 : 316 : uint64_t prp1, prp2, len;
1557 : :
1558 [ + + ]: 2102 : if (!ctrlr->cdata.oacs.doorbell_buffer_config) {
1559 : 1598 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1560 : 1598 : ctrlr->opts.admin_timeout_ms);
1561 : 1598 : return 0;
1562 : : }
1563 : :
1564 [ - + ]: 504 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
1565 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1566 : 0 : ctrlr->opts.admin_timeout_ms);
1567 : 0 : return 0;
1568 : : }
1569 : :
1570 : : /* only 1 page size for doorbell buffer */
1571 : 504 : ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1572 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1573 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1574 [ - + ]: 504 : if (ctrlr->shadow_doorbell == NULL) {
1575 : 0 : rc = -ENOMEM;
1576 : 0 : goto error;
1577 : : }
1578 : :
1579 : 504 : len = ctrlr->page_size;
1580 : 504 : prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len);
1581 [ + - - + ]: 504 : if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1582 : 0 : rc = -EFAULT;
1583 : 0 : goto error;
1584 : : }
1585 : :
1586 : 504 : ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1587 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1588 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1589 [ - + ]: 504 : if (ctrlr->eventidx == NULL) {
1590 : 0 : rc = -ENOMEM;
1591 : 0 : goto error;
1592 : : }
1593 : :
1594 : 504 : len = ctrlr->page_size;
1595 : 504 : prp2 = spdk_vtophys(ctrlr->eventidx, &len);
1596 [ + - - + ]: 504 : if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1597 : 0 : rc = -EFAULT;
1598 : 0 : goto error;
1599 : : }
1600 : :
1601 : 504 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG,
1602 : 504 : ctrlr->opts.admin_timeout_ms);
1603 : :
1604 : 504 : rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2,
1605 : : nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr);
1606 [ - + ]: 504 : if (rc != 0) {
1607 : 0 : goto error;
1608 : : }
1609 : :
1610 : 504 : return 0;
1611 : :
1612 : 0 : error:
1613 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1614 : 0 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1615 : 0 : return rc;
1616 : : }
1617 : :
1618 : : void
1619 : 4830 : nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr)
1620 : : {
1621 : : struct nvme_request *req, *tmp;
1622 : 4830 : struct spdk_nvme_cpl cpl = {};
1623 : :
1624 : 4830 : cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION;
1625 : 4830 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
1626 : :
1627 [ - + ]: 4830 : STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) {
1628 [ # # ]: 0 : STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq);
1629 : 0 : ctrlr->outstanding_aborts++;
1630 : :
1631 : 0 : nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl);
1632 : : }
1633 : 4830 : }
1634 : :
1635 : : static int
1636 : 486 : nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1637 : : {
1638 [ + + + + : 486 : if (ctrlr->is_resetting || ctrlr->is_removed) {
- + - + ]
1639 : : /*
1640 : : * Controller is already resetting or has been removed. Return
1641 : : * immediately since there is no need to kick off another
1642 : : * reset in these cases.
1643 : : */
1644 [ + + + - ]: 4 : return ctrlr->is_resetting ? -EBUSY : -ENXIO;
1645 : : }
1646 : :
1647 : 482 : ctrlr->is_resetting = true;
1648 : 482 : ctrlr->is_failed = false;
1649 : 482 : ctrlr->is_disconnecting = true;
1650 : 482 : ctrlr->prepare_for_reset = true;
1651 : :
1652 [ + + + + ]: 482 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n");
1653 : :
1654 : : /* Disable keep-alive, it'll be re-enabled as part of the init process */
1655 : 482 : ctrlr->keep_alive_interval_ticks = 0;
1656 : :
1657 : : /* Abort all of the queued abort requests */
1658 : 482 : nvme_ctrlr_abort_queued_aborts(ctrlr);
1659 : :
1660 : 482 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
1661 : :
1662 : 482 : ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1663 : 482 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1664 : :
1665 : 482 : return 0;
1666 : : }
1667 : :
1668 : : static void
1669 : 482 : nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr)
1670 : : {
1671 [ - + - + ]: 482 : assert(ctrlr->is_failed == false);
1672 : 482 : ctrlr->is_disconnecting = false;
1673 : :
1674 : : /* Doorbell buffer config is invalid during reset */
1675 : 482 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1676 : :
1677 : : /* I/O Command Set Specific Identify Controller data is invalidated during reset */
1678 : 482 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
1679 : :
1680 : 482 : spdk_bit_array_free(&ctrlr->free_io_qids);
1681 : :
1682 : : /* Set the state back to DISCONNECTED to cause a full hardware reset. */
1683 : 482 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE);
1684 : 482 : }
1685 : :
1686 : : int
1687 : 433 : spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1688 : : {
1689 : : int rc;
1690 : :
1691 : 433 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1692 : 433 : rc = nvme_ctrlr_disconnect(ctrlr);
1693 : 433 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1694 : :
1695 : 433 : return rc;
1696 : : }
1697 : :
1698 : : void
1699 : 482 : spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr)
1700 : : {
1701 : 482 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1702 : :
1703 : 482 : ctrlr->prepare_for_reset = false;
1704 : :
1705 : : /* Set the state back to INIT to cause a full hardware reset. */
1706 : 482 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
1707 : :
1708 : : /* Return without releasing ctrlr_lock. ctrlr_lock will be released when
1709 : : * spdk_nvme_ctrlr_reset_poll_async() returns 0.
1710 : : */
1711 : 482 : }
1712 : :
1713 : : int
1714 : 21 : nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
1715 : : {
1716 : : bool async;
1717 : : int rc;
1718 : :
1719 [ + - + - ]: 42 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc ||
1720 [ - + ]: 42 : spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) {
1721 : 0 : assert(false);
1722 : : return -EINVAL;
1723 : : }
1724 : :
1725 : : /* Force a synchronous connect. */
1726 : 21 : async = qpair->async;
1727 : 21 : qpair->async = false;
1728 : 21 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
1729 : 21 : qpair->async = async;
1730 : :
1731 [ - + ]: 21 : if (rc != 0) {
1732 : 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1733 : : }
1734 : :
1735 : 21 : return rc;
1736 : : }
1737 : :
1738 : : /**
1739 : : * This function will be called when the controller is being reinitialized.
1740 : : * Note: the ctrlr_lock must be held when calling this function.
1741 : : */
1742 : : int
1743 : 1609312 : spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr)
1744 : : {
1745 : : struct spdk_nvme_ns *ns, *tmp_ns;
1746 : : struct spdk_nvme_qpair *qpair;
1747 : 1609312 : int rc = 0, rc_tmp = 0;
1748 : :
1749 [ + + ]: 1609312 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1750 [ + + + - ]: 365 : NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n");
1751 : 365 : rc = -1;
1752 : : }
1753 [ + + + + ]: 1609312 : if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) {
1754 : 1608837 : return -EAGAIN;
1755 : : }
1756 : :
1757 : : /*
1758 : : * For non-fabrics controllers, the memory locations of the transport qpair
1759 : : * don't change when the controller is reset. They simply need to be
1760 : : * re-enabled with admin commands to the controller. For fabric
1761 : : * controllers we need to disconnect and reconnect the qpair on its
1762 : : * own thread outside of the context of the reset.
1763 : : */
1764 [ + + + + ]: 475 : if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
1765 : : /* Reinitialize qpairs */
1766 [ + + ]: 87 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1767 : : /* Always clear the qid bit here, even for a foreign qpair. We need
1768 : : * to make sure another process doesn't get the chance to grab that
1769 : : * qid.
1770 : : */
1771 [ - + ]: 21 : assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id));
1772 : 21 : spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id);
1773 [ + + ]: 21 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) {
1774 : : /*
1775 : : * We cannot reinitialize a foreign qpair. The qpair's owning
1776 : : * process will take care of it. Set failure reason to FAILURE_RESET
1777 : : * to ensure that happens.
1778 : : */
1779 : 15 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET;
1780 : 15 : continue;
1781 : : }
1782 : 6 : rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair);
1783 [ - + ]: 6 : if (rc_tmp != 0) {
1784 : 0 : rc = rc_tmp;
1785 : : }
1786 : : }
1787 : : }
1788 : :
1789 : : /*
1790 : : * Take this opportunity to remove inactive namespaces. During a reset namespace
1791 : : * handles can be invalidated.
1792 : : */
1793 [ + + + - ]: 998 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
1794 [ + + + + ]: 523 : if (!ns->active) {
1795 : 5 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
1796 : 5 : spdk_free(ns);
1797 : : }
1798 : : }
1799 : :
1800 [ + + ]: 475 : if (rc) {
1801 : 365 : nvme_ctrlr_fail(ctrlr, false);
1802 : : }
1803 : 475 : ctrlr->is_resetting = false;
1804 : :
1805 : 475 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1806 : :
1807 [ + + ]: 475 : if (!ctrlr->cdata.oaes.ns_attribute_notices) {
1808 : : /*
1809 : : * If controller doesn't support ns_attribute_notices and
1810 : : * namespace attributes change (e.g. number of namespaces)
1811 : : * we need to update system handling device reset.
1812 : : */
1813 : 16 : nvme_io_msg_ctrlr_update(ctrlr);
1814 : : }
1815 : :
1816 : 475 : return rc;
1817 : : }
1818 : :
1819 : : /*
1820 : : * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset
1821 : : * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair.
1822 : : * The following two functions are added to do a Controller Level Reset. They have
1823 : : * to be called under the nvme controller's lock.
1824 : : */
1825 : : void
1826 : 66 : nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
1827 : : {
1828 [ - + - + ]: 66 : assert(ctrlr->is_disconnecting == true);
1829 : :
1830 : 66 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
1831 : 66 : }
1832 : :
1833 : : int
1834 : 431 : nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr)
1835 : : {
1836 : 431 : int rc = 0;
1837 : :
1838 [ - + ]: 431 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1839 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n");
1840 : 0 : rc = -1;
1841 : : }
1842 : :
1843 [ + + + - ]: 431 : if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) {
1844 : 365 : return -EAGAIN;
1845 : : }
1846 : :
1847 : 66 : return rc;
1848 : : }
1849 : :
1850 : : static void
1851 : 49 : nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr)
1852 : : {
1853 : : struct spdk_nvme_qpair *qpair;
1854 : :
1855 [ + + ]: 86 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1856 : 37 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1857 : : }
1858 : 49 : }
1859 : :
1860 : : int
1861 : 53 : spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
1862 : : {
1863 : : int rc;
1864 : :
1865 : 53 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1866 : :
1867 : 53 : rc = nvme_ctrlr_disconnect(ctrlr);
1868 [ + + ]: 53 : if (rc == 0) {
1869 : 49 : nvme_ctrlr_fail_io_qpairs(ctrlr);
1870 : : }
1871 : :
1872 : 53 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1873 : :
1874 [ + + ]: 53 : if (rc != 0) {
1875 [ + - ]: 4 : if (rc == -EBUSY) {
1876 : 4 : rc = 0;
1877 : : }
1878 : 4 : return rc;
1879 : : }
1880 : :
1881 : : while (1) {
1882 : 330 : rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr);
1883 [ + + ]: 330 : if (rc == -ENXIO) {
1884 : 49 : break;
1885 : : }
1886 : : }
1887 : :
1888 : 49 : spdk_nvme_ctrlr_reconnect_async(ctrlr);
1889 : :
1890 : : while (true) {
1891 : 29340 : rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr);
1892 [ + + ]: 29340 : if (rc != -EAGAIN) {
1893 : 49 : break;
1894 : : }
1895 : : }
1896 : :
1897 : 49 : return rc;
1898 : : }
1899 : :
1900 : : int
1901 : 0 : spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr)
1902 : : {
1903 : : union spdk_nvme_cap_register cap;
1904 : 0 : int rc = 0;
1905 : :
1906 : 0 : cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
1907 [ # # ]: 0 : if (cap.bits.nssrs == 0) {
1908 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n");
1909 : 0 : return -ENOTSUP;
1910 : : }
1911 : :
1912 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n");
1913 : 0 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1914 : 0 : ctrlr->is_resetting = true;
1915 : 0 : rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE);
1916 : 0 : ctrlr->is_resetting = false;
1917 : :
1918 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1919 : : /*
1920 : : * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause
1921 : : * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup.
1922 : : */
1923 : 0 : return rc;
1924 : : }
1925 : :
1926 : : int
1927 : 33 : spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid)
1928 : : {
1929 : 33 : int rc = 0;
1930 : :
1931 : 33 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1932 : :
1933 [ + + + + ]: 33 : if (ctrlr->is_failed == false) {
1934 : 4 : rc = -EPERM;
1935 : 4 : goto out;
1936 : : }
1937 : :
1938 [ + + ]: 29 : if (trid->trtype != ctrlr->trid.trtype) {
1939 : 4 : rc = -EINVAL;
1940 : 4 : goto out;
1941 : : }
1942 : :
1943 [ + + - + : 25 : if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) {
+ + ]
1944 : 4 : rc = -EINVAL;
1945 : 4 : goto out;
1946 : : }
1947 : :
1948 : 21 : ctrlr->trid = *trid;
1949 : :
1950 : 33 : out:
1951 : 33 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1952 : 33 : return rc;
1953 : : }
1954 : :
1955 : : void
1956 : 1316 : spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr,
1957 : : spdk_nvme_remove_cb remove_cb, void *remove_ctx)
1958 : : {
1959 [ - + ]: 1316 : if (!spdk_process_is_primary()) {
1960 : 0 : return;
1961 : : }
1962 : :
1963 : 1316 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1964 : 1316 : ctrlr->remove_cb = remove_cb;
1965 : 1316 : ctrlr->cb_ctx = remove_ctx;
1966 : 1316 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1967 : : }
1968 : :
1969 : : static void
1970 : 2198 : nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
1971 : : {
1972 : 2198 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1973 : :
1974 [ + - - + ]: 2198 : if (spdk_nvme_cpl_is_error(cpl)) {
1975 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n");
1976 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1977 : 0 : return;
1978 : : }
1979 : :
1980 : : /*
1981 : : * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
1982 : : * controller supports.
1983 : : */
1984 : 2198 : ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr);
1985 [ - + + + : 2198 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + + + ]
1986 [ + + ]: 2198 : if (ctrlr->cdata.mdts > 0) {
1987 [ - + + + : 1890 : ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size,
- + ]
1988 : : ctrlr->min_page_size * (1 << ctrlr->cdata.mdts));
1989 [ - + + + : 1890 : NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + + + ]
1990 : : }
1991 : :
1992 [ - + + + : 2198 : NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid);
+ + + + ]
1993 [ + + ]: 2198 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
1994 : 609 : ctrlr->cntlid = ctrlr->cdata.cntlid;
1995 : : } else {
1996 : : /*
1997 : : * Fabrics controllers should already have CNTLID from the Connect command.
1998 : : *
1999 : : * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data,
2000 : : * trust the one from Connect.
2001 : : */
2002 [ + + ]: 1589 : if (ctrlr->cntlid != ctrlr->cdata.cntlid) {
2003 [ - + + + : 35 : NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n",
+ - - + ]
2004 : : ctrlr->cdata.cntlid, ctrlr->cntlid);
2005 : : }
2006 : : }
2007 : :
2008 [ + + + - ]: 2198 : if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
2009 [ - + ]: 2029 : assert(ctrlr->cdata.sgls.supported != 0x3);
2010 : 2029 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
2011 [ + + ]: 2029 : if (ctrlr->cdata.sgls.supported == 0x2) {
2012 : 35 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT;
2013 : : }
2014 : :
2015 : 2029 : ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr);
2016 [ - + + + : 2029 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges);
+ + + + ]
2017 : : }
2018 : :
2019 [ - + - - ]: 2198 : if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
2020 : 0 : ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED;
2021 : : }
2022 : :
2023 [ + + + - ]: 2198 : if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
2024 : 26 : ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
2025 : : }
2026 : :
2027 [ + + ]: 2198 : if (ctrlr->cdata.oacs.directives) {
2028 : 500 : ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED;
2029 : : }
2030 : :
2031 [ - + + + : 2198 : NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n",
+ + + + ]
2032 : : ctrlr->cdata.fuses.compare_and_write);
2033 [ + + ]: 2198 : if (ctrlr->cdata.fuses.compare_and_write) {
2034 : 1208 : ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED;
2035 : : }
2036 : :
2037 : 2198 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2038 : 2198 : ctrlr->opts.admin_timeout_ms);
2039 : : }
2040 : :
2041 : : static int
2042 : 2198 : nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
2043 : : {
2044 : : int rc;
2045 : :
2046 : 2198 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
2047 : 2198 : ctrlr->opts.admin_timeout_ms);
2048 : :
2049 : 2198 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0,
2050 : 2198 : &ctrlr->cdata, sizeof(ctrlr->cdata),
2051 : : nvme_ctrlr_identify_done, ctrlr);
2052 [ - + ]: 2198 : if (rc != 0) {
2053 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2054 : 0 : return rc;
2055 : : }
2056 : :
2057 : 2198 : return 0;
2058 : : }
2059 : :
2060 : : static void
2061 : 817 : nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl)
2062 : : {
2063 : : struct spdk_nvme_cmds_and_effect_log_page *log_page;
2064 : 817 : struct spdk_nvme_ctrlr *ctrlr = arg;
2065 : :
2066 [ + - - + ]: 817 : if (spdk_nvme_cpl_is_error(cpl)) {
2067 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n");
2068 : 0 : spdk_free(ctrlr->tmp_ptr);
2069 : 0 : ctrlr->tmp_ptr = NULL;
2070 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2071 : 0 : return;
2072 : : }
2073 : :
2074 : 817 : log_page = ctrlr->tmp_ptr;
2075 : :
2076 [ + - ]: 817 : if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) {
2077 : 817 : ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED;
2078 : : }
2079 : 817 : spdk_free(ctrlr->tmp_ptr);
2080 : 817 : ctrlr->tmp_ptr = NULL;
2081 : :
2082 : 817 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms);
2083 : : }
2084 : :
2085 : : static int
2086 : 817 : nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr)
2087 : : {
2088 : : int rc;
2089 : :
2090 [ - + ]: 817 : assert(!ctrlr->tmp_ptr);
2091 : 817 : ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL,
2092 : : SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2093 [ - + ]: 817 : if (!ctrlr->tmp_ptr) {
2094 : 0 : rc = -ENOMEM;
2095 : 0 : goto error;
2096 : : }
2097 : :
2098 : 817 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG,
2099 : 817 : ctrlr->opts.admin_timeout_ms);
2100 : :
2101 : 817 : rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG,
2102 : : 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page),
2103 : : 0, 0, 0, SPDK_NVME_CSI_ZNS << 24,
2104 : : nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr);
2105 [ - + ]: 817 : if (rc != 0) {
2106 : 0 : goto error;
2107 : : }
2108 : :
2109 : 817 : return 0;
2110 : :
2111 : 0 : error:
2112 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2113 : 0 : spdk_free(ctrlr->tmp_ptr);
2114 : 0 : ctrlr->tmp_ptr = NULL;
2115 : 0 : return rc;
2116 : : }
2117 : :
2118 : : static void
2119 : 817 : nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl)
2120 : : {
2121 : 817 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2122 : :
2123 [ + - - + ]: 817 : if (spdk_nvme_cpl_is_error(cpl)) {
2124 : : /* no need to print an error, the controller simply does not support ZNS */
2125 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2126 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2127 : 0 : ctrlr->opts.admin_timeout_ms);
2128 : 0 : return;
2129 : : }
2130 : :
2131 : : /* A zero zasl value means use mdts */
2132 [ - + ]: 817 : if (ctrlr->cdata_zns->zasl) {
2133 [ # # ]: 0 : uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl);
2134 : 0 : ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append);
2135 : : } else {
2136 : 817 : ctrlr->max_zone_append_size = ctrlr->max_xfer_size;
2137 : : }
2138 : :
2139 : 817 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG,
2140 : 817 : ctrlr->opts.admin_timeout_ms);
2141 : : }
2142 : :
2143 : : /**
2144 : : * This function will try to fetch the I/O Command Specific Controller data structure for
2145 : : * each I/O Command Set supported by SPDK.
2146 : : *
2147 : : * If an I/O Command Set is not supported by the controller, "Invalid Field in Command"
2148 : : * will be returned. Since we are fetching in a exploratively way, getting an error back
2149 : : * from the controller should not be treated as fatal.
2150 : : *
2151 : : * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set).
2152 : : *
2153 : : * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific
2154 : : * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set).
2155 : : */
2156 : : static int
2157 : 2118 : nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2158 : : {
2159 : : int rc;
2160 : :
2161 [ + + ]: 2118 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2162 : 1301 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2163 : 1301 : ctrlr->opts.admin_timeout_ms);
2164 : 1301 : return 0;
2165 : : }
2166 : :
2167 : : /*
2168 : : * Since SPDK currently only needs to fetch a single Command Set, keep the code here,
2169 : : * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates,
2170 : : * which would require additional functions and complexity for no good reason.
2171 : : */
2172 [ - + ]: 817 : assert(!ctrlr->cdata_zns);
2173 : 817 : ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2174 : : SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2175 [ - + ]: 817 : if (!ctrlr->cdata_zns) {
2176 : 0 : rc = -ENOMEM;
2177 : 0 : goto error;
2178 : : }
2179 : :
2180 : 817 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC,
2181 : 817 : ctrlr->opts.admin_timeout_ms);
2182 : :
2183 : 817 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS,
2184 : 817 : ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns),
2185 : : nvme_ctrlr_identify_zns_specific_done, ctrlr);
2186 [ - + ]: 817 : if (rc != 0) {
2187 : 0 : goto error;
2188 : : }
2189 : :
2190 : 817 : return 0;
2191 : :
2192 : 0 : error:
2193 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2194 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2195 : 0 : return rc;
2196 : : }
2197 : :
2198 : : enum nvme_active_ns_state {
2199 : : NVME_ACTIVE_NS_STATE_IDLE,
2200 : : NVME_ACTIVE_NS_STATE_PROCESSING,
2201 : : NVME_ACTIVE_NS_STATE_DONE,
2202 : : NVME_ACTIVE_NS_STATE_ERROR
2203 : : };
2204 : :
2205 : : typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *);
2206 : :
2207 : : struct nvme_active_ns_ctx {
2208 : : struct spdk_nvme_ctrlr *ctrlr;
2209 : : uint32_t page_count;
2210 : : uint32_t next_nsid;
2211 : : uint32_t *new_ns_list;
2212 : : nvme_active_ns_ctx_deleter deleter;
2213 : :
2214 : : enum nvme_active_ns_state state;
2215 : : };
2216 : :
2217 : : static struct nvme_active_ns_ctx *
2218 : 2322 : nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter)
2219 : : {
2220 : : struct nvme_active_ns_ctx *ctx;
2221 : 2322 : uint32_t *new_ns_list = NULL;
2222 : :
2223 : 2322 : ctx = calloc(1, sizeof(*ctx));
2224 [ - + ]: 2322 : if (!ctx) {
2225 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n");
2226 : 0 : return NULL;
2227 : : }
2228 : :
2229 : 2322 : new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size,
2230 : : NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE);
2231 [ - + ]: 2322 : if (!new_ns_list) {
2232 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n");
2233 : 0 : free(ctx);
2234 : 0 : return NULL;
2235 : : }
2236 : :
2237 : 2322 : ctx->page_count = 1;
2238 : 2322 : ctx->new_ns_list = new_ns_list;
2239 : 2322 : ctx->ctrlr = ctrlr;
2240 : 2322 : ctx->deleter = deleter;
2241 : :
2242 : 2322 : return ctx;
2243 : : }
2244 : :
2245 : : static void
2246 : 2322 : nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx)
2247 : : {
2248 : 2322 : spdk_free(ctx->new_ns_list);
2249 : 2322 : free(ctx);
2250 : 2322 : }
2251 : :
2252 : : static int
2253 : 75219 : nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2254 : : {
2255 : 73867 : struct spdk_nvme_ns tmp, *ns;
2256 : :
2257 [ - + ]: 75219 : assert(ctrlr != NULL);
2258 : :
2259 : 75219 : tmp.id = nsid;
2260 : 75219 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
2261 [ - + ]: 75219 : if (ns == NULL) {
2262 : 0 : return -EINVAL;
2263 : : }
2264 : :
2265 : 75219 : nvme_ns_destruct(ns);
2266 : 75219 : ns->active = false;
2267 : :
2268 : 75219 : return 0;
2269 : : }
2270 : :
2271 : : static int
2272 : 51064 : nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2273 : : {
2274 : : struct spdk_nvme_ns *ns;
2275 : :
2276 [ + - - + ]: 51064 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
2277 : 0 : return -EINVAL;
2278 : : }
2279 : :
2280 : : /* Namespaces are constructed on demand, so simply request it. */
2281 : 51064 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2282 [ - + ]: 51064 : if (ns == NULL) {
2283 : 0 : return -ENOMEM;
2284 : : }
2285 : :
2286 : 51064 : ns->active = true;
2287 : :
2288 : 51064 : return 0;
2289 : : }
2290 : :
2291 : : static void
2292 : 2318 : nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list,
2293 : : size_t max_entries)
2294 : : {
2295 : 2318 : uint32_t active_ns_count = 0;
2296 : : size_t i;
2297 : : uint32_t nsid;
2298 : : struct spdk_nvme_ns *ns, *tmp_ns;
2299 : : int rc;
2300 : :
2301 : : /* First, remove namespaces that no longer exist */
2302 [ + + + - ]: 63980 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
2303 : 61662 : nsid = new_ns_list[0];
2304 : 61662 : active_ns_count = 0;
2305 [ + + ]: 14190175 : while (nsid != 0) {
2306 [ + + ]: 14147263 : if (nsid == ns->id) {
2307 : 18753 : break;
2308 : : }
2309 : :
2310 : 14128516 : nsid = new_ns_list[active_ns_count++];
2311 : : }
2312 : :
2313 [ + + ]: 61662 : if (nsid != ns->id) {
2314 : : /* Did not find this namespace id in the new list. */
2315 [ - + - + : 42909 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id);
- - - - ]
2316 : 42909 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
2317 : : }
2318 : : }
2319 : :
2320 : : /* Next, add new namespaces */
2321 : 2318 : active_ns_count = 0;
2322 [ + - ]: 53382 : for (i = 0; i < max_entries; i++) {
2323 : 53382 : nsid = new_ns_list[active_ns_count];
2324 : :
2325 [ + + ]: 53382 : if (nsid == 0) {
2326 : 2318 : break;
2327 : : }
2328 : :
2329 : : /* If the namespace already exists, this will not construct it a second time. */
2330 : 51064 : rc = nvme_ctrlr_construct_namespace(ctrlr, nsid);
2331 [ - + ]: 51064 : if (rc != 0) {
2332 : : /* We can't easily handle a failure here. But just move on. */
2333 : 0 : assert(false);
2334 : : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n");
2335 : : continue;
2336 : : }
2337 : :
2338 : 51064 : active_ns_count++;
2339 : : }
2340 : :
2341 : 2318 : ctrlr->active_ns_count = active_ns_count;
2342 : 2318 : }
2343 : :
2344 : : static void
2345 : 2262 : nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2346 : : {
2347 : 2262 : struct nvme_active_ns_ctx *ctx = arg;
2348 : 2262 : uint32_t *new_ns_list = NULL;
2349 : :
2350 [ + + - + ]: 2262 : if (spdk_nvme_cpl_is_error(cpl)) {
2351 : 4 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2352 : 4 : goto out;
2353 : : }
2354 : :
2355 : 2258 : ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1];
2356 [ + + ]: 2258 : if (ctx->next_nsid == 0) {
2357 : 2238 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2358 : 2238 : goto out;
2359 : : }
2360 : :
2361 : 20 : ctx->page_count++;
2362 : 20 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2363 : 20 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2364 : 20 : ctx->ctrlr->page_size);
2365 [ - + ]: 20 : if (!new_ns_list) {
2366 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2367 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2368 : 0 : goto out;
2369 : : }
2370 : :
2371 : 20 : ctx->new_ns_list = new_ns_list;
2372 : 20 : nvme_ctrlr_identify_active_ns_async(ctx);
2373 : 20 : return;
2374 : :
2375 : 2242 : out:
2376 [ + + ]: 2242 : if (ctx->deleter) {
2377 : 2078 : ctx->deleter(ctx);
2378 : : }
2379 : : }
2380 : :
2381 : : static void
2382 : 2342 : nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx)
2383 : : {
2384 : 2342 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2385 : : uint32_t i;
2386 : : int rc;
2387 : :
2388 [ + + ]: 2342 : if (ctrlr->cdata.nn == 0) {
2389 : 64 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2390 : 64 : goto out;
2391 : : }
2392 : :
2393 [ - + ]: 2278 : assert(ctx->new_ns_list != NULL);
2394 : :
2395 : : /*
2396 : : * If controller doesn't support active ns list CNS 0x02 dummy up
2397 : : * an active ns list, i.e. all namespaces report as active
2398 : : */
2399 [ + + - + ]: 2278 : if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) {
2400 : : uint32_t *new_ns_list;
2401 : :
2402 : : /*
2403 : : * Active NS list must always end with zero element.
2404 : : * So, we allocate for cdata.nn+1.
2405 : : */
2406 : 16 : ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1,
2407 : : sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0]));
2408 : 16 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2409 : 16 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2410 : 16 : ctx->ctrlr->page_size);
2411 [ - + ]: 16 : if (!new_ns_list) {
2412 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2413 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2414 : 0 : goto out;
2415 : : }
2416 : :
2417 : 16 : ctx->new_ns_list = new_ns_list;
2418 : 16 : ctx->new_ns_list[ctrlr->cdata.nn] = 0;
2419 [ + + ]: 16364 : for (i = 0; i < ctrlr->cdata.nn; i++) {
2420 : 16348 : ctx->new_ns_list[i] = i + 1;
2421 : : }
2422 : :
2423 : 16 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2424 : 16 : goto out;
2425 : : }
2426 : :
2427 : 2262 : ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING;
2428 : 2262 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0,
2429 : 2262 : &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list),
2430 : : nvme_ctrlr_identify_active_ns_async_done, ctx);
2431 [ - + ]: 2262 : if (rc != 0) {
2432 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2433 : 0 : goto out;
2434 : : }
2435 : :
2436 : 2262 : return;
2437 : :
2438 : 80 : out:
2439 [ + + ]: 80 : if (ctx->deleter) {
2440 : 60 : ctx->deleter(ctx);
2441 : : }
2442 : : }
2443 : :
2444 : : static void
2445 : 2138 : _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx)
2446 : : {
2447 : 2138 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2448 : : struct spdk_nvme_ns *ns;
2449 : :
2450 [ - + ]: 2138 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2451 : 0 : nvme_active_ns_ctx_destroy(ctx);
2452 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2453 : 0 : return;
2454 : : }
2455 : :
2456 [ - + ]: 2138 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2457 : :
2458 [ + + ]: 2259 : RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) {
2459 : 121 : nvme_ns_free_iocs_specific_data(ns);
2460 : : }
2461 : :
2462 : 2138 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2463 : 2138 : nvme_active_ns_ctx_destroy(ctx);
2464 : 2138 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms);
2465 : : }
2466 : :
2467 : : static void
2468 : 2138 : _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2469 : : {
2470 : : struct nvme_active_ns_ctx *ctx;
2471 : :
2472 : 2138 : ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter);
2473 [ - + ]: 2138 : if (!ctx) {
2474 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2475 : 0 : return;
2476 : : }
2477 : :
2478 : 2138 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS,
2479 : 2138 : ctrlr->opts.admin_timeout_ms);
2480 : 2138 : nvme_ctrlr_identify_active_ns_async(ctx);
2481 : : }
2482 : :
2483 : : int
2484 : 184 : nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2485 : : {
2486 : : struct nvme_active_ns_ctx *ctx;
2487 : : int rc;
2488 : :
2489 : 184 : ctx = nvme_active_ns_ctx_create(ctrlr, NULL);
2490 [ - + ]: 184 : if (!ctx) {
2491 : 0 : return -ENOMEM;
2492 : : }
2493 : :
2494 : 184 : nvme_ctrlr_identify_active_ns_async(ctx);
2495 [ + + ]: 167312 : while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) {
2496 : 167128 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
2497 [ - + ]: 167128 : if (rc < 0) {
2498 : 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2499 : 0 : break;
2500 : : }
2501 : : }
2502 : :
2503 [ + + ]: 184 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2504 : 4 : nvme_active_ns_ctx_destroy(ctx);
2505 : 4 : return -ENXIO;
2506 : : }
2507 : :
2508 [ - + ]: 180 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2509 : 180 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2510 : 180 : nvme_active_ns_ctx_destroy(ctx);
2511 : :
2512 : 180 : return 0;
2513 : : }
2514 : :
2515 : : static void
2516 : 1749 : nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2517 : : {
2518 : 1749 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2519 : 1749 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2520 : : uint32_t nsid;
2521 : : int rc;
2522 : :
2523 [ + - - + ]: 1749 : if (spdk_nvme_cpl_is_error(cpl)) {
2524 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2525 : 0 : return;
2526 : : }
2527 : :
2528 : 1749 : nvme_ns_set_identify_data(ns);
2529 : :
2530 : : /* move on to the next active NS */
2531 : 1749 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2532 : 1749 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2533 [ + + ]: 1749 : if (ns == NULL) {
2534 : 1579 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2535 : 1579 : ctrlr->opts.admin_timeout_ms);
2536 : 1579 : return;
2537 : : }
2538 : 170 : ns->ctrlr = ctrlr;
2539 : 170 : ns->id = nsid;
2540 : :
2541 : 170 : rc = nvme_ctrlr_identify_ns_async(ns);
2542 [ - + ]: 170 : if (rc) {
2543 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2544 : : }
2545 : : }
2546 : :
2547 : : static int
2548 : 1749 : nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns)
2549 : : {
2550 : 1749 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2551 : : struct spdk_nvme_ns_data *nsdata;
2552 : :
2553 : 1749 : nsdata = &ns->nsdata;
2554 : :
2555 : 1749 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS,
2556 : 1749 : ctrlr->opts.admin_timeout_ms);
2557 : 1749 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0,
2558 : : nsdata, sizeof(*nsdata),
2559 : : nvme_ctrlr_identify_ns_async_done, ns);
2560 : : }
2561 : :
2562 : : static int
2563 : 2098 : nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2564 : : {
2565 : : uint32_t nsid;
2566 : : struct spdk_nvme_ns *ns;
2567 : : int rc;
2568 : :
2569 : 2098 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2570 : 2098 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2571 [ + + ]: 2098 : if (ns == NULL) {
2572 : : /* No active NS, move on to the next state */
2573 : 519 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2574 : 519 : ctrlr->opts.admin_timeout_ms);
2575 : 519 : return 0;
2576 : : }
2577 : :
2578 : 1579 : ns->ctrlr = ctrlr;
2579 : 1579 : ns->id = nsid;
2580 : :
2581 : 1579 : rc = nvme_ctrlr_identify_ns_async(ns);
2582 [ - + ]: 1579 : if (rc) {
2583 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2584 : : }
2585 : :
2586 : 1579 : return rc;
2587 : : }
2588 : :
2589 : : static int
2590 : 835 : nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
2591 : : {
2592 : : uint32_t nsid;
2593 : : struct spdk_nvme_ns *ns;
2594 : : int rc;
2595 : :
2596 [ + + ]: 835 : if (!prev_nsid) {
2597 : 825 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2598 : : } else {
2599 : : /* move on to the next active NS */
2600 : 10 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid);
2601 : : }
2602 : :
2603 : 835 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2604 [ + + ]: 835 : if (ns == NULL) {
2605 : : /* No first/next active NS, move on to the next state */
2606 : 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2607 : 6 : ctrlr->opts.admin_timeout_ms);
2608 : 6 : return 0;
2609 : : }
2610 : :
2611 : : /* loop until we find a ns which has (supported) iocs specific data */
2612 [ + + ]: 929 : while (!nvme_ns_has_supported_iocs_specific_data(ns)) {
2613 : 919 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2614 : 919 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2615 [ + + ]: 919 : if (ns == NULL) {
2616 : : /* no namespace with (supported) iocs specific data found */
2617 : 819 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2618 : 819 : ctrlr->opts.admin_timeout_ms);
2619 : 819 : return 0;
2620 : : }
2621 : : }
2622 : :
2623 : 10 : rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns);
2624 [ + + ]: 10 : if (rc) {
2625 : 4 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2626 : : }
2627 : :
2628 : 10 : return rc;
2629 : : }
2630 : :
2631 : : static void
2632 : 2 : nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2633 : : {
2634 : 2 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2635 : 2 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2636 : :
2637 [ + - - + ]: 2 : if (spdk_nvme_cpl_is_error(cpl)) {
2638 : 0 : nvme_ns_free_zns_specific_data(ns);
2639 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2640 : 0 : return;
2641 : : }
2642 : :
2643 : 2 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2644 : : }
2645 : :
2646 : : static int
2647 : 10 : nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns)
2648 : : {
2649 : 10 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2650 : : int rc;
2651 : :
2652 [ + - ]: 10 : switch (ns->csi) {
2653 : 10 : case SPDK_NVME_CSI_ZNS:
2654 : 10 : break;
2655 : 0 : default:
2656 : : /*
2657 : : * This switch must handle all cases for which
2658 : : * nvme_ns_has_supported_iocs_specific_data() returns true,
2659 : : * other cases should never happen.
2660 : : */
2661 : 0 : assert(0);
2662 : : }
2663 : :
2664 [ - + ]: 10 : assert(!ns->nsdata_zns);
2665 : 10 : ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2666 : : SPDK_MALLOC_SHARE);
2667 [ - + ]: 10 : if (!ns->nsdata_zns) {
2668 : 0 : return -ENOMEM;
2669 : : }
2670 : :
2671 : 10 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2672 : 10 : ctrlr->opts.admin_timeout_ms);
2673 : 10 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
2674 : 10 : ns->nsdata_zns, sizeof(*ns->nsdata_zns),
2675 : : nvme_ctrlr_identify_ns_zns_specific_async_done, ns);
2676 [ + + ]: 10 : if (rc) {
2677 : 4 : nvme_ns_free_zns_specific_data(ns);
2678 : : }
2679 : :
2680 : 10 : return rc;
2681 : : }
2682 : :
2683 : : static int
2684 : 2098 : nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2685 : : {
2686 [ + + ]: 2098 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2687 : : /* Multi IOCS not supported/enabled, move on to the next state */
2688 : 1281 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2689 : 1281 : ctrlr->opts.admin_timeout_ms);
2690 : 1281 : return 0;
2691 : : }
2692 : :
2693 : 817 : return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0);
2694 : : }
2695 : :
2696 : : static void
2697 : 1597 : nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2698 : : {
2699 : 1597 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2700 : 1597 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2701 : : uint32_t nsid;
2702 : : int rc;
2703 : :
2704 [ + + - + ]: 1597 : if (spdk_nvme_cpl_is_error(cpl)) {
2705 : : /*
2706 : : * Many controllers claim to be compatible with NVMe 1.3, however,
2707 : : * they do not implement NS ID Desc List. Therefore, instead of setting
2708 : : * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion
2709 : : * error and move on to the next state.
2710 : : *
2711 : : * The proper way is to create a new quirk for controllers that violate
2712 : : * the NVMe 1.3 spec by not supporting NS ID Desc List.
2713 : : * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since
2714 : : * it is too generic and was added in order to handle controllers that
2715 : : * violate the NVMe 1.1 spec by not supporting ACTIVE LIST).
2716 : : */
2717 : 15 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2718 : 15 : ctrlr->opts.admin_timeout_ms);
2719 : 15 : return;
2720 : : }
2721 : :
2722 : 1582 : nvme_ns_set_id_desc_list_data(ns);
2723 : :
2724 : : /* move on to the next active NS */
2725 : 1582 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2726 : 1582 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2727 [ + + ]: 1582 : if (ns == NULL) {
2728 : 1456 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2729 : 1456 : ctrlr->opts.admin_timeout_ms);
2730 : 1456 : return;
2731 : : }
2732 : :
2733 : 126 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2734 [ - + ]: 126 : if (rc) {
2735 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2736 : : }
2737 : : }
2738 : :
2739 : : static int
2740 : 1597 : nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns)
2741 : : {
2742 : 1597 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2743 : :
2744 [ - + ]: 1597 : memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list));
2745 : :
2746 : 1597 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS,
2747 : 1597 : ctrlr->opts.admin_timeout_ms);
2748 : 1840 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST,
2749 : 1597 : 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list),
2750 : : nvme_ctrlr_identify_id_desc_async_done, ns);
2751 : : }
2752 : :
2753 : : static int
2754 : 2098 : nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2755 : : {
2756 : : uint32_t nsid;
2757 : : struct spdk_nvme_ns *ns;
2758 : : int rc;
2759 : :
2760 [ + + ]: 2098 : if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) &&
2761 [ - + ]: 142 : !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) ||
2762 [ - + ]: 1956 : (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2763 [ - + - + : 142 : NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n");
- - - - ]
2764 : : /* NS ID Desc List not supported, move on to the next state */
2765 : 142 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2766 : 142 : ctrlr->opts.admin_timeout_ms);
2767 : 142 : return 0;
2768 : : }
2769 : :
2770 : 1956 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2771 : 1956 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2772 [ + + ]: 1956 : if (ns == NULL) {
2773 : : /* No active NS, move on to the next state */
2774 : 485 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2775 : 485 : ctrlr->opts.admin_timeout_ms);
2776 : 485 : return 0;
2777 : : }
2778 : :
2779 : 1471 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2780 [ - + ]: 1471 : if (rc) {
2781 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2782 : : }
2783 : :
2784 : 1471 : return rc;
2785 : : }
2786 : :
2787 : : static void
2788 : 2118 : nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr)
2789 : : {
2790 [ + + ]: 2118 : if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
2791 [ - + ]: 1418 : if (ctrlr->cdata.nvmf_specific.ioccsz < 4) {
2792 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n",
2793 : : ctrlr->cdata.nvmf_specific.ioccsz);
2794 : 0 : ctrlr->cdata.nvmf_specific.ioccsz = 4;
2795 : 0 : assert(0);
2796 : : }
2797 : 1418 : ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd);
2798 : 1418 : ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff;
2799 : : }
2800 : 2118 : }
2801 : :
2802 : : static void
2803 : 2118 : nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl)
2804 : : {
2805 : : uint32_t cq_allocated, sq_allocated, min_allocated, i;
2806 : 2118 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2807 : :
2808 [ + - - + ]: 2118 : if (spdk_nvme_cpl_is_error(cpl)) {
2809 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n");
2810 : 0 : ctrlr->opts.num_io_queues = 0;
2811 : : } else {
2812 : : /*
2813 : : * Data in cdw0 is 0-based.
2814 : : * Lower 16-bits indicate number of submission queues allocated.
2815 : : * Upper 16-bits indicate number of completion queues allocated.
2816 : : */
2817 : 2118 : sq_allocated = (cpl->cdw0 & 0xFFFF) + 1;
2818 : 2118 : cq_allocated = (cpl->cdw0 >> 16) + 1;
2819 : :
2820 : : /*
2821 : : * For 1:1 queue mapping, set number of allocated queues to be minimum of
2822 : : * submission and completion queues.
2823 : : */
2824 : 2118 : min_allocated = spdk_min(sq_allocated, cq_allocated);
2825 : :
2826 : : /* Set number of queues to be minimum of requested and actually allocated. */
2827 : 2118 : ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues);
2828 : : }
2829 : :
2830 : 2118 : ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
2831 [ - + ]: 2118 : if (ctrlr->free_io_qids == NULL) {
2832 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2833 : 0 : return;
2834 : : }
2835 : :
2836 : : /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */
2837 [ + + ]: 230585 : for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
2838 : 228467 : spdk_nvme_ctrlr_free_qid(ctrlr, i);
2839 : : }
2840 : :
2841 : 2118 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS,
2842 : 2118 : ctrlr->opts.admin_timeout_ms);
2843 : : }
2844 : :
2845 : : static int
2846 : 2118 : nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr)
2847 : : {
2848 : : int rc;
2849 : :
2850 [ - + ]: 2118 : if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
2851 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n",
2852 : : ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
2853 : 0 : ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
2854 [ + + ]: 2118 : } else if (ctrlr->opts.num_io_queues < 1) {
2855 [ + - - + ]: 52 : NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n");
2856 : 52 : ctrlr->opts.num_io_queues = 1;
2857 : : }
2858 : :
2859 : 2118 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES,
2860 : 2118 : ctrlr->opts.admin_timeout_ms);
2861 : :
2862 : 2118 : rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
2863 : : nvme_ctrlr_set_num_queues_done, ctrlr);
2864 [ - + ]: 2118 : if (rc != 0) {
2865 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2866 : 0 : return rc;
2867 : : }
2868 : :
2869 : 2118 : return 0;
2870 : : }
2871 : :
2872 : : static void
2873 : 1541 : nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl)
2874 : : {
2875 : : uint32_t keep_alive_interval_us;
2876 : 1541 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2877 : :
2878 [ + + - + ]: 1541 : if (spdk_nvme_cpl_is_error(cpl)) {
2879 [ + - ]: 8 : if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) &&
2880 [ + + ]: 8 : (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) {
2881 [ - + - + : 4 : NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n");
- - - - ]
2882 : : } else {
2883 [ + - - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n",
2884 : : cpl->status.sc, cpl->status.sct);
2885 : 4 : ctrlr->opts.keep_alive_timeout_ms = 0;
2886 : 4 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2887 : 4 : return;
2888 : : }
2889 : : } else {
2890 [ + + ]: 1533 : if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) {
2891 [ - + + + : 39 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n",
+ - - + ]
2892 : : cpl->cdw0);
2893 : : }
2894 : :
2895 : 1533 : ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0;
2896 : : }
2897 : :
2898 [ + + ]: 1537 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2899 : 35 : ctrlr->keep_alive_interval_ticks = 0;
2900 : : } else {
2901 : 1502 : keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2;
2902 : :
2903 [ - + + + : 1502 : NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us);
+ + + - ]
2904 : :
2905 : 1502 : ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) /
2906 : : UINT64_C(1000000);
2907 : :
2908 : : /* Schedule the first Keep Alive to be sent as soon as possible. */
2909 : 1502 : ctrlr->next_keep_alive_tick = spdk_get_ticks();
2910 : : }
2911 : :
2912 [ + + ]: 1537 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2913 : 92 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2914 : : } else {
2915 : 1445 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2916 : 1445 : ctrlr->opts.admin_timeout_ms);
2917 : : }
2918 : : }
2919 : :
2920 : : static int
2921 : 2222 : nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr)
2922 : : {
2923 : : int rc;
2924 : :
2925 [ + + ]: 2222 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2926 [ - + ]: 138 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2927 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2928 : : } else {
2929 : 138 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2930 : 138 : ctrlr->opts.admin_timeout_ms);
2931 : : }
2932 : 138 : return 0;
2933 : : }
2934 : :
2935 : : /* Note: Discovery controller identify data does not populate KAS according to spec. */
2936 [ + + + + ]: 2084 : if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) {
2937 [ - + - + : 543 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n");
- - - - ]
2938 : 543 : ctrlr->opts.keep_alive_timeout_ms = 0;
2939 : 543 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2940 : 543 : ctrlr->opts.admin_timeout_ms);
2941 : 543 : return 0;
2942 : : }
2943 : :
2944 : 1541 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT,
2945 : 1541 : ctrlr->opts.admin_timeout_ms);
2946 : :
2947 : : /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */
2948 : 1541 : rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0,
2949 : : nvme_ctrlr_set_keep_alive_timeout_done, ctrlr);
2950 [ - + ]: 1541 : if (rc != 0) {
2951 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc);
2952 : 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
2953 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2954 : 0 : return rc;
2955 : : }
2956 : :
2957 : 1541 : return 0;
2958 : : }
2959 : :
2960 : : static void
2961 : 0 : nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl)
2962 : : {
2963 : 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2964 : :
2965 [ # # # # ]: 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2966 : : /*
2967 : : * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature
2968 : : * is optional.
2969 : : */
2970 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n",
2971 : : cpl->status.sc, cpl->status.sct);
2972 : : } else {
2973 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n");
# # # # ]
2974 : : }
2975 : :
2976 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
2977 : 0 : }
2978 : :
2979 : : static int
2980 : 2098 : nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr)
2981 : : {
2982 : : uint8_t *host_id;
2983 : : uint32_t host_id_size;
2984 : : int rc;
2985 : :
2986 [ + + ]: 2098 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
2987 : : /*
2988 : : * NVMe-oF sends the host ID during Connect and doesn't allow
2989 : : * Set Features - Host Identifier after Connect, so we don't need to do anything here.
2990 : : */
2991 [ - + + + : 1493 : NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n");
+ + + + ]
2992 : 1493 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
2993 : 1493 : return 0;
2994 : : }
2995 : :
2996 [ - + ]: 605 : if (ctrlr->cdata.ctratt.bits.host_id_exhid_supported) {
2997 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n");
# # # # ]
2998 : 0 : host_id = ctrlr->opts.extended_host_id;
2999 : 0 : host_id_size = sizeof(ctrlr->opts.extended_host_id);
3000 : : } else {
3001 [ - + - + : 605 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n");
- - - - ]
3002 : 605 : host_id = ctrlr->opts.host_id;
3003 : 605 : host_id_size = sizeof(ctrlr->opts.host_id);
3004 : : }
3005 : :
3006 : : /* If the user specified an all-zeroes host identifier, don't send the command. */
3007 [ + - ]: 605 : if (spdk_mem_all_zero(host_id, host_id_size)) {
3008 [ - + - + : 605 : NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n");
- - - - ]
3009 : 605 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
3010 : 605 : return 0;
3011 : : }
3012 : :
3013 [ # # # # ]: 0 : SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size);
3014 : :
3015 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID,
3016 : 0 : ctrlr->opts.admin_timeout_ms);
3017 : :
3018 : 0 : rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr);
3019 [ # # ]: 0 : if (rc != 0) {
3020 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc);
3021 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3022 : 0 : return rc;
3023 : : }
3024 : :
3025 : 0 : return 0;
3026 : : }
3027 : :
3028 : : void
3029 : 116 : nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr)
3030 : : {
3031 : : uint32_t nsid;
3032 : : struct spdk_nvme_ns *ns;
3033 : :
3034 [ + + ]: 146 : for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
3035 [ + + ]: 323 : nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) {
3036 : 215 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
3037 : 215 : nvme_ns_construct(ns, nsid, ctrlr);
3038 : : }
3039 : 116 : }
3040 : :
3041 : : static int
3042 : 116 : nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr)
3043 : : {
3044 : : struct nvme_completion_poll_status *status;
3045 : 116 : int rc = -ENOMEM;
3046 : 116 : char *buffer = NULL;
3047 : : uint32_t nsid;
3048 : 116 : size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t));
3049 : :
3050 [ - + ]: 116 : if (ctrlr->opts.disable_read_changed_ns_list_log_page) {
3051 : 0 : return 0;
3052 : : }
3053 : :
3054 : 116 : buffer = spdk_dma_zmalloc(buf_size, 4096, NULL);
3055 [ - + ]: 116 : if (!buffer) {
3056 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting "
3057 : : "changed ns log.\n");
3058 : 0 : return rc;
3059 : : }
3060 : :
3061 : 116 : status = calloc(1, sizeof(*status));
3062 [ - + ]: 116 : if (!status) {
3063 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
3064 : 0 : goto free_buffer;
3065 : : }
3066 : :
3067 : 116 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr,
3068 : : SPDK_NVME_LOG_CHANGED_NS_LIST,
3069 : : SPDK_NVME_GLOBAL_NS_TAG,
3070 : : buffer, buf_size, 0,
3071 : : nvme_completion_poll_cb, status);
3072 : :
3073 [ - + ]: 116 : if (rc) {
3074 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc);
3075 : 0 : free(status);
3076 : 0 : goto free_buffer;
3077 : : }
3078 : :
3079 : 116 : rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status,
3080 : 116 : ctrlr->opts.admin_timeout_ms * 1000);
3081 [ + + + - ]: 116 : if (!status->timed_out) {
3082 : 116 : free(status);
3083 : : }
3084 : :
3085 [ - + ]: 116 : if (rc) {
3086 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc);
3087 : 0 : goto free_buffer;
3088 : : }
3089 : :
3090 : : /* only check the case of overflow. */
3091 : 116 : nsid = from_le32(buffer);
3092 [ + - ]: 116 : if (nsid == 0xffffffffu) {
3093 [ # # # # ]: 0 : NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n");
3094 : : }
3095 : :
3096 : 116 : free_buffer:
3097 : 116 : spdk_dma_free(buffer);
3098 : 116 : return rc;
3099 : : }
3100 : :
3101 : : static void
3102 : 273 : nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr,
3103 : : const struct spdk_nvme_cpl *cpl)
3104 : : {
3105 : : union spdk_nvme_async_event_completion event;
3106 : : struct spdk_nvme_ctrlr_process *active_proc;
3107 : : int rc;
3108 : :
3109 : 273 : event.raw = cpl->cdw0;
3110 : :
3111 [ + + ]: 273 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3112 [ + + ]: 234 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) {
3113 : 116 : nvme_ctrlr_clear_changed_ns_log(ctrlr);
3114 : :
3115 : 116 : rc = nvme_ctrlr_identify_active_ns(ctrlr);
3116 [ - + ]: 116 : if (rc) {
3117 : 0 : return;
3118 : : }
3119 : 116 : nvme_ctrlr_update_namespaces(ctrlr);
3120 : 116 : nvme_io_msg_ctrlr_update(ctrlr);
3121 : : }
3122 : :
3123 [ + + ]: 273 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3124 [ + + ]: 234 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) {
3125 [ + + + + ]: 104 : if (!ctrlr->opts.disable_read_ana_log_page) {
3126 : 4 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
3127 [ - + ]: 4 : if (rc) {
3128 : 0 : return;
3129 : : }
3130 : 4 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
3131 : : ctrlr);
3132 : : }
3133 : : }
3134 : :
3135 : 273 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3136 [ + - + + ]: 273 : if (active_proc && active_proc->aer_cb_fn) {
3137 : 160 : active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl);
3138 : : }
3139 : : }
3140 : :
3141 : : static void
3142 : 825 : nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr,
3143 : : const struct spdk_nvme_cpl *cpl)
3144 : : {
3145 : : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event;
3146 : : struct spdk_nvme_ctrlr_process *proc;
3147 : :
3148 : : /* Add async event to each process objects event list */
3149 [ + + ]: 1673 : TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) {
3150 : : /* Must be shared memory so other processes can access */
3151 : 848 : nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3152 [ - + ]: 848 : if (!nvme_event) {
3153 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n");
3154 : 0 : return;
3155 : : }
3156 : 848 : nvme_event->cpl = *cpl;
3157 : :
3158 : 848 : STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link);
3159 : : }
3160 : : }
3161 : :
3162 : : static void
3163 : 23203361 : nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr)
3164 : : {
3165 : : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event, *nvme_event_tmp;
3166 : : struct spdk_nvme_ctrlr_process *active_proc;
3167 : :
3168 : 23203361 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3169 : :
3170 [ + + ]: 23203629 : STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) {
3171 [ + - + + : 273 : STAILQ_REMOVE(&active_proc->async_events, nvme_event,
- - - - ]
3172 : : spdk_nvme_ctrlr_aer_completion_list, link);
3173 : 273 : nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl);
3174 : 273 : spdk_free(nvme_event);
3175 : :
3176 : : }
3177 : 23203361 : }
3178 : :
3179 : : static void
3180 : 9064 : nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
3181 : : {
3182 : 9064 : struct nvme_async_event_request *aer = arg;
3183 : 9064 : struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
3184 : :
3185 [ + - ]: 9064 : if (cpl->status.sct == SPDK_NVME_SCT_GENERIC &&
3186 [ + + ]: 9064 : cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
3187 : : /*
3188 : : * This is simulated when controller is being shut down, to
3189 : : * effectively abort outstanding asynchronous event requests
3190 : : * and make sure all memory is freed. Do not repost the
3191 : : * request in this case.
3192 : : */
3193 : 8239 : return;
3194 : : }
3195 : :
3196 [ - + ]: 825 : if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
3197 [ # # ]: 0 : cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) {
3198 : : /*
3199 : : * SPDK will only send as many AERs as the device says it supports,
3200 : : * so this status code indicates an out-of-spec device. Do not repost
3201 : : * the request in this case.
3202 : : */
3203 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n"
3204 : : "handling. Do not repost this AER.\n");
3205 : 0 : return;
3206 : : }
3207 : :
3208 : : /* Add the events to the list */
3209 : 825 : nvme_ctrlr_queue_async_event(ctrlr, cpl);
3210 : :
3211 : : /* If the ctrlr was removed or in the destruct state, we should not send aer again */
3212 [ + + + + : 825 : if (ctrlr->is_removed || ctrlr->is_destructed) {
- + + + ]
3213 : 217 : return;
3214 : : }
3215 : :
3216 : : /*
3217 : : * Repost another asynchronous event request to replace the one
3218 : : * that just completed.
3219 : : */
3220 [ - + ]: 608 : if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
3221 : : /*
3222 : : * We can't do anything to recover from a failure here,
3223 : : * so just print a warning message and leave the AER unsubmitted.
3224 : : */
3225 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n");
3226 : : }
3227 : : }
3228 : :
3229 : : static int
3230 : 9208 : nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
3231 : : struct nvme_async_event_request *aer)
3232 : : {
3233 : : struct nvme_request *req;
3234 : :
3235 : 9208 : aer->ctrlr = ctrlr;
3236 : 9208 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer);
3237 : 9208 : aer->req = req;
3238 [ - + ]: 9208 : if (req == NULL) {
3239 : 0 : return -1;
3240 : : }
3241 : :
3242 : 9208 : req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
3243 : 9208 : return nvme_ctrlr_submit_admin_request(ctrlr, req);
3244 : : }
3245 : :
3246 : : static void
3247 : 2210 : nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl)
3248 : : {
3249 : : struct nvme_async_event_request *aer;
3250 : : int rc;
3251 : : uint32_t i;
3252 : 2210 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3253 : :
3254 [ + - - + ]: 2210 : if (spdk_nvme_cpl_is_error(cpl)) {
3255 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n");
3256 : 0 : ctrlr->num_aers = 0;
3257 : : } else {
3258 : : /* aerl is a zero-based value, so we need to add 1 here. */
3259 [ + - ]: 2210 : ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
3260 : : }
3261 : :
3262 [ + + ]: 10810 : for (i = 0; i < ctrlr->num_aers; i++) {
3263 : 8600 : aer = &ctrlr->aer[i];
3264 : 8600 : rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
3265 [ - + ]: 8600 : if (rc) {
3266 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n");
3267 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3268 : 0 : return;
3269 : : }
3270 : : }
3271 : 2210 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms);
3272 : : }
3273 : :
3274 : : static int
3275 : 2210 : nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
3276 : : {
3277 : : union spdk_nvme_feat_async_event_configuration config;
3278 : : int rc;
3279 : :
3280 : 2210 : config.raw = 0;
3281 : :
3282 [ + + ]: 2210 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3283 : 92 : config.bits.discovery_log_change_notice = 1;
3284 : : } else {
3285 : 2118 : config.bits.crit_warn.bits.available_spare = 1;
3286 : 2118 : config.bits.crit_warn.bits.temperature = 1;
3287 : 2118 : config.bits.crit_warn.bits.device_reliability = 1;
3288 : 2118 : config.bits.crit_warn.bits.read_only = 1;
3289 : 2118 : config.bits.crit_warn.bits.volatile_memory_backup = 1;
3290 : :
3291 [ + + ]: 2118 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) {
3292 [ + + ]: 2058 : if (ctrlr->cdata.oaes.ns_attribute_notices) {
3293 : 1948 : config.bits.ns_attr_notice = 1;
3294 : : }
3295 [ + + ]: 2058 : if (ctrlr->cdata.oaes.fw_activation_notices) {
3296 : 105 : config.bits.fw_activation_notice = 1;
3297 : : }
3298 [ + + ]: 2058 : if (ctrlr->cdata.oaes.ana_change_notices) {
3299 : 331 : config.bits.ana_change_notice = 1;
3300 : : }
3301 : : }
3302 [ + + + + ]: 2118 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) {
3303 : 11 : config.bits.telemetry_log_notice = 1;
3304 : : }
3305 : : }
3306 : :
3307 : 2210 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER,
3308 : 2210 : ctrlr->opts.admin_timeout_ms);
3309 : :
3310 : 2210 : rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config,
3311 : : nvme_ctrlr_configure_aer_done,
3312 : : ctrlr);
3313 [ - + ]: 2210 : if (rc != 0) {
3314 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3315 : 0 : return rc;
3316 : : }
3317 : :
3318 : 2210 : return 0;
3319 : : }
3320 : :
3321 : : struct spdk_nvme_ctrlr_process *
3322 : 71779124 : nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid)
3323 : : {
3324 : : struct spdk_nvme_ctrlr_process *active_proc;
3325 : :
3326 [ + + ]: 126144300 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3327 [ + + ]: 126141824 : if (active_proc->pid == pid) {
3328 : 71776648 : return active_proc;
3329 : : }
3330 : : }
3331 : :
3332 : 2473 : return NULL;
3333 : : }
3334 : :
3335 : : struct spdk_nvme_ctrlr_process *
3336 : 71776705 : nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr)
3337 : : {
3338 : 71776705 : return nvme_ctrlr_get_process(ctrlr, getpid());
3339 : : }
3340 : :
3341 : : /**
3342 : : * This function will be called when a process is using the controller.
3343 : : * 1. For the primary process, it is called when constructing the controller.
3344 : : * 2. For the secondary process, it is called at probing the controller.
3345 : : * Note: will check whether the process is already added for the same process.
3346 : : */
3347 : : int
3348 : 2282 : nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
3349 : : {
3350 : : struct spdk_nvme_ctrlr_process *ctrlr_proc;
3351 : 2282 : pid_t pid = getpid();
3352 : :
3353 : : /* Check whether the process is already added or not */
3354 [ + + ]: 2282 : if (nvme_ctrlr_get_process(ctrlr, pid)) {
3355 : 41 : return 0;
3356 : : }
3357 : :
3358 : : /* Initialize the per process properties for this ctrlr */
3359 : 2241 : ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process),
3360 : : 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3361 [ - + ]: 2241 : if (ctrlr_proc == NULL) {
3362 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n");
3363 : :
3364 : 0 : return -1;
3365 : : }
3366 : :
3367 : 2241 : ctrlr_proc->is_primary = spdk_process_is_primary();
3368 : 2241 : ctrlr_proc->pid = pid;
3369 : 2241 : STAILQ_INIT(&ctrlr_proc->active_reqs);
3370 : 2241 : ctrlr_proc->devhandle = devhandle;
3371 : 2241 : ctrlr_proc->ref = 0;
3372 : 2241 : TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs);
3373 : 2241 : STAILQ_INIT(&ctrlr_proc->async_events);
3374 : :
3375 : 2241 : TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq);
3376 : :
3377 : 2241 : return 0;
3378 : : }
3379 : :
3380 : : /**
3381 : : * This function will be called when the process detaches the controller.
3382 : : * Note: the ctrlr_lock must be held when calling this function.
3383 : : */
3384 : : static void
3385 : 141 : nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr,
3386 : : struct spdk_nvme_ctrlr_process *proc)
3387 : : {
3388 : : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3389 : :
3390 [ - + ]: 141 : assert(STAILQ_EMPTY(&proc->active_reqs));
3391 : :
3392 [ + + ]: 153 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3393 : 12 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3394 : : }
3395 : :
3396 [ + + ]: 141 : TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq);
3397 : :
3398 [ + - ]: 141 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
3399 : 141 : spdk_pci_device_detach(proc->devhandle);
3400 : : }
3401 : :
3402 : 141 : spdk_free(proc);
3403 : 141 : }
3404 : :
3405 : : /**
3406 : : * This function will be called when the process exited unexpectedly
3407 : : * in order to free any incomplete nvme request, allocated IO qpairs
3408 : : * and allocated memory.
3409 : : * Note: the ctrlr_lock must be held when calling this function.
3410 : : */
3411 : : static void
3412 : 5 : nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc)
3413 : : {
3414 : : struct nvme_request *req, *tmp_req;
3415 : : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3416 : : struct spdk_nvme_ctrlr_aer_completion_list *event;
3417 : :
3418 [ - + ]: 5 : STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
3419 [ # # # # : 0 : STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
# # # # ]
3420 : :
3421 [ # # ]: 0 : assert(req->pid == proc->pid);
3422 : 0 : nvme_cleanup_user_req(req);
3423 : 0 : nvme_free_request(req);
3424 : : }
3425 : :
3426 : : /* Remove async event from each process objects event list */
3427 [ - + ]: 5 : while (!STAILQ_EMPTY(&proc->async_events)) {
3428 : 0 : event = STAILQ_FIRST(&proc->async_events);
3429 [ # # ]: 0 : STAILQ_REMOVE_HEAD(&proc->async_events, link);
3430 : 0 : spdk_free(event);
3431 : : }
3432 : :
3433 [ - + ]: 5 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3434 [ # # ]: 0 : TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq);
3435 : :
3436 : : /*
3437 : : * The process may have been killed while some qpairs were in their
3438 : : * completion context. Clear that flag here to allow these IO
3439 : : * qpairs to be deleted.
3440 : : */
3441 : 0 : qpair->in_completion_context = 0;
3442 : :
3443 : 0 : qpair->no_deletion_notification_needed = 1;
3444 : :
3445 : 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3446 : : }
3447 : :
3448 : 5 : spdk_free(proc);
3449 : 5 : }
3450 : :
3451 : : /**
3452 : : * This function will be called when destructing the controller.
3453 : : * 1. There is no more admin request on this controller.
3454 : : * 2. Clean up any left resource allocation when its associated process is gone.
3455 : : */
3456 : : void
3457 : 2286 : nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr)
3458 : : {
3459 : : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3460 : :
3461 : : /* Free all the processes' properties and make sure no pending admin IOs */
3462 [ + + ]: 4377 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3463 [ - + ]: 2091 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3464 : :
3465 [ - + ]: 2091 : assert(STAILQ_EMPTY(&active_proc->active_reqs));
3466 : :
3467 : 2091 : spdk_free(active_proc);
3468 : : }
3469 : 2286 : }
3470 : :
3471 : : /**
3472 : : * This function will be called when any other process attaches or
3473 : : * detaches the controller in order to cleanup those unexpectedly
3474 : : * terminated processes.
3475 : : * Note: the ctrlr_lock must be held when calling this function.
3476 : : */
3477 : : static int
3478 : 6339 : nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr)
3479 : : {
3480 : : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3481 : 6339 : int active_proc_count = 0;
3482 : :
3483 [ + + ]: 13225 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3484 [ + + + - ]: 6886 : if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) {
3485 [ + - - + ]: 5 : NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid);
3486 : :
3487 [ + - ]: 5 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3488 : :
3489 : 5 : nvme_ctrlr_cleanup_process(active_proc);
3490 : : } else {
3491 : 6881 : active_proc_count++;
3492 : : }
3493 : : }
3494 : :
3495 : 6339 : return active_proc_count;
3496 : : }
3497 : :
3498 : : void
3499 : 2119 : nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr)
3500 : : {
3501 : : struct spdk_nvme_ctrlr_process *active_proc;
3502 : :
3503 : 2119 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3504 : :
3505 : 2119 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3506 : :
3507 : 2119 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3508 [ + - ]: 2119 : if (active_proc) {
3509 : 2119 : active_proc->ref++;
3510 : : }
3511 : :
3512 : 2119 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3513 : 2119 : }
3514 : :
3515 : : void
3516 : 2110 : nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr)
3517 : : {
3518 : : struct spdk_nvme_ctrlr_process *active_proc;
3519 : : int proc_count;
3520 : :
3521 : 2110 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3522 : :
3523 : 2110 : proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr);
3524 : :
3525 : 2110 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3526 [ + - ]: 2110 : if (active_proc) {
3527 : 2110 : active_proc->ref--;
3528 [ - + ]: 2110 : assert(active_proc->ref >= 0);
3529 : :
3530 : : /*
3531 : : * The last active process will be removed at the end of
3532 : : * the destruction of the controller.
3533 : : */
3534 [ + - + + ]: 2110 : if (active_proc->ref == 0 && proc_count != 1) {
3535 : 137 : nvme_ctrlr_remove_process(ctrlr, active_proc);
3536 : : }
3537 : : }
3538 : :
3539 : 2110 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3540 : 2110 : }
3541 : :
3542 : : int
3543 : 2110 : nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr)
3544 : : {
3545 : : struct spdk_nvme_ctrlr_process *active_proc;
3546 : 2110 : int ref = 0;
3547 : :
3548 : 2110 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3549 : :
3550 : 2110 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3551 : :
3552 [ + + ]: 4399 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3553 : 2289 : ref += active_proc->ref;
3554 : : }
3555 : :
3556 : 2110 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3557 : :
3558 : 2110 : return ref;
3559 : : }
3560 : :
3561 : : /**
3562 : : * Get the PCI device handle which is only visible to its associated process.
3563 : : */
3564 : : struct spdk_pci_device *
3565 : 631 : nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr)
3566 : : {
3567 : : struct spdk_nvme_ctrlr_process *active_proc;
3568 : 631 : struct spdk_pci_device *devhandle = NULL;
3569 : :
3570 : 631 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3571 : :
3572 : 631 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3573 [ + - ]: 631 : if (active_proc) {
3574 : 631 : devhandle = active_proc->devhandle;
3575 : : }
3576 : :
3577 : 631 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3578 : :
3579 : 631 : return devhandle;
3580 : : }
3581 : :
3582 : : static void
3583 : 2218 : nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3584 : : {
3585 : 2218 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3586 : :
3587 [ + - - + ]: 2218 : if (spdk_nvme_cpl_is_error(cpl)) {
3588 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n");
3589 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3590 : 0 : return;
3591 : : }
3592 : :
3593 [ - + ]: 2218 : assert(value <= UINT32_MAX);
3594 : 2218 : ctrlr->vs.raw = (uint32_t)value;
3595 : 2218 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE);
3596 : : }
3597 : :
3598 : : static void
3599 : 2218 : nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3600 : : {
3601 : 2218 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3602 : :
3603 [ + - - + ]: 2218 : if (spdk_nvme_cpl_is_error(cpl)) {
3604 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n");
3605 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3606 : 0 : return;
3607 : : }
3608 : :
3609 : 2218 : ctrlr->cap.raw = value;
3610 : 2218 : nvme_ctrlr_init_cap(ctrlr);
3611 : 2218 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
3612 : : }
3613 : :
3614 : : static void
3615 : 2284 : nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3616 : : {
3617 : 2284 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3618 : : enum nvme_ctrlr_state state;
3619 : :
3620 [ + - - + ]: 2284 : if (spdk_nvme_cpl_is_error(cpl)) {
3621 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3622 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3623 : 0 : return;
3624 : : }
3625 : :
3626 [ - + ]: 2284 : assert(value <= UINT32_MAX);
3627 : 2284 : ctrlr->process_init_cc.raw = (uint32_t)value;
3628 : :
3629 [ + + ]: 2284 : if (ctrlr->process_init_cc.bits.en) {
3630 [ - + - + : 503 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n");
- - - - ]
3631 : 503 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1;
3632 : : } else {
3633 : 1781 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0;
3634 : : }
3635 : :
3636 : 2284 : nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr));
3637 : : }
3638 : :
3639 : : static void
3640 : 503 : nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3641 : : {
3642 : 503 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3643 : :
3644 [ + - - + ]: 503 : if (spdk_nvme_cpl_is_error(cpl)) {
3645 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n");
3646 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3647 : 0 : return;
3648 : : }
3649 : :
3650 : : /*
3651 : : * Wait 2.5 seconds before accessing PCI registers.
3652 : : * Not using sleep() to avoid blocking other controller's initialization.
3653 : : */
3654 [ - + ]: 503 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
3655 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n");
# # # # ]
3656 : 0 : ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000);
3657 : : }
3658 : :
3659 : 503 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3660 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3661 : : }
3662 : :
3663 : : static void
3664 : 503 : nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3665 : : {
3666 : 503 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3667 : : union spdk_nvme_cc_register cc;
3668 : : int rc;
3669 : :
3670 [ + - - + ]: 503 : if (spdk_nvme_cpl_is_error(cpl)) {
3671 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3672 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3673 : 0 : return;
3674 : : }
3675 : :
3676 [ - + ]: 503 : assert(value <= UINT32_MAX);
3677 : 503 : cc.raw = (uint32_t)value;
3678 : 503 : cc.bits.en = 0;
3679 : 503 : ctrlr->process_init_cc.raw = cc.raw;
3680 : :
3681 : 503 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC,
3682 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3683 : :
3684 : 503 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr);
3685 [ - + ]: 503 : if (rc != 0) {
3686 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
3687 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3688 : : }
3689 : : }
3690 : :
3691 : : static void
3692 : 503 : nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3693 : : {
3694 : 503 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3695 : : union spdk_nvme_csts_register csts;
3696 : :
3697 [ + - - + ]: 503 : if (spdk_nvme_cpl_is_error(cpl)) {
3698 : : /* While a device is resetting, it may be unable to service MMIO reads
3699 : : * temporarily. Allow for this case.
3700 : : */
3701 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # ]
3702 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # ]
3703 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3704 : : NVME_TIMEOUT_KEEP_EXISTING);
3705 : : } else {
3706 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3707 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3708 : : }
3709 : :
3710 : 0 : return;
3711 : : }
3712 : :
3713 [ - + ]: 503 : assert(value <= UINT32_MAX);
3714 : 503 : csts.raw = (uint32_t)value;
3715 [ - + - - ]: 503 : if (csts.bits.rdy == 1 || csts.bits.cfs == 1) {
3716 : 503 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0,
3717 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3718 : : } else {
3719 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
# # # # ]
3720 : 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3721 : : NVME_TIMEOUT_KEEP_EXISTING);
3722 : : }
3723 : : }
3724 : :
3725 : : static void
3726 : 2335 : nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3727 : : {
3728 : 2335 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3729 : : union spdk_nvme_csts_register csts;
3730 : :
3731 [ + - - + ]: 2335 : if (spdk_nvme_cpl_is_error(cpl)) {
3732 : : /* While a device is resetting, it may be unable to service MMIO reads
3733 : : * temporarily. Allow for this case.
3734 : : */
3735 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # ]
3736 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # ]
3737 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3738 : : NVME_TIMEOUT_KEEP_EXISTING);
3739 : : } else {
3740 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3741 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3742 : : }
3743 : :
3744 : 0 : return;
3745 : : }
3746 : :
3747 [ - + ]: 2335 : assert(value <= UINT32_MAX);
3748 : 2335 : csts.raw = (uint32_t)value;
3749 [ + + ]: 2335 : if (csts.bits.rdy == 0) {
3750 [ - + + + : 2284 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n");
+ + + + ]
3751 : 2284 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED,
3752 : : nvme_ctrlr_get_ready_timeout(ctrlr));
3753 : : } else {
3754 : 51 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3755 : : NVME_TIMEOUT_KEEP_EXISTING);
3756 : : }
3757 : : }
3758 : :
3759 : : static void
3760 : 30786 : nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value,
3761 : : const struct spdk_nvme_cpl *cpl)
3762 : : {
3763 : 30786 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3764 : : union spdk_nvme_csts_register csts;
3765 : :
3766 [ + - - + ]: 30786 : if (spdk_nvme_cpl_is_error(cpl)) {
3767 : : /* While a device is resetting, it may be unable to service MMIO reads
3768 : : * temporarily. Allow for this case.
3769 : : */
3770 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # ]
3771 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # ]
3772 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3773 : : NVME_TIMEOUT_KEEP_EXISTING);
3774 : : } else {
3775 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3776 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3777 : : }
3778 : :
3779 : 0 : return;
3780 : : }
3781 : :
3782 [ - + ]: 30786 : assert(value <= UINT32_MAX);
3783 : 30786 : csts.raw = value;
3784 [ + + ]: 30786 : if (csts.bits.rdy == 1) {
3785 [ - + + + : 2170 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
+ + + + ]
3786 : : /*
3787 : : * The controller has been enabled.
3788 : : * Perform the rest of initialization serially.
3789 : : */
3790 : 2170 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
3791 : 2170 : ctrlr->opts.admin_timeout_ms);
3792 : : } else {
3793 : 28616 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3794 : : NVME_TIMEOUT_KEEP_EXISTING);
3795 : : }
3796 : : }
3797 : :
3798 : : /**
3799 : : * This function will be called repeatedly during initialization until the controller is ready.
3800 : : */
3801 : : int
3802 : 123751680 : nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
3803 : : {
3804 : : uint32_t ready_timeout_in_ms;
3805 : : uint64_t ticks;
3806 : 123751680 : int rc = 0;
3807 : :
3808 : 123751680 : ticks = spdk_get_ticks();
3809 : :
3810 : : /*
3811 : : * May need to avoid accessing any register on the target controller
3812 : : * for a while. Return early without touching the FSM.
3813 : : * Check sleep_timeout_tsc > 0 for unit test.
3814 : : */
3815 [ + + ]: 123751680 : if ((ctrlr->sleep_timeout_tsc > 0) &&
3816 [ + + ]: 118820634 : (ticks <= ctrlr->sleep_timeout_tsc)) {
3817 : 118820548 : return 0;
3818 : : }
3819 : 4931132 : ctrlr->sleep_timeout_tsc = 0;
3820 : :
3821 : 4931132 : ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr);
3822 : :
3823 : : /*
3824 : : * Check if the current initialization step is done or has timed out.
3825 : : */
3826 [ + - + + : 4931132 : switch (ctrlr->state) {
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + +
- ]
3827 : 547 : case NVME_CTRLR_STATE_INIT_DELAY:
3828 : 547 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms);
3829 [ + + ]: 547 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) {
3830 : : /*
3831 : : * Controller may need some delay before it's enabled.
3832 : : *
3833 : : * This is a workaround for an issue where the PCIe-attached NVMe controller
3834 : : * is not ready after VFIO reset. We delay the initialization rather than the
3835 : : * enabling itself, because this is required only for the very first enabling
3836 : : * - directly after a VFIO reset.
3837 : : */
3838 [ - + - + : 86 : NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n");
- - - - ]
3839 : 86 : ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000);
3840 : : }
3841 : 547 : break;
3842 : :
3843 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
3844 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
3845 : 0 : break;
3846 : :
3847 : 2638 : case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */
3848 : 2638 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq);
3849 [ + - ]: 2638 : if (rc == 0) {
3850 : 2638 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ,
3851 : : NVME_TIMEOUT_INFINITE);
3852 : : } else {
3853 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3854 : : }
3855 : 2638 : break;
3856 : :
3857 : 3038027 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
3858 : 3038027 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3859 : :
3860 : 3038027 : switch (nvme_qpair_get_state(ctrlr->adminq)) {
3861 : 2436265 : case NVME_QPAIR_CONNECTING:
3862 : 2436265 : break;
3863 : 1640 : case NVME_QPAIR_CONNECTED:
3864 : 1640 : nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED);
3865 : : /* Fall through */
3866 : 2218 : case NVME_QPAIR_ENABLED:
3867 : 2218 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS,
3868 : : NVME_TIMEOUT_INFINITE);
3869 : : /* Abort any queued requests that were sent while the adminq was connecting
3870 : : * to avoid stalling the init process during a reset, as requests don't get
3871 : : * resubmitted while the controller is resetting and subsequent commands
3872 : : * would get queued too.
3873 : : */
3874 : 2218 : nvme_qpair_abort_queued_reqs(ctrlr->adminq);
3875 : 2218 : break;
3876 : 599124 : case NVME_QPAIR_DISCONNECTING:
3877 [ - + ]: 599124 : assert(ctrlr->adminq->async == true);
3878 : 599124 : break;
3879 : 420 : case NVME_QPAIR_DISCONNECTED:
3880 : : /* fallthrough */
3881 : : default:
3882 : 420 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3883 : 420 : break;
3884 : : }
3885 : :
3886 : 3038027 : break;
3887 : :
3888 : 2218 : case NVME_CTRLR_STATE_READ_VS:
3889 : 2218 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE);
3890 : 2218 : rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr);
3891 : 2218 : break;
3892 : :
3893 : 2218 : case NVME_CTRLR_STATE_READ_CAP:
3894 : 2218 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE);
3895 : 2218 : rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr);
3896 : 2218 : break;
3897 : :
3898 : 2284 : case NVME_CTRLR_STATE_CHECK_EN:
3899 : : /* Begin the hardware initialization by making sure the controller is disabled. */
3900 : 2284 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms);
3901 : 2284 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr);
3902 : 2284 : break;
3903 : :
3904 : 503 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
3905 : : /*
3906 : : * Controller is currently enabled. We need to disable it to cause a reset.
3907 : : *
3908 : : * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
3909 : : * Wait for the ready bit to be 1 before disabling the controller.
3910 : : */
3911 : 503 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3912 : : NVME_TIMEOUT_KEEP_EXISTING);
3913 : 503 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr);
3914 : 503 : break;
3915 : :
3916 : 503 : case NVME_CTRLR_STATE_SET_EN_0:
3917 [ - + - + : 503 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n");
- - - - ]
3918 : 503 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms);
3919 : 503 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr);
3920 : 503 : break;
3921 : :
3922 : 2335 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
3923 : 2335 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS,
3924 : : NVME_TIMEOUT_KEEP_EXISTING);
3925 : 2335 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr);
3926 : 2335 : break;
3927 : :
3928 : 2280 : case NVME_CTRLR_STATE_DISABLED:
3929 [ + + + + ]: 2280 : if (ctrlr->is_disconnecting) {
3930 [ - + - + : 62 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n");
- - - - ]
3931 : : } else {
3932 : 2218 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
3933 : :
3934 : : /*
3935 : : * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting
3936 : : * set to 1 if it is too soon after CSTS.RDY is reported as 0.
3937 : : */
3938 : 2218 : spdk_delay_us(100);
3939 : : }
3940 : 2280 : break;
3941 : :
3942 : 2218 : case NVME_CTRLR_STATE_ENABLE:
3943 [ - + + + : 2218 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n");
+ + + + ]
3944 : 2218 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms);
3945 : 2218 : rc = nvme_ctrlr_enable(ctrlr);
3946 [ + + ]: 2218 : if (rc) {
3947 [ + - - + ]: 28 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc);
3948 : : }
3949 : 2218 : return rc;
3950 : :
3951 : 30786 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
3952 : 30786 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3953 : : NVME_TIMEOUT_KEEP_EXISTING);
3954 : 30786 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1,
3955 : : ctrlr);
3956 : 30786 : break;
3957 : :
3958 : 2170 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
3959 : 2170 : nvme_transport_qpair_reset(ctrlr->adminq);
3960 : 2170 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE);
3961 : 2170 : break;
3962 : :
3963 : 2198 : case NVME_CTRLR_STATE_IDENTIFY:
3964 : 2198 : rc = nvme_ctrlr_identify(ctrlr);
3965 : 2198 : break;
3966 : :
3967 : 2210 : case NVME_CTRLR_STATE_CONFIGURE_AER:
3968 : 2210 : rc = nvme_ctrlr_configure_aer(ctrlr);
3969 : 2210 : break;
3970 : :
3971 : 2222 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
3972 : 2222 : rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
3973 : 2222 : break;
3974 : :
3975 : 2118 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
3976 : 2118 : rc = nvme_ctrlr_identify_iocs_specific(ctrlr);
3977 : 2118 : break;
3978 : :
3979 : 817 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
3980 : 817 : rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr);
3981 : 817 : break;
3982 : :
3983 : 2118 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
3984 : 2118 : nvme_ctrlr_update_nvmf_ioccsz(ctrlr);
3985 : 2118 : rc = nvme_ctrlr_set_num_queues(ctrlr);
3986 : 2118 : break;
3987 : :
3988 : 2138 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
3989 : 2138 : _nvme_ctrlr_identify_active_ns(ctrlr);
3990 : 2138 : break;
3991 : :
3992 : 2098 : case NVME_CTRLR_STATE_IDENTIFY_NS:
3993 : 2098 : rc = nvme_ctrlr_identify_namespaces(ctrlr);
3994 : 2098 : break;
3995 : :
3996 : 2098 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
3997 : 2098 : rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr);
3998 : 2098 : break;
3999 : :
4000 : 2098 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
4001 : 2098 : rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr);
4002 : 2098 : break;
4003 : :
4004 : 2102 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
4005 : 2102 : rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
4006 : 2102 : break;
4007 : :
4008 : 98 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
4009 : 98 : rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr);
4010 : 98 : break;
4011 : :
4012 : 2098 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
4013 : 2098 : nvme_ctrlr_set_supported_features(ctrlr);
4014 : 2098 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
4015 : 2098 : ctrlr->opts.admin_timeout_ms);
4016 : 2098 : break;
4017 : :
4018 : 2098 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
4019 : 2098 : rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
4020 : 2098 : break;
4021 : :
4022 : 2098 : case NVME_CTRLR_STATE_SET_HOST_ID:
4023 : 2098 : rc = nvme_ctrlr_set_host_id(ctrlr);
4024 : 2098 : break;
4025 : :
4026 : 2110 : case NVME_CTRLR_STATE_TRANSPORT_READY:
4027 : 2110 : rc = nvme_transport_ctrlr_ready(ctrlr);
4028 [ + + ]: 2110 : if (rc) {
4029 [ + - - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc);
4030 : 4 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4031 : : } else {
4032 : 2106 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
4033 : : }
4034 : 2110 : break;
4035 : :
4036 : 41 : case NVME_CTRLR_STATE_READY:
4037 [ - + + + : 41 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n");
+ + + - ]
4038 : 41 : return 0;
4039 : :
4040 : 420 : case NVME_CTRLR_STATE_ERROR:
4041 [ + + + - ]: 420 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n");
4042 : 420 : return -1;
4043 : :
4044 : 1811225 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
4045 : : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
4046 : : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
4047 : : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
4048 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4049 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
4050 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
4051 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4052 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
4053 : : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
4054 : : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
4055 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
4056 : : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
4057 : : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
4058 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
4059 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
4060 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
4061 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
4062 : : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
4063 : : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
4064 : : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
4065 : : /*
4066 : : * nvme_ctrlr_process_init() may be called from the completion context
4067 : : * for the admin qpair. Avoid recursive calls for this case.
4068 : : */
4069 [ + + ]: 1811225 : if (!ctrlr->adminq->in_completion_context) {
4070 : 1811163 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4071 : : }
4072 : 1811225 : break;
4073 : :
4074 : 0 : default:
4075 : 0 : assert(0);
4076 : : return -1;
4077 : : }
4078 : :
4079 [ + + ]: 4928453 : if (rc) {
4080 [ + - - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n",
4081 : : rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4082 : : }
4083 : :
4084 : : /* Note: we use the ticks captured when we entered this function.
4085 : : * This covers environments where the SPDK process gets swapped out after
4086 : : * we tried to advance the state but before we check the timeout here.
4087 : : * It is not normal for this to happen, but harmless to handle it in this
4088 : : * way.
4089 : : */
4090 [ + + ]: 4928453 : if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
4091 [ - + ]: 1812071 : ticks > ctrlr->state_timeout_tsc) {
4092 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n",
4093 : : ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4094 : 0 : return -1;
4095 : : }
4096 : :
4097 : 4928453 : return rc;
4098 : : }
4099 : :
4100 : : int
4101 : 2278 : nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx)
4102 : : {
4103 : 449 : pthread_mutexattr_t attr;
4104 : 2278 : int rc = 0;
4105 : :
4106 [ - + - + ]: 2278 : if (pthread_mutexattr_init(&attr)) {
4107 : 0 : return -1;
4108 : : }
4109 [ + + + - : 4556 : if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
+ - ]
4110 : : #ifndef __FreeBSD__
4111 [ + + + - ]: 4556 : pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) ||
4112 [ - + - + ]: 4556 : pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) ||
4113 : : #endif
4114 [ - + ]: 2278 : pthread_mutex_init(mtx, &attr)) {
4115 : 0 : rc = -1;
4116 : : }
4117 [ - + ]: 2278 : pthread_mutexattr_destroy(&attr);
4118 : 2278 : return rc;
4119 : : }
4120 : :
4121 : : int
4122 : 2278 : nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
4123 : : {
4124 : : int rc;
4125 : :
4126 [ + + ]: 2278 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
4127 : 547 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE);
4128 : : } else {
4129 : 1731 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
4130 : : }
4131 : :
4132 [ - + ]: 2278 : if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) {
4133 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n",
4134 : : ctrlr->opts.admin_queue_size);
4135 : 0 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES;
4136 : : }
4137 : :
4138 [ - + ]: 2278 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE &&
4139 [ # # ]: 0 : (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) {
4140 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr,
4141 : : "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n",
4142 : : ctrlr->opts.admin_queue_size);
4143 : 0 : ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size,
4144 : : SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE);
4145 : : }
4146 : :
4147 [ + + ]: 2278 : if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) {
4148 [ + - - + ]: 100 : NVME_CTRLR_ERRLOG(ctrlr,
4149 : : "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n",
4150 : : ctrlr->opts.admin_queue_size);
4151 : 100 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES;
4152 : : }
4153 : :
4154 : 2278 : ctrlr->flags = 0;
4155 : 2278 : ctrlr->free_io_qids = NULL;
4156 : 2278 : ctrlr->is_resetting = false;
4157 : 2278 : ctrlr->is_failed = false;
4158 : 2278 : ctrlr->is_destructed = false;
4159 : :
4160 : 2278 : TAILQ_INIT(&ctrlr->active_io_qpairs);
4161 : 2278 : STAILQ_INIT(&ctrlr->queued_aborts);
4162 : 2278 : ctrlr->outstanding_aborts = 0;
4163 : :
4164 : 2278 : ctrlr->ana_log_page = NULL;
4165 : 2278 : ctrlr->ana_log_page_size = 0;
4166 : :
4167 : 2278 : rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock);
4168 [ - + ]: 2278 : if (rc != 0) {
4169 : 0 : return rc;
4170 : : }
4171 : :
4172 : 2278 : TAILQ_INIT(&ctrlr->active_procs);
4173 : 2278 : STAILQ_INIT(&ctrlr->register_operations);
4174 : :
4175 : 2278 : RB_INIT(&ctrlr->ns);
4176 : :
4177 : 2278 : return rc;
4178 : : }
4179 : :
4180 : : static void
4181 : 2218 : nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr)
4182 : : {
4183 [ + + ]: 2218 : if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
4184 : 125 : ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
4185 : : }
4186 : :
4187 [ - + ]: 2218 : ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin);
4188 : :
4189 : : /* For now, always select page_size == min_page_size. */
4190 : 2218 : ctrlr->page_size = ctrlr->min_page_size;
4191 : :
4192 : 2218 : ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES);
4193 : 2218 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES);
4194 [ + + ]: 2218 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE &&
4195 [ + + ]: 94 : ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) {
4196 : : /* If the user specifically set an IO queue size different than the
4197 : : * default, use that value. Otherwise overwrite with the quirked value.
4198 : : * This allows this quirk to be overridden when necessary.
4199 : : * However, cap.mqes still needs to be respected.
4200 : : */
4201 : 82 : ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK;
4202 : : }
4203 : 2218 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u);
4204 : :
4205 : 2218 : ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size);
4206 : 2218 : }
4207 : :
4208 : : void
4209 : 2274 : nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr)
4210 : : {
4211 [ - + ]: 2274 : pthread_mutex_destroy(&ctrlr->ctrlr_lock);
4212 : :
4213 : 2274 : nvme_ctrlr_free_processes(ctrlr);
4214 : 2274 : }
4215 : :
4216 : : void
4217 : 2263 : nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr,
4218 : : struct nvme_ctrlr_detach_ctx *ctx)
4219 : : {
4220 : : struct spdk_nvme_qpair *qpair, *tmp;
4221 : :
4222 [ - + + + : 2263 : NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n");
+ + + + ]
4223 : :
4224 : 2263 : ctrlr->prepare_for_reset = false;
4225 : 2263 : ctrlr->is_destructed = true;
4226 : :
4227 : 2263 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4228 : :
4229 : 2263 : nvme_ctrlr_abort_queued_aborts(ctrlr);
4230 : 2263 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
4231 : :
4232 [ + + ]: 2421 : TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) {
4233 : 158 : spdk_nvme_ctrlr_free_io_qpair(qpair);
4234 : : }
4235 : :
4236 : 2263 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
4237 : 2263 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
4238 : :
4239 : 2263 : nvme_ctrlr_shutdown_async(ctrlr, ctx);
4240 : 2263 : }
4241 : :
4242 : : int
4243 : 16525416 : nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr,
4244 : : struct nvme_ctrlr_detach_ctx *ctx)
4245 : : {
4246 : : struct spdk_nvme_ns *ns, *tmp_ns;
4247 : 16525416 : int rc = 0;
4248 : :
4249 [ + + + + ]: 16525416 : if (!ctx->shutdown_complete) {
4250 : 16525247 : rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx);
4251 [ + + ]: 16525247 : if (rc == -EAGAIN) {
4252 : 16523153 : return -EAGAIN;
4253 : : }
4254 : : /* Destruct ctrlr forcefully for any other error. */
4255 : : }
4256 : :
4257 [ + + ]: 2263 : if (ctx->cb_fn) {
4258 : 1973 : ctx->cb_fn(ctrlr);
4259 : : }
4260 : :
4261 : 2263 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
4262 : :
4263 [ + + + - ]: 34573 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
4264 : 32310 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
4265 : 32310 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
4266 : 32310 : spdk_free(ns);
4267 : : }
4268 : :
4269 : 2263 : ctrlr->active_ns_count = 0;
4270 : :
4271 : 2263 : spdk_bit_array_free(&ctrlr->free_io_qids);
4272 : :
4273 : 2263 : free(ctrlr->ana_log_page);
4274 : 2263 : free(ctrlr->copied_ana_desc);
4275 : 2263 : ctrlr->ana_log_page = NULL;
4276 : 2263 : ctrlr->copied_ana_desc = NULL;
4277 : 2263 : ctrlr->ana_log_page_size = 0;
4278 : :
4279 : 2263 : nvme_transport_ctrlr_destruct(ctrlr);
4280 : :
4281 : 2263 : return rc;
4282 : : }
4283 : :
4284 : : void
4285 : 290 : nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
4286 : : {
4287 : 290 : struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr };
4288 : : int rc;
4289 : :
4290 : 290 : nvme_ctrlr_destruct_async(ctrlr, &ctx);
4291 : :
4292 : : while (1) {
4293 : 769 : rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx);
4294 [ + + ]: 769 : if (rc != -EAGAIN) {
4295 : 290 : break;
4296 : : }
4297 : 479 : nvme_delay(1000);
4298 : : }
4299 : 290 : }
4300 : :
4301 : : int
4302 : 1319703 : nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
4303 : : struct nvme_request *req)
4304 : : {
4305 : 1319703 : return nvme_qpair_submit_request(ctrlr->adminq, req);
4306 : : }
4307 : :
4308 : : static void
4309 : 1386 : nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl)
4310 : : {
4311 : : /* Do nothing */
4312 : 1386 : }
4313 : :
4314 : : /*
4315 : : * Check if we need to send a Keep Alive command.
4316 : : * Caller must hold ctrlr->ctrlr_lock.
4317 : : */
4318 : : static int
4319 : 4150980 : nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr)
4320 : : {
4321 : : uint64_t now;
4322 : : struct nvme_request *req;
4323 : : struct spdk_nvme_cmd *cmd;
4324 : 4150980 : int rc = 0;
4325 : :
4326 : 4150980 : now = spdk_get_ticks();
4327 [ + + ]: 4150980 : if (now < ctrlr->next_keep_alive_tick) {
4328 : 4123452 : return rc;
4329 : : }
4330 : :
4331 : 27528 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL);
4332 [ + + ]: 27528 : if (req == NULL) {
4333 : 26140 : return rc;
4334 : : }
4335 : :
4336 : 1388 : cmd = &req->cmd;
4337 : 1388 : cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE;
4338 : :
4339 : 1388 : rc = nvme_ctrlr_submit_admin_request(ctrlr, req);
4340 [ + + ]: 1388 : if (rc != 0) {
4341 [ + - + - ]: 2 : NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n");
4342 : 2 : rc = -ENXIO;
4343 : : }
4344 : :
4345 : 1388 : ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks;
4346 : 1388 : return rc;
4347 : : }
4348 : :
4349 : : int32_t
4350 : 23203347 : spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
4351 : : {
4352 : : int32_t num_completions;
4353 : : int32_t rc;
4354 : : struct spdk_nvme_ctrlr_process *active_proc;
4355 : :
4356 : 23203347 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4357 : :
4358 [ + + ]: 23203347 : if (ctrlr->keep_alive_interval_ticks) {
4359 : 4150980 : rc = nvme_ctrlr_keep_alive(ctrlr);
4360 [ + + ]: 4150980 : if (rc) {
4361 : 2 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4362 : 2 : return rc;
4363 : : }
4364 : : }
4365 : :
4366 : 23203345 : rc = nvme_io_msg_process(ctrlr);
4367 [ - + ]: 23203345 : if (rc < 0) {
4368 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4369 : 0 : return rc;
4370 : : }
4371 : 23203345 : num_completions = rc;
4372 : :
4373 : 23203345 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4374 : :
4375 : : /* Each process has an async list, complete the ones for this process object */
4376 : 23203345 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4377 [ + + ]: 23203345 : if (active_proc) {
4378 : 23203341 : nvme_ctrlr_complete_queued_async_events(ctrlr);
4379 : : }
4380 : :
4381 [ + + + + : 23203345 : if (rc == -ENXIO && ctrlr->is_disconnecting) {
+ + ]
4382 : 482 : nvme_ctrlr_disconnect_done(ctrlr);
4383 : : }
4384 : :
4385 : 23203345 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4386 : :
4387 [ + + ]: 23203345 : if (rc < 0) {
4388 : 1607 : num_completions = rc;
4389 : : } else {
4390 : 23201734 : num_completions += rc;
4391 : : }
4392 : :
4393 : 23203345 : return num_completions;
4394 : : }
4395 : :
4396 : : const struct spdk_nvme_ctrlr_data *
4397 : 1770113 : spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
4398 : : {
4399 : 1770113 : return &ctrlr->cdata;
4400 : : }
4401 : :
4402 : 20434 : union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr)
4403 : : {
4404 : 9697 : union spdk_nvme_csts_register csts;
4405 : :
4406 [ - + ]: 20434 : if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
4407 : 0 : csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4408 : : }
4409 : 20434 : return csts;
4410 : : }
4411 : :
4412 : 0 : union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr)
4413 : : {
4414 : 0 : union spdk_nvme_cc_register cc;
4415 : :
4416 [ # # ]: 0 : if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
4417 : 0 : cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4418 : : }
4419 : 0 : return cc;
4420 : : }
4421 : :
4422 : 67 : union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
4423 : : {
4424 : 67 : return ctrlr->cap;
4425 : : }
4426 : :
4427 : 1140 : union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
4428 : : {
4429 : 1140 : return ctrlr->vs;
4430 : : }
4431 : :
4432 : 8 : union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr)
4433 : : {
4434 : 0 : union spdk_nvme_cmbsz_register cmbsz;
4435 : :
4436 [ - + ]: 8 : if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) {
4437 : 0 : cmbsz.raw = 0;
4438 : : }
4439 : :
4440 : 8 : return cmbsz;
4441 : : }
4442 : :
4443 : 8 : union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr)
4444 : : {
4445 : 0 : union spdk_nvme_pmrcap_register pmrcap;
4446 : :
4447 [ - + ]: 8 : if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) {
4448 : 0 : pmrcap.raw = 0;
4449 : : }
4450 : :
4451 : 8 : return pmrcap;
4452 : : }
4453 : :
4454 : 0 : union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr)
4455 : : {
4456 : 0 : union spdk_nvme_bpinfo_register bpinfo;
4457 : :
4458 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
4459 : 0 : bpinfo.raw = 0;
4460 : : }
4461 : :
4462 : 0 : return bpinfo;
4463 : : }
4464 : :
4465 : : uint64_t
4466 : 8 : spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr)
4467 : : {
4468 : 8 : return ctrlr->pmr_size;
4469 : : }
4470 : :
4471 : : uint32_t
4472 : 20 : spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
4473 : : {
4474 : 20 : return ctrlr->cdata.nn;
4475 : : }
4476 : :
4477 : : bool
4478 : 37292 : spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4479 : : {
4480 : 37216 : struct spdk_nvme_ns tmp, *ns;
4481 : :
4482 : 37292 : tmp.id = nsid;
4483 : 37292 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4484 : :
4485 [ + + ]: 37292 : if (ns != NULL) {
4486 [ - + ]: 36917 : return ns->active;
4487 : : }
4488 : :
4489 : 375 : return false;
4490 : : }
4491 : :
4492 : : uint32_t
4493 : 10682 : spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr)
4494 : : {
4495 : : struct spdk_nvme_ns *ns;
4496 : :
4497 : 10682 : ns = RB_MIN(nvme_ns_tree, &ctrlr->ns);
4498 [ + + ]: 10682 : if (ns == NULL) {
4499 : 1322 : return 0;
4500 : : }
4501 : :
4502 [ + + ]: 27775 : while (ns != NULL) {
4503 [ + + + + ]: 27758 : if (ns->active) {
4504 : 9343 : return ns->id;
4505 : : }
4506 : :
4507 : 18415 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4508 : : }
4509 : :
4510 : 17 : return 0;
4511 : : }
4512 : :
4513 : : uint32_t
4514 : 28276 : spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
4515 : : {
4516 : 19606 : struct spdk_nvme_ns tmp, *ns;
4517 : :
4518 : 28276 : tmp.id = prev_nsid;
4519 : 28276 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4520 [ + + ]: 28276 : if (ns == NULL) {
4521 : 20 : return 0;
4522 : : }
4523 : :
4524 : 28256 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4525 [ + + ]: 34386 : while (ns != NULL) {
4526 [ + + + + ]: 25110 : if (ns->active) {
4527 : 18980 : return ns->id;
4528 : : }
4529 : :
4530 : 6130 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4531 : : }
4532 : :
4533 : 9276 : return 0;
4534 : : }
4535 : :
4536 : : struct spdk_nvme_ns *
4537 : 62131 : spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4538 : : {
4539 : 51635 : struct spdk_nvme_ns tmp;
4540 : : struct spdk_nvme_ns *ns;
4541 : :
4542 [ + + - + ]: 62131 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
4543 : 4864 : return NULL;
4544 : : }
4545 : :
4546 : 57267 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4547 : :
4548 : 57267 : tmp.id = nsid;
4549 : 57267 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4550 : :
4551 [ + + ]: 57267 : if (ns == NULL) {
4552 : 32319 : ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
4553 [ - + ]: 32319 : if (ns == NULL) {
4554 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4555 : 0 : return NULL;
4556 : : }
4557 : :
4558 [ - + + + : 32319 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid);
+ + + + ]
4559 : 32319 : ns->id = nsid;
4560 : 32319 : RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns);
4561 : : }
4562 : :
4563 : 57267 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4564 : :
4565 : 57267 : return ns;
4566 : : }
4567 : :
4568 : : struct spdk_pci_device *
4569 : 92 : spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr)
4570 : : {
4571 [ - + ]: 92 : if (ctrlr == NULL) {
4572 : 0 : return NULL;
4573 : : }
4574 : :
4575 [ - + ]: 92 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
4576 : 0 : return NULL;
4577 : : }
4578 : :
4579 : 92 : return nvme_ctrlr_proc_get_devhandle(ctrlr);
4580 : : }
4581 : :
4582 : : uint32_t
4583 : 1098 : spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr)
4584 : : {
4585 : 1098 : return ctrlr->max_xfer_size;
4586 : : }
4587 : :
4588 : : uint16_t
4589 : 1004 : spdk_nvme_ctrlr_get_max_sges(const struct spdk_nvme_ctrlr *ctrlr)
4590 : : {
4591 [ + - ]: 1004 : if (ctrlr->flags & SPDK_NVME_CTRLR_SGL_SUPPORTED) {
4592 : 1004 : return ctrlr->max_sges;
4593 : : } else {
4594 : 0 : return UINT16_MAX;
4595 : : }
4596 : : }
4597 : :
4598 : : void
4599 : 1409 : spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
4600 : : spdk_nvme_aer_cb aer_cb_fn,
4601 : : void *aer_cb_arg)
4602 : : {
4603 : : struct spdk_nvme_ctrlr_process *active_proc;
4604 : :
4605 : 1409 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4606 : :
4607 : 1409 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4608 [ + - ]: 1409 : if (active_proc) {
4609 : 1409 : active_proc->aer_cb_fn = aer_cb_fn;
4610 : 1409 : active_proc->aer_cb_arg = aer_cb_arg;
4611 : : }
4612 : :
4613 : 1409 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4614 : 1409 : }
4615 : :
4616 : : void
4617 : 0 : spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr)
4618 : : {
4619 : 0 : ctrlr->opts.disable_read_changed_ns_list_log_page = true;
4620 : 0 : }
4621 : :
4622 : : void
4623 : 24 : spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr,
4624 : : uint64_t timeout_io_us, uint64_t timeout_admin_us,
4625 : : spdk_nvme_timeout_cb cb_fn, void *cb_arg)
4626 : : {
4627 : : struct spdk_nvme_ctrlr_process *active_proc;
4628 : :
4629 : 24 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4630 : :
4631 : 24 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4632 [ + - ]: 24 : if (active_proc) {
4633 : 24 : active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL;
4634 : 24 : active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL;
4635 : 24 : active_proc->timeout_cb_fn = cb_fn;
4636 : 24 : active_proc->timeout_cb_arg = cb_arg;
4637 : : }
4638 : :
4639 : 24 : ctrlr->timeout_enabled = true;
4640 : :
4641 : 24 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4642 : 24 : }
4643 : :
4644 : : bool
4645 : 298 : spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
4646 : : {
4647 : : /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
4648 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
4649 [ - + ]: 298 : return ctrlr->log_page_supported[log_page];
4650 : : }
4651 : :
4652 : : bool
4653 : 16 : spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
4654 : : {
4655 : : /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
4656 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
4657 [ - + ]: 16 : return ctrlr->feature_supported[feature_code];
4658 : : }
4659 : :
4660 : : int
4661 : 4 : spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4662 : : struct spdk_nvme_ctrlr_list *payload)
4663 : : {
4664 : : struct nvme_completion_poll_status *status;
4665 : : struct spdk_nvme_ns *ns;
4666 : : int res;
4667 : :
4668 [ - + ]: 4 : if (nsid == 0) {
4669 : 0 : return -EINVAL;
4670 : : }
4671 : :
4672 : 4 : status = calloc(1, sizeof(*status));
4673 [ - + ]: 4 : if (!status) {
4674 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4675 : 0 : return -ENOMEM;
4676 : : }
4677 : :
4678 : 4 : res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
4679 : : nvme_completion_poll_cb, status);
4680 [ - + ]: 4 : if (res) {
4681 : 0 : free(status);
4682 : 0 : return res;
4683 : : }
4684 [ - + ]: 4 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4685 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n");
4686 [ # # # # ]: 0 : if (!status->timed_out) {
4687 : 0 : free(status);
4688 : : }
4689 : 0 : return -ENXIO;
4690 : : }
4691 : 4 : free(status);
4692 : :
4693 : 4 : res = nvme_ctrlr_identify_active_ns(ctrlr);
4694 [ - + ]: 4 : if (res) {
4695 : 0 : return res;
4696 : : }
4697 : :
4698 : 4 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
4699 [ - + ]: 4 : if (ns == NULL) {
4700 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n");
4701 : 0 : return -ENXIO;
4702 : : }
4703 : :
4704 : 4 : return nvme_ns_construct(ns, nsid, ctrlr);
4705 : : }
4706 : :
4707 : : int
4708 : 4 : spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4709 : : struct spdk_nvme_ctrlr_list *payload)
4710 : : {
4711 : : struct nvme_completion_poll_status *status;
4712 : : int res;
4713 : :
4714 [ - + ]: 4 : if (nsid == 0) {
4715 : 0 : return -EINVAL;
4716 : : }
4717 : :
4718 : 4 : status = calloc(1, sizeof(*status));
4719 [ - + ]: 4 : if (!status) {
4720 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4721 : 0 : return -ENOMEM;
4722 : : }
4723 : :
4724 : 4 : res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
4725 : : nvme_completion_poll_cb, status);
4726 [ - + ]: 4 : if (res) {
4727 : 0 : free(status);
4728 : 0 : return res;
4729 : : }
4730 [ - + ]: 4 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4731 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n");
4732 [ # # # # ]: 0 : if (!status->timed_out) {
4733 : 0 : free(status);
4734 : : }
4735 : 0 : return -ENXIO;
4736 : : }
4737 : 4 : free(status);
4738 : :
4739 : 4 : return nvme_ctrlr_identify_active_ns(ctrlr);
4740 : : }
4741 : :
4742 : : uint32_t
4743 : 4 : spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
4744 : : {
4745 : : struct nvme_completion_poll_status *status;
4746 : : int res;
4747 : : uint32_t nsid;
4748 : :
4749 : 4 : status = calloc(1, sizeof(*status));
4750 [ - + ]: 4 : if (!status) {
4751 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4752 : 0 : return 0;
4753 : : }
4754 : :
4755 : 4 : res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status);
4756 [ - + ]: 4 : if (res) {
4757 : 0 : free(status);
4758 : 0 : return 0;
4759 : : }
4760 [ - + ]: 4 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4761 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n");
4762 [ # # # # ]: 0 : if (!status->timed_out) {
4763 : 0 : free(status);
4764 : : }
4765 : 0 : return 0;
4766 : : }
4767 : :
4768 : 4 : nsid = status->cpl.cdw0;
4769 : 4 : free(status);
4770 : :
4771 [ - + ]: 4 : assert(nsid > 0);
4772 : :
4773 : : /* Return the namespace ID that was created */
4774 : 4 : return nsid;
4775 : : }
4776 : :
4777 : : int
4778 : 4 : spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4779 : : {
4780 : : struct nvme_completion_poll_status *status;
4781 : : int res;
4782 : :
4783 [ - + ]: 4 : if (nsid == 0) {
4784 : 0 : return -EINVAL;
4785 : : }
4786 : :
4787 : 4 : status = calloc(1, sizeof(*status));
4788 [ - + ]: 4 : if (!status) {
4789 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4790 : 0 : return -ENOMEM;
4791 : : }
4792 : :
4793 : 4 : res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status);
4794 [ - + ]: 4 : if (res) {
4795 : 0 : free(status);
4796 : 0 : return res;
4797 : : }
4798 [ - + ]: 4 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4799 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n");
4800 [ # # # # ]: 0 : if (!status->timed_out) {
4801 : 0 : free(status);
4802 : : }
4803 : 0 : return -ENXIO;
4804 : : }
4805 : 4 : free(status);
4806 : :
4807 : 4 : return nvme_ctrlr_identify_active_ns(ctrlr);
4808 : : }
4809 : :
4810 : : int
4811 : 0 : spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4812 : : struct spdk_nvme_format *format)
4813 : : {
4814 : : struct nvme_completion_poll_status *status;
4815 : : int res;
4816 : :
4817 : 0 : status = calloc(1, sizeof(*status));
4818 [ # # ]: 0 : if (!status) {
4819 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4820 : 0 : return -ENOMEM;
4821 : : }
4822 : :
4823 : 0 : res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
4824 : : status);
4825 [ # # ]: 0 : if (res) {
4826 : 0 : free(status);
4827 : 0 : return res;
4828 : : }
4829 [ # # ]: 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4830 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n");
4831 [ # # # # ]: 0 : if (!status->timed_out) {
4832 : 0 : free(status);
4833 : : }
4834 : 0 : return -ENXIO;
4835 : : }
4836 : 0 : free(status);
4837 : :
4838 : 0 : return spdk_nvme_ctrlr_reset(ctrlr);
4839 : : }
4840 : :
4841 : : int
4842 : 32 : spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
4843 : : int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status)
4844 : : {
4845 : 32 : struct spdk_nvme_fw_commit fw_commit;
4846 : : struct nvme_completion_poll_status *status;
4847 : : int res;
4848 : : unsigned int size_remaining;
4849 : : unsigned int offset;
4850 : : unsigned int transfer;
4851 : : uint8_t *p;
4852 : :
4853 [ - + ]: 32 : if (!completion_status) {
4854 : 0 : return -EINVAL;
4855 : : }
4856 [ - + ]: 32 : memset(completion_status, 0, sizeof(struct spdk_nvme_status));
4857 [ + + ]: 32 : if (size % 4) {
4858 [ + - - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n");
4859 : 4 : return -1;
4860 : : }
4861 : :
4862 : : /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG
4863 : : * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG
4864 : : */
4865 [ - + - - ]: 28 : if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) &&
4866 : : (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) {
4867 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n");
4868 : 0 : return -1;
4869 : : }
4870 : :
4871 : 28 : status = calloc(1, sizeof(*status));
4872 [ - + ]: 28 : if (!status) {
4873 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4874 : 0 : return -ENOMEM;
4875 : : }
4876 : :
4877 : : /* Firmware download */
4878 : 28 : size_remaining = size;
4879 : 28 : offset = 0;
4880 : 28 : p = payload;
4881 : :
4882 [ + + ]: 40 : while (size_remaining > 0) {
4883 : 28 : transfer = spdk_min(size_remaining, ctrlr->min_page_size);
4884 : :
4885 [ - + ]: 28 : memset(status, 0, sizeof(*status));
4886 : 28 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
4887 : : nvme_completion_poll_cb,
4888 : : status);
4889 [ + + ]: 28 : if (res) {
4890 : 8 : free(status);
4891 : 8 : return res;
4892 : : }
4893 : :
4894 [ + + ]: 20 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4895 [ + - - + ]: 8 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n");
4896 [ + + + + ]: 8 : if (!status->timed_out) {
4897 : 4 : free(status);
4898 : : }
4899 : 8 : return -ENXIO;
4900 : : }
4901 : 12 : p += transfer;
4902 : 12 : offset += transfer;
4903 : 12 : size_remaining -= transfer;
4904 : : }
4905 : :
4906 : : /* Firmware commit */
4907 [ - + ]: 12 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
4908 : 12 : fw_commit.fs = slot;
4909 : 12 : fw_commit.ca = commit_action;
4910 : :
4911 [ - + ]: 12 : memset(status, 0, sizeof(*status));
4912 : 12 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
4913 : : status);
4914 [ + + ]: 12 : if (res) {
4915 : 4 : free(status);
4916 : 4 : return res;
4917 : : }
4918 : :
4919 : 8 : res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock);
4920 : :
4921 : 8 : memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status));
4922 : :
4923 [ + + + - ]: 8 : if (!status->timed_out) {
4924 : 8 : free(status);
4925 : : }
4926 : :
4927 [ + + ]: 8 : if (res) {
4928 [ - + ]: 4 : if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC ||
4929 [ # # ]: 0 : completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) {
4930 [ - + ]: 4 : if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
4931 [ # # ]: 0 : completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) {
4932 [ # # # # ]: 0 : NVME_CTRLR_NOTICELOG(ctrlr,
4933 : : "firmware activation requires conventional reset to be performed. !\n");
4934 : : } else {
4935 [ + - - + ]: 4 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
4936 : : }
4937 : 4 : return -ENXIO;
4938 : : }
4939 : : }
4940 : :
4941 : 4 : return spdk_nvme_ctrlr_reset(ctrlr);
4942 : : }
4943 : :
4944 : : int
4945 : 0 : spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr)
4946 : : {
4947 : : int rc, size;
4948 : : union spdk_nvme_cmbsz_register cmbsz;
4949 : :
4950 : 0 : cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
4951 : :
4952 [ # # # # ]: 0 : if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) {
4953 : 0 : return -ENOTSUP;
4954 : : }
4955 : :
4956 [ # # ]: 0 : size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4));
4957 : :
4958 : 0 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4959 : 0 : rc = nvme_transport_ctrlr_reserve_cmb(ctrlr);
4960 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4961 : :
4962 [ # # ]: 0 : if (rc < 0) {
4963 : 0 : return rc;
4964 : : }
4965 : :
4966 : 0 : return size;
4967 : : }
4968 : :
4969 : : void *
4970 : 10 : spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
4971 : : {
4972 : : void *buf;
4973 : :
4974 : 10 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4975 : 10 : buf = nvme_transport_ctrlr_map_cmb(ctrlr, size);
4976 : 10 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4977 : :
4978 : 10 : return buf;
4979 : : }
4980 : :
4981 : : void
4982 : 2 : spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
4983 : : {
4984 : 2 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4985 : 2 : nvme_transport_ctrlr_unmap_cmb(ctrlr);
4986 : 2 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4987 : 2 : }
4988 : :
4989 : : int
4990 : 44 : spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
4991 : : {
4992 : : int rc;
4993 : :
4994 : 44 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4995 : 44 : rc = nvme_transport_ctrlr_enable_pmr(ctrlr);
4996 : 44 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4997 : :
4998 : 44 : return rc;
4999 : : }
5000 : :
5001 : : int
5002 : 44 : spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
5003 : : {
5004 : : int rc;
5005 : :
5006 : 44 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
5007 : 44 : rc = nvme_transport_ctrlr_disable_pmr(ctrlr);
5008 : 44 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5009 : :
5010 : 44 : return rc;
5011 : : }
5012 : :
5013 : : void *
5014 : 44 : spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5015 : : {
5016 : : void *buf;
5017 : :
5018 : 44 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
5019 : 44 : buf = nvme_transport_ctrlr_map_pmr(ctrlr, size);
5020 : 44 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5021 : :
5022 : 44 : return buf;
5023 : : }
5024 : :
5025 : : int
5026 : 44 : spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
5027 : : {
5028 : : int rc;
5029 : :
5030 : 44 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
5031 : 44 : rc = nvme_transport_ctrlr_unmap_pmr(ctrlr);
5032 : 44 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5033 : :
5034 : 44 : return rc;
5035 : : }
5036 : :
5037 : : int
5038 : 0 : spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload,
5039 : : uint32_t bprsz, uint32_t bprof, uint32_t bpid)
5040 : : {
5041 : 0 : union spdk_nvme_bprsel_register bprsel;
5042 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5043 : 0 : uint64_t bpmbl, bpmb_size;
5044 : :
5045 [ # # ]: 0 : if (ctrlr->cap.bits.bps == 0) {
5046 : 0 : return -ENOTSUP;
5047 : : }
5048 : :
5049 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5050 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5051 : 0 : return -EIO;
5052 : : }
5053 : :
5054 [ # # ]: 0 : if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) {
5055 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n");
5056 : 0 : return -EALREADY;
5057 : : }
5058 : :
5059 : 0 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
5060 : :
5061 : 0 : bpmb_size = bprsz * 4096;
5062 : 0 : bpmbl = spdk_vtophys(payload, &bpmb_size);
5063 [ # # ]: 0 : if (bpmbl == SPDK_VTOPHYS_ERROR) {
5064 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n");
5065 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5066 : 0 : return -EFAULT;
5067 : : }
5068 : :
5069 [ # # ]: 0 : if (bpmb_size != bprsz * 4096) {
5070 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n");
5071 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5072 : 0 : return -EFAULT;
5073 : : }
5074 : :
5075 [ # # ]: 0 : if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) {
5076 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n");
5077 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5078 : 0 : return -EIO;
5079 : : }
5080 : :
5081 : 0 : bprsel.bits.bpid = bpid;
5082 : 0 : bprsel.bits.bprof = bprof;
5083 : 0 : bprsel.bits.bprsz = bprsz;
5084 : :
5085 [ # # ]: 0 : if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) {
5086 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n");
5087 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5088 : 0 : return -EIO;
5089 : : }
5090 : :
5091 : 0 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5092 : 0 : return 0;
5093 : : }
5094 : :
5095 : : int
5096 : 0 : spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr)
5097 : : {
5098 : 0 : int rc = 0;
5099 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5100 : :
5101 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5102 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5103 : 0 : return -EIO;
5104 : : }
5105 : :
5106 [ # # # # : 0 : switch (bpinfo.bits.brs) {
# ]
5107 : 0 : case SPDK_NVME_BRS_NO_READ:
5108 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n");
5109 : 0 : rc = -EINVAL;
5110 : 0 : break;
5111 : 0 : case SPDK_NVME_BRS_READ_IN_PROGRESS:
5112 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n");
# # # # ]
5113 : 0 : rc = -EAGAIN;
5114 : 0 : break;
5115 : 0 : case SPDK_NVME_BRS_READ_ERROR:
5116 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n");
5117 : 0 : rc = -EIO;
5118 : 0 : break;
5119 : 0 : case SPDK_NVME_BRS_READ_SUCCESS:
5120 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n");
# # # # ]
5121 : 0 : break;
5122 : 0 : default:
5123 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n");
5124 : 0 : rc = -EINVAL;
5125 : : }
5126 : :
5127 : 0 : return rc;
5128 : : }
5129 : :
5130 : : static void
5131 : 0 : nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl)
5132 : : {
5133 : : int res;
5134 : 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
5135 : 0 : struct spdk_nvme_fw_commit fw_commit;
5136 : 0 : struct spdk_nvme_cpl err_cpl =
5137 : : {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }};
5138 : :
5139 [ # # # # ]: 0 : if (spdk_nvme_cpl_is_error(cpl)) {
5140 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n");
5141 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5142 : 0 : return;
5143 : : }
5144 : :
5145 [ # # ]: 0 : if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) {
5146 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset);
# # # # ]
5147 : 0 : ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size;
5148 : 0 : ctrlr->fw_offset += ctrlr->fw_transfer_size;
5149 : 0 : ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size;
5150 : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5151 : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5152 : : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5153 [ # # ]: 0 : if (res) {
5154 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n");
5155 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5156 : 0 : return;
5157 : : }
5158 : :
5159 [ # # ]: 0 : if (ctrlr->fw_transfer_size < ctrlr->min_page_size) {
5160 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED;
5161 : : }
5162 [ # # ]: 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) {
5163 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n");
# # # # ]
5164 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5165 : 0 : fw_commit.bpid = ctrlr->bpid;
5166 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION;
5167 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5168 : : nvme_write_boot_partition_cb, ctrlr);
5169 [ # # ]: 0 : if (res) {
5170 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5171 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5172 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5173 : 0 : return;
5174 : : }
5175 : :
5176 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE;
5177 [ # # ]: 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) {
5178 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n");
# # # # ]
5179 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5180 : 0 : fw_commit.bpid = ctrlr->bpid;
5181 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION;
5182 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5183 : : nvme_write_boot_partition_cb, ctrlr);
5184 [ # # ]: 0 : if (res) {
5185 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5186 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5187 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5188 : 0 : return;
5189 : : }
5190 : :
5191 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE;
5192 [ # # ]: 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) {
5193 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n");
# # # # ]
5194 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5195 : : } else {
5196 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n");
5197 : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5198 : 0 : return;
5199 : : }
5200 : : }
5201 : :
5202 : : int
5203 : 0 : spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr,
5204 : : void *payload, uint32_t size, uint32_t bpid,
5205 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
5206 : : {
5207 : : int res;
5208 : :
5209 [ # # ]: 0 : if (ctrlr->cap.bits.bps == 0) {
5210 : 0 : return -ENOTSUP;
5211 : : }
5212 : :
5213 : 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING;
5214 : 0 : ctrlr->bpid = bpid;
5215 : 0 : ctrlr->bp_write_cb_fn = cb_fn;
5216 : 0 : ctrlr->bp_write_cb_arg = cb_arg;
5217 : 0 : ctrlr->fw_offset = 0;
5218 : 0 : ctrlr->fw_size_remaining = size;
5219 : 0 : ctrlr->fw_payload = payload;
5220 : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5221 : :
5222 : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5223 : : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5224 : :
5225 : 0 : return res;
5226 : : }
5227 : :
5228 : : bool
5229 : 6439 : spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr)
5230 : : {
5231 [ - + ]: 6439 : assert(ctrlr);
5232 : :
5233 [ - + ]: 6439 : return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN,
5234 : : strlen(SPDK_NVMF_DISCOVERY_NQN));
5235 : : }
5236 : :
5237 : : bool
5238 : 3006 : spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr)
5239 : : {
5240 [ - + ]: 3006 : assert(ctrlr);
5241 : :
5242 : 3006 : return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype);
5243 : : }
5244 : :
5245 : : int
5246 : 42 : spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5247 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5248 : : {
5249 : : struct nvme_completion_poll_status *status;
5250 : : int res;
5251 : :
5252 : 42 : status = calloc(1, sizeof(*status));
5253 [ - + ]: 42 : if (!status) {
5254 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5255 : 0 : return -ENOMEM;
5256 : : }
5257 : :
5258 : 42 : res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size,
5259 : : nvme_completion_poll_cb, status);
5260 [ - + ]: 42 : if (res) {
5261 : 0 : free(status);
5262 : 0 : return res;
5263 : : }
5264 [ - + ]: 42 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5265 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n");
5266 [ # # # # ]: 0 : if (!status->timed_out) {
5267 : 0 : free(status);
5268 : : }
5269 : 0 : return -ENXIO;
5270 : : }
5271 : 42 : free(status);
5272 : :
5273 : 42 : return 0;
5274 : : }
5275 : :
5276 : : int
5277 : 0 : spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5278 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5279 : : {
5280 : : struct nvme_completion_poll_status *status;
5281 : : int res;
5282 : :
5283 : 0 : status = calloc(1, sizeof(*status));
5284 [ # # ]: 0 : if (!status) {
5285 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5286 : 0 : return -ENOMEM;
5287 : : }
5288 : :
5289 : 0 : res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size,
5290 : : nvme_completion_poll_cb,
5291 : : status);
5292 [ # # ]: 0 : if (res) {
5293 : 0 : free(status);
5294 : 0 : return res;
5295 : : }
5296 [ # # ]: 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5297 [ # # # # ]: 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n");
5298 [ # # # # ]: 0 : if (!status->timed_out) {
5299 : 0 : free(status);
5300 : : }
5301 : 0 : return -ENXIO;
5302 : : }
5303 : :
5304 : 0 : free(status);
5305 : :
5306 : 0 : return 0;
5307 : : }
5308 : :
5309 : : uint64_t
5310 : 7029 : spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr)
5311 : : {
5312 : 7029 : return ctrlr->flags;
5313 : : }
5314 : :
5315 : : const struct spdk_nvme_transport_id *
5316 : 2006 : spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr)
5317 : : {
5318 : 2006 : return &ctrlr->trid;
5319 : : }
5320 : :
5321 : : int32_t
5322 : 4272 : spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr)
5323 : : {
5324 : : uint32_t qid;
5325 : :
5326 [ - + ]: 4272 : assert(ctrlr->free_io_qids);
5327 : 4272 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
5328 : 4272 : qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
5329 [ + + ]: 4272 : if (qid > ctrlr->opts.num_io_queues) {
5330 [ + - - + ]: 9 : NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n");
5331 : 9 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5332 : 9 : return -1;
5333 : : }
5334 : :
5335 : 4263 : spdk_bit_array_clear(ctrlr->free_io_qids, qid);
5336 : 4263 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5337 : 4263 : return qid;
5338 : : }
5339 : :
5340 : : void
5341 : 232726 : spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid)
5342 : : {
5343 [ - + ]: 232726 : assert(qid <= ctrlr->opts.num_io_queues);
5344 : :
5345 : 232726 : nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
5346 : :
5347 [ + + ]: 232726 : if (spdk_likely(ctrlr->free_io_qids)) {
5348 : 232709 : spdk_bit_array_set(ctrlr->free_io_qids, qid);
5349 : : }
5350 : :
5351 : 232726 : nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
5352 : 232726 : }
5353 : :
5354 : : int
5355 : 8809 : spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
5356 : : struct spdk_memory_domain **domains, int array_size)
5357 : : {
5358 : 8809 : return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size);
5359 : : }
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