LCOV - code coverage report
Current view: top level - spdk/test/unit/lib/nvme/nvme_ctrlr.c - nvme_ctrlr_ut.c (source / functions) Hit Total Coverage
Test: Combined Lines: 1910 1975 96.7 %
Date: 2024-07-11 01:03:03 Functions: 99 123 80.5 %
Legend: Lines: hit not hit | Branches: + taken - not taken # not executed Branches: 371 569 65.2 %

           Branch data     Line data    Source code
       1                 :            : /*   SPDX-License-Identifier: BSD-3-Clause
       2                 :            :  *   Copyright (C) 2015 Intel Corporation. All rights reserved.
       3                 :            :  *   Copyright (c) 2020, 2021 Mellanox Technologies LTD. All rights reserved.
       4                 :            :  *   Copyright (c) 2021, 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
       5                 :            :  */
       6                 :            : 
       7                 :            : #include "spdk/stdinc.h"
       8                 :            : 
       9                 :            : #include "spdk_internal/cunit.h"
      10                 :            : 
      11                 :            : #include "spdk/log.h"
      12                 :            : 
      13                 :            : #include "common/lib/test_env.c"
      14                 :            : 
      15                 :            : #include "nvme/nvme_ctrlr.c"
      16                 :            : #include "nvme/nvme_quirks.c"
      17                 :            : 
      18                 :          4 : SPDK_LOG_REGISTER_COMPONENT(nvme)
      19                 :            : 
      20                 :            : pid_t g_spdk_nvme_pid;
      21                 :            : 
      22                 :            : struct nvme_driver _g_nvme_driver = {
      23                 :            :         .lock = PTHREAD_MUTEX_INITIALIZER,
      24                 :            : };
      25                 :            : 
      26                 :            : struct nvme_driver *g_spdk_nvme_driver = &_g_nvme_driver;
      27                 :            : 
      28                 :            : struct spdk_nvme_registers g_ut_nvme_regs = {};
      29                 :            : typedef void (*set_reg_cb)(void);
      30                 :            : set_reg_cb g_set_reg_cb;
      31                 :            : 
      32                 :            : __thread int    nvme_thread_ioq_index = -1;
      33                 :            : 
      34                 :            : uint32_t set_size = 1;
      35                 :            : 
      36                 :            : int set_status_cpl = -1;
      37                 :            : 
      38                 :          0 : DEFINE_STUB(nvme_ctrlr_cmd_set_host_id, int,
      39                 :            :             (struct spdk_nvme_ctrlr *ctrlr, void *host_id, uint32_t host_id_size,
      40                 :            :              spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0);
      41                 :         84 : DEFINE_STUB_V(nvme_ns_set_identify_data, (struct spdk_nvme_ns *ns));
      42                 :         24 : DEFINE_STUB_V(nvme_ns_set_id_desc_list_data, (struct spdk_nvme_ns *ns));
      43                 :         16 : DEFINE_STUB_V(nvme_ns_free_iocs_specific_data, (struct spdk_nvme_ns *ns));
      44                 :         56 : DEFINE_STUB_V(nvme_qpair_abort_all_queued_reqs, (struct spdk_nvme_qpair *qpair));
      45                 :          0 : DEFINE_STUB(spdk_nvme_poll_group_remove, int, (struct spdk_nvme_poll_group *group,
      46                 :            :                 struct spdk_nvme_qpair *qpair), 0);
      47                 :         20 : DEFINE_STUB_V(nvme_io_msg_ctrlr_update, (struct spdk_nvme_ctrlr *ctrlr));
      48                 :          4 : DEFINE_STUB(nvme_io_msg_process, int, (struct spdk_nvme_ctrlr *ctrlr), 0);
      49                 :          0 : DEFINE_STUB(nvme_transport_ctrlr_reserve_cmb, int, (struct spdk_nvme_ctrlr *ctrlr), 0);
      50                 :          0 : DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_receive, int, (struct spdk_nvme_ctrlr *ctrlr,
      51                 :            :                 uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload,
      52                 :            :                 uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0);
      53                 :          0 : DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_send, int, (struct spdk_nvme_ctrlr *ctrlr,
      54                 :            :                 uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload,
      55                 :            :                 uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0);
      56                 :         84 : DEFINE_STUB_V(nvme_qpair_abort_queued_reqs, (struct spdk_nvme_qpair *qpair));
      57                 :            : 
      58                 :            : DEFINE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains, int);
      59                 :            : int
      60                 :          8 : nvme_transport_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
      61                 :            :                                         struct spdk_memory_domain **domains, int array_size)
      62                 :            : {
      63   [ +  +  +  - ]:          8 :         HANDLE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains);
      64                 :            : 
      65                 :          0 :         return 0;
      66                 :            : }
      67                 :            : 
      68                 :            : DEFINE_RETURN_MOCK(nvme_transport_ctrlr_ready, int);
      69                 :            : int
      70                 :         68 : nvme_transport_ctrlr_ready(struct spdk_nvme_ctrlr *ctrlr)
      71                 :            : {
      72   [ +  +  +  + ]:         68 :         HANDLE_RETURN_MOCK(nvme_transport_ctrlr_ready);
      73                 :         64 :         return 0;
      74                 :            : }
      75                 :            : 
      76                 :          0 : struct spdk_nvme_ctrlr *nvme_transport_ctrlr_construct(const struct spdk_nvme_transport_id *trid,
      77                 :            :                 const struct spdk_nvme_ctrlr_opts *opts,
      78                 :            :                 void *devhandle)
      79                 :            : {
      80                 :          0 :         return NULL;
      81                 :            : }
      82                 :            : 
      83                 :            : int
      84                 :        184 : nvme_transport_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
      85                 :            : {
      86                 :        184 :         nvme_ctrlr_destruct_finish(ctrlr);
      87                 :            : 
      88                 :        184 :         return 0;
      89                 :            : }
      90                 :            : 
      91                 :            : int
      92                 :         84 : nvme_transport_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
      93                 :            : {
      94                 :         84 :         return 0;
      95                 :            : }
      96                 :            : 
      97                 :            : int
      98                 :        216 : nvme_transport_ctrlr_set_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value)
      99                 :            : {
     100         [ -  + ]:        216 :         SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4);
     101                 :        216 :         *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value;
     102         [ +  + ]:        216 :         if (g_set_reg_cb) {
     103                 :          4 :                 g_set_reg_cb();
     104                 :            :         }
     105                 :        216 :         return 0;
     106                 :            : }
     107                 :            : 
     108                 :            : int
     109                 :          0 : nvme_transport_ctrlr_set_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value)
     110                 :            : {
     111         [ #  # ]:          0 :         SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8);
     112                 :          0 :         *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value;
     113         [ #  # ]:          0 :         if (g_set_reg_cb) {
     114                 :          0 :                 g_set_reg_cb();
     115                 :            :         }
     116                 :          0 :         return 0;
     117                 :            : }
     118                 :            : 
     119                 :            : int
     120                 :        620 : nvme_transport_ctrlr_get_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value)
     121                 :            : {
     122         [ -  + ]:        620 :         SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4);
     123                 :        620 :         *value = *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset);
     124                 :        620 :         return 0;
     125                 :            : }
     126                 :            : 
     127                 :            : int
     128                 :         84 : nvme_transport_ctrlr_get_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value)
     129                 :            : {
     130         [ -  + ]:         84 :         SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8);
     131                 :         84 :         *value = *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset);
     132                 :         84 :         return 0;
     133                 :            : }
     134                 :            : 
     135                 :            : int
     136                 :        216 : nvme_transport_ctrlr_set_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
     137                 :            :                                      uint32_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg)
     138                 :            : {
     139                 :        216 :         struct spdk_nvme_cpl cpl = {};
     140                 :            : 
     141                 :        216 :         cpl.status.sct = SPDK_NVME_SCT_GENERIC;
     142                 :        216 :         cpl.status.sc = SPDK_NVME_SC_SUCCESS;
     143                 :            : 
     144                 :        216 :         nvme_transport_ctrlr_set_reg_4(ctrlr, offset, value);
     145                 :        216 :         cb_fn(cb_arg, value, &cpl);
     146                 :        216 :         return 0;
     147                 :            : }
     148                 :            : 
     149                 :            : int
     150                 :          0 : nvme_transport_ctrlr_set_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
     151                 :            :                                      uint64_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg)
     152                 :            : {
     153                 :          0 :         struct spdk_nvme_cpl cpl = {};
     154                 :            : 
     155                 :          0 :         cpl.status.sct = SPDK_NVME_SCT_GENERIC;
     156                 :          0 :         cpl.status.sc = SPDK_NVME_SC_SUCCESS;
     157                 :            : 
     158                 :          0 :         nvme_transport_ctrlr_set_reg_8(ctrlr, offset, value);
     159                 :          0 :         cb_fn(cb_arg, value, &cpl);
     160                 :          0 :         return 0;
     161                 :            : }
     162                 :            : 
     163                 :            : int
     164                 :        616 : nvme_transport_ctrlr_get_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
     165                 :            :                                      spdk_nvme_reg_cb cb_fn, void *cb_arg)
     166                 :            : {
     167                 :        616 :         struct spdk_nvme_cpl cpl = {};
     168                 :        616 :         uint32_t value;
     169                 :            : 
     170                 :        616 :         cpl.status.sct = SPDK_NVME_SCT_GENERIC;
     171                 :        616 :         cpl.status.sc = SPDK_NVME_SC_SUCCESS;
     172                 :            : 
     173                 :        616 :         nvme_transport_ctrlr_get_reg_4(ctrlr, offset, &value);
     174                 :        616 :         cb_fn(cb_arg, value, &cpl);
     175                 :        616 :         return 0;
     176                 :            : }
     177                 :            : 
     178                 :            : int
     179                 :         84 : nvme_transport_ctrlr_get_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset,
     180                 :            :                                      spdk_nvme_reg_cb cb_fn, void *cb_arg)
     181                 :            : {
     182                 :         84 :         struct spdk_nvme_cpl cpl = {};
     183                 :         84 :         uint64_t value;
     184                 :            : 
     185                 :         84 :         cpl.status.sct = SPDK_NVME_SCT_GENERIC;
     186                 :         84 :         cpl.status.sc = SPDK_NVME_SC_SUCCESS;
     187                 :            : 
     188                 :         84 :         nvme_transport_ctrlr_get_reg_8(ctrlr, offset, &value);
     189                 :         84 :         cb_fn(cb_arg, value, &cpl);
     190                 :         84 :         return 0;
     191                 :            : }
     192                 :            : 
     193                 :            : uint32_t
     194                 :         64 : nvme_transport_ctrlr_get_max_xfer_size(struct spdk_nvme_ctrlr *ctrlr)
     195                 :            : {
     196                 :         64 :         return UINT32_MAX;
     197                 :            : }
     198                 :            : 
     199                 :            : uint16_t
     200                 :          0 : nvme_transport_ctrlr_get_max_sges(struct spdk_nvme_ctrlr *ctrlr)
     201                 :            : {
     202                 :          0 :         return 1;
     203                 :            : }
     204                 :            : 
     205                 :            : void *
     206                 :          0 : nvme_transport_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
     207                 :            : {
     208                 :          0 :         return NULL;
     209                 :            : }
     210                 :            : 
     211                 :            : int
     212                 :          0 : nvme_transport_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
     213                 :            : {
     214                 :          0 :         return 0;
     215                 :            : }
     216                 :            : 
     217                 :            : int
     218                 :          0 : nvme_transport_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
     219                 :            : {
     220                 :          0 :         return 0;
     221                 :            : }
     222                 :            : 
     223                 :            : int
     224                 :          0 : nvme_transport_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
     225                 :            : {
     226                 :          0 :         return 0;
     227                 :            : }
     228                 :            : 
     229                 :            : void *
     230                 :          0 : nvme_transport_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
     231                 :            : {
     232                 :          0 :         return NULL;
     233                 :            : }
     234                 :            : 
     235                 :            : int
     236                 :          0 : nvme_transport_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
     237                 :            : {
     238                 :          0 :         return 0;
     239                 :            : }
     240                 :            : 
     241                 :            : struct spdk_nvme_qpair *
     242                 :         60 : nvme_transport_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid,
     243                 :            :                                      const struct spdk_nvme_io_qpair_opts *opts)
     244                 :            : {
     245                 :            :         struct spdk_nvme_qpair *qpair;
     246                 :            : 
     247                 :         60 :         qpair = calloc(1, sizeof(*qpair));
     248         [ -  + ]:         60 :         SPDK_CU_ASSERT_FATAL(qpair != NULL);
     249                 :            : 
     250                 :         60 :         qpair->ctrlr = ctrlr;
     251                 :         60 :         qpair->id = qid;
     252                 :         60 :         qpair->qprio = opts->qprio;
     253                 :            : 
     254                 :         60 :         return qpair;
     255                 :            : }
     256                 :            : 
     257                 :            : void
     258                 :         60 : nvme_transport_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
     259                 :            : {
     260                 :         60 :         free(qpair);
     261                 :         60 : }
     262                 :            : 
     263                 :            : void
     264                 :        248 : nvme_transport_ctrlr_disconnect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
     265                 :            : {
     266                 :        248 : }
     267                 :            : 
     268                 :            : int
     269                 :         36 : nvme_transport_qpair_reset(struct spdk_nvme_qpair *qpair)
     270                 :            : {
     271                 :         36 :         return 0;
     272                 :            : }
     273                 :            : 
     274                 :            : void
     275                 :        188 : nvme_transport_admin_qpair_abort_aers(struct spdk_nvme_qpair *qpair)
     276                 :            : {
     277                 :        188 : }
     278                 :            : 
     279                 :            : void
     280                 :          0 : nvme_transport_qpair_abort_reqs(struct spdk_nvme_qpair *qpair)
     281                 :            : {
     282                 :          0 : }
     283                 :            : 
     284                 :            : int
     285                 :          8 : nvme_driver_init(void)
     286                 :            : {
     287                 :          8 :         return 0;
     288                 :            : }
     289                 :            : 
     290                 :            : int
     291                 :          0 : nvme_qpair_init(struct spdk_nvme_qpair *qpair, uint16_t id,
     292                 :            :                 struct spdk_nvme_ctrlr *ctrlr,
     293                 :            :                 enum spdk_nvme_qprio qprio,
     294                 :            :                 uint32_t num_requests, bool async)
     295                 :            : {
     296                 :          0 :         qpair->id = id;
     297                 :          0 :         qpair->qprio = qprio;
     298                 :          0 :         qpair->ctrlr = ctrlr;
     299                 :          0 :         qpair->async = async;
     300                 :            : 
     301                 :          0 :         return 0;
     302                 :            : }
     303                 :            : 
     304                 :            : static struct spdk_nvme_cpl fake_cpl = {};
     305                 :            : static enum spdk_nvme_generic_command_status_code set_status_code = SPDK_NVME_SC_SUCCESS;
     306                 :            : 
     307                 :            : static void
     308                 :        500 : fake_cpl_sc(spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     309                 :            : {
     310                 :        500 :         fake_cpl.status.sc = set_status_code;
     311                 :        500 :         cb_fn(cb_arg, &fake_cpl);
     312                 :        500 : }
     313                 :            : 
     314                 :            : static uint32_t g_ut_cdw11;
     315                 :            : 
     316                 :            : int
     317                 :          4 : spdk_nvme_ctrlr_cmd_set_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature,
     318                 :            :                                 uint32_t cdw11, uint32_t cdw12, void *payload, uint32_t payload_size,
     319                 :            :                                 spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     320                 :            : {
     321                 :          4 :         g_ut_cdw11 = cdw11;
     322                 :          4 :         return 0;
     323                 :            : }
     324                 :            : 
     325                 :            : int
     326                 :         12 : spdk_nvme_ctrlr_cmd_get_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature,
     327                 :            :                                 uint32_t cdw11, void *payload, uint32_t payload_size,
     328                 :            :                                 spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     329                 :            : {
     330                 :         12 :         fake_cpl_sc(cb_fn, cb_arg);
     331                 :         12 :         return 0;
     332                 :            : }
     333                 :            : 
     334                 :            : struct spdk_nvme_ana_page *g_ana_hdr;
     335                 :            : struct spdk_nvme_ana_group_descriptor **g_ana_descs;
     336                 :            : 
     337                 :            : int
     338                 :         36 : spdk_nvme_ctrlr_cmd_get_log_page(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page,
     339                 :            :                                  uint32_t nsid, void *payload, uint32_t payload_size,
     340                 :            :                                  uint64_t offset, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     341                 :            : {
     342   [ +  +  +  + ]:         44 :         if ((log_page == SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS) && g_ana_hdr) {
     343                 :            :                 uint32_t i;
     344                 :          8 :                 uint8_t *ptr = payload;
     345                 :            : 
     346         [ -  + ]:          8 :                 memset(payload, 0, payload_size);
     347                 :          8 :                 memcpy(ptr, g_ana_hdr, sizeof(*g_ana_hdr));
     348                 :          8 :                 ptr += sizeof(*g_ana_hdr);
     349         [ +  + ]:         16 :                 for (i = 0; i < g_ana_hdr->num_ana_group_desc; ++i) {
     350                 :          8 :                         uint32_t desc_size = sizeof(**g_ana_descs) +
     351                 :          8 :                                              g_ana_descs[i]->num_of_nsid * sizeof(uint32_t);
     352   [ -  +  -  + ]:          8 :                         memcpy(ptr, g_ana_descs[i], desc_size);
     353                 :          8 :                         ptr += desc_size;
     354                 :            :                 }
     355         [ +  + ]:         28 :         } else if (log_page == SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY) {
     356                 :          4 :                 struct spdk_nvme_intel_log_page_directory *log_page_directory = payload;
     357                 :          4 :                 log_page_directory->read_latency_log_len = true;
     358                 :          4 :                 log_page_directory->write_latency_log_len = true;
     359                 :          4 :                 log_page_directory->temperature_statistics_log_len = true;
     360                 :          4 :                 log_page_directory->smart_log_len = true;
     361                 :          4 :                 log_page_directory->marketing_description_log_len =  true;
     362                 :            :         }
     363                 :            : 
     364                 :         36 :         fake_cpl_sc(cb_fn, cb_arg);
     365                 :         36 :         return 0;
     366                 :            : }
     367                 :            : 
     368                 :            : int
     369                 :          0 : spdk_nvme_ctrlr_cmd_get_log_page_ext(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page,
     370                 :            :                                      uint32_t nsid, void *payload, uint32_t payload_size,
     371                 :            :                                      uint64_t offset, uint32_t cdw10, uint32_t cdw11,
     372                 :            :                                      uint32_t cdw14, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     373                 :            : {
     374                 :          0 :         fake_cpl_sc(cb_fn, cb_arg);
     375                 :          0 :         return 0;
     376                 :            : }
     377                 :            : 
     378                 :            : int
     379                 :         96 : nvme_qpair_submit_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req)
     380                 :            : {
     381                 :         96 :         CU_ASSERT(req->cmd.opc == SPDK_NVME_OPC_ASYNC_EVENT_REQUEST);
     382         [ +  + ]:         96 :         STAILQ_INSERT_HEAD(&qpair->free_req, req, stailq);
     383                 :            : 
     384                 :            :         /*
     385                 :            :          * For the purposes of this unit test, we don't need to bother emulating request submission.
     386                 :            :          */
     387                 :            : 
     388                 :         96 :         return 0;
     389                 :            : }
     390                 :            : 
     391                 :            : static int32_t g_wait_for_completion_return_val;
     392                 :            : 
     393                 :            : int32_t
     394                 :        352 : spdk_nvme_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_completions)
     395                 :            : {
     396                 :        352 :         return g_wait_for_completion_return_val;
     397                 :            : }
     398                 :            : 
     399                 :            : void
     400                 :          0 : nvme_qpair_complete_error_reqs(struct spdk_nvme_qpair *qpair)
     401                 :            : {
     402                 :          0 : }
     403                 :            : 
     404                 :            : 
     405                 :            : void
     406                 :         36 : nvme_completion_poll_cb(void *arg, const struct spdk_nvme_cpl *cpl)
     407                 :            : {
     408                 :         36 :         struct nvme_completion_poll_status      *status = arg;
     409                 :            :         /* This should not happen it test env since this callback is always called
     410                 :            :          * before wait_for_completion_* while this field can only be set to true in
     411                 :            :          * wait_for_completion_* functions */
     412         [ -  + ]:         36 :         CU_ASSERT(status->timed_out == false);
     413                 :            : 
     414                 :         36 :         status->cpl = *cpl;
     415                 :         36 :         status->done = true;
     416                 :         36 : }
     417                 :            : 
     418                 :            : static struct nvme_completion_poll_status *g_failed_status;
     419                 :            : 
     420                 :            : int
     421                 :         80 : nvme_wait_for_completion_robust_lock_timeout(
     422                 :            :         struct spdk_nvme_qpair *qpair,
     423                 :            :         struct nvme_completion_poll_status *status,
     424                 :            :         pthread_mutex_t *robust_mutex,
     425                 :            :         uint64_t timeout_in_usecs)
     426                 :            : {
     427         [ +  + ]:         80 :         if (spdk_nvme_qpair_process_completions(qpair, 0) < 0) {
     428                 :          4 :                 g_failed_status = status;
     429                 :          4 :                 status->timed_out = true;
     430                 :          4 :                 return -1;
     431                 :            :         }
     432                 :            : 
     433                 :         76 :         status->done = true;
     434         [ +  + ]:         76 :         if (set_status_cpl == 1) {
     435                 :          8 :                 status->cpl.status.sc = 1;
     436                 :            :         }
     437   [ +  +  -  + ]:         76 :         return spdk_nvme_cpl_is_error(&status->cpl) ? -EIO : 0;
     438                 :            : }
     439                 :            : 
     440                 :            : int
     441                 :         44 : nvme_wait_for_completion_robust_lock(
     442                 :            :         struct spdk_nvme_qpair *qpair,
     443                 :            :         struct nvme_completion_poll_status *status,
     444                 :            :         pthread_mutex_t *robust_mutex)
     445                 :            : {
     446                 :         44 :         return nvme_wait_for_completion_robust_lock_timeout(qpair, status, robust_mutex, 0);
     447                 :            : }
     448                 :            : 
     449                 :            : int
     450                 :          0 : nvme_wait_for_completion(struct spdk_nvme_qpair *qpair,
     451                 :            :                          struct nvme_completion_poll_status *status)
     452                 :            : {
     453                 :          0 :         return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, 0);
     454                 :            : }
     455                 :            : 
     456                 :            : int
     457                 :         20 : nvme_wait_for_completion_timeout(struct spdk_nvme_qpair *qpair,
     458                 :            :                                  struct nvme_completion_poll_status *status,
     459                 :            :                                  uint64_t timeout_in_usecs)
     460                 :            : {
     461                 :         20 :         return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, timeout_in_usecs);
     462                 :            : }
     463                 :            : 
     464                 :            : int
     465                 :         76 : nvme_ctrlr_cmd_set_async_event_config(struct spdk_nvme_ctrlr *ctrlr,
     466                 :            :                                       union spdk_nvme_feat_async_event_configuration config, spdk_nvme_cmd_cb cb_fn,
     467                 :            :                                       void *cb_arg)
     468                 :            : {
     469                 :         76 :         fake_cpl_sc(cb_fn, cb_arg);
     470                 :         76 :         return 0;
     471                 :            : }
     472                 :            : 
     473                 :            : static uint32_t *g_active_ns_list = NULL;
     474                 :            : static uint32_t g_active_ns_list_length = 0;
     475                 :            : static struct spdk_nvme_ctrlr_data *g_cdata = NULL;
     476                 :            : static bool g_fail_next_identify = false;
     477                 :            : 
     478                 :            : int
     479                 :        300 : nvme_ctrlr_cmd_identify(struct spdk_nvme_ctrlr *ctrlr, uint8_t cns, uint16_t cntid, uint32_t nsid,
     480                 :            :                         uint8_t csi, void *payload, size_t payload_size,
     481                 :            :                         spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     482                 :            : {
     483   [ +  +  +  + ]:        300 :         if (g_fail_next_identify) {
     484                 :          4 :                 g_fail_next_identify = false;
     485                 :          4 :                 return 1;
     486                 :            :         }
     487                 :            : 
     488         [ -  + ]:        296 :         memset(payload, 0, payload_size);
     489         [ +  + ]:        296 :         if (cns == SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST) {
     490                 :        120 :                 uint32_t count = 0;
     491                 :        120 :                 uint32_t i = 0;
     492                 :        120 :                 struct spdk_nvme_ns_list *ns_list = (struct spdk_nvme_ns_list *)payload;
     493                 :            : 
     494         [ +  + ]:        120 :                 if (g_active_ns_list == NULL) {
     495         [ +  + ]:         12 :                         for (i = 1; i <= ctrlr->cdata.nn; i++) {
     496         [ -  + ]:          8 :                                 if (i <= nsid) {
     497                 :          0 :                                         continue;
     498                 :            :                                 }
     499                 :            : 
     500                 :          8 :                                 ns_list->ns_list[count++] = i;
     501         [ -  + ]:          8 :                                 if (count == SPDK_COUNTOF(ns_list->ns_list)) {
     502                 :          0 :                                         break;
     503                 :            :                                 }
     504                 :            :                         }
     505                 :            :                 } else {
     506         [ +  + ]:      57572 :                         for (i = 0; i < g_active_ns_list_length; i++) {
     507                 :      57476 :                                 uint32_t cur_nsid = g_active_ns_list[i];
     508         [ +  + ]:      57476 :                                 if (cur_nsid <= nsid) {
     509                 :      24580 :                                         continue;
     510                 :            :                                 }
     511                 :            : 
     512                 :      32896 :                                 ns_list->ns_list[count++] = cur_nsid;
     513         [ +  + ]:      32896 :                                 if (count == SPDK_COUNTOF(ns_list->ns_list)) {
     514                 :         20 :                                         break;
     515                 :            :                                 }
     516                 :            :                         }
     517                 :            :                 }
     518         [ +  + ]:        176 :         } else if (cns == SPDK_NVME_IDENTIFY_CTRLR) {
     519         [ +  + ]:         64 :                 if (g_cdata) {
     520   [ -  +  -  + ]:         28 :                         memcpy(payload, g_cdata, sizeof(*g_cdata));
     521                 :            :                 }
     522         [ +  + ]:        112 :         } else if (cns == SPDK_NVME_IDENTIFY_NS_IOCS) {
     523                 :          4 :                 return 0;
     524                 :            :         }
     525                 :            : 
     526                 :        292 :         fake_cpl_sc(cb_fn, cb_arg);
     527                 :        292 :         return 0;
     528                 :            : }
     529                 :            : 
     530                 :            : int
     531                 :         76 : nvme_ctrlr_cmd_set_num_queues(struct spdk_nvme_ctrlr *ctrlr,
     532                 :            :                               uint32_t num_queues, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     533                 :            : {
     534                 :         76 :         fake_cpl_sc(cb_fn, cb_arg);
     535                 :         76 :         return 0;
     536                 :            : }
     537                 :            : 
     538                 :            : int
     539                 :          0 : nvme_ctrlr_cmd_get_num_queues(struct spdk_nvme_ctrlr *ctrlr,
     540                 :            :                               spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     541                 :            : {
     542                 :          0 :         CU_ASSERT(0);
     543                 :          0 :         return -1;
     544                 :            : }
     545                 :            : 
     546                 :            : int
     547                 :          4 : nvme_ctrlr_cmd_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
     548                 :            :                          struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     549                 :            : {
     550                 :          4 :         return 0;
     551                 :            : }
     552                 :            : 
     553                 :            : int
     554                 :          4 : nvme_ctrlr_cmd_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
     555                 :            :                          struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     556                 :            : {
     557                 :          4 :         return 0;
     558                 :            : }
     559                 :            : 
     560                 :            : int
     561                 :          4 : nvme_ctrlr_cmd_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload,
     562                 :            :                          spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     563                 :            : {
     564                 :          4 :         fake_cpl_sc(cb_fn, cb_arg);
     565                 :          4 :         return 0;
     566                 :            : }
     567                 :            : 
     568                 :            : int
     569                 :          4 : nvme_ctrlr_cmd_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, spdk_nvme_cmd_cb cb_fn,
     570                 :            :                          void *cb_arg)
     571                 :            : {
     572                 :          4 :         return 0;
     573                 :            : }
     574                 :            : 
     575                 :            : int
     576                 :          0 : nvme_ctrlr_cmd_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, struct spdk_nvme_format *format,
     577                 :            :                       spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     578                 :            : {
     579                 :          0 :         return 0;
     580                 :            : }
     581                 :            : 
     582                 :            : int
     583                 :          0 : spdk_nvme_ctrlr_cmd_directive_send(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
     584                 :            :                                    uint32_t doper, uint32_t dtype, uint32_t dspec,
     585                 :            :                                    void *payload, uint32_t payload_size, uint32_t cdw12,
     586                 :            :                                    uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     587                 :            : {
     588                 :          0 :         return 0;
     589                 :            : }
     590                 :            : 
     591                 :            : int
     592                 :          0 : spdk_nvme_ctrlr_cmd_directive_receive(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
     593                 :            :                                       uint32_t doper, uint32_t dtype, uint32_t dspec,
     594                 :            :                                       void *payload, uint32_t payload_size, uint32_t cdw12,
     595                 :            :                                       uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     596                 :            : {
     597                 :          0 :         return 0;
     598                 :            : }
     599                 :            : 
     600                 :            : int
     601                 :         12 : nvme_ctrlr_cmd_fw_commit(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_fw_commit *fw_commit,
     602                 :            :                          spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     603                 :            : {
     604                 :         12 :         CU_ASSERT(fw_commit->ca == SPDK_NVME_FW_COMMIT_REPLACE_IMG);
     605         [ +  + ]:         12 :         if (fw_commit->fs == 0) {
     606                 :          4 :                 return -1;
     607                 :            :         }
     608                 :          8 :         set_status_cpl = 1;
     609   [ +  +  +  + ]:          8 :         if (ctrlr->is_resetting == true) {
     610                 :          4 :                 set_status_cpl = 0;
     611                 :            :         }
     612                 :          8 :         return 0;
     613                 :            : }
     614                 :            : 
     615                 :            : int
     616                 :         28 : nvme_ctrlr_cmd_fw_image_download(struct spdk_nvme_ctrlr *ctrlr,
     617                 :            :                                  uint32_t size, uint32_t offset, void *payload,
     618                 :            :                                  spdk_nvme_cmd_cb cb_fn, void *cb_arg)
     619                 :            : {
     620   [ +  +  +  +  :         28 :         if ((size != 0 && payload == NULL) || (size == 0 && payload != NULL)) {
             +  +  +  - ]
     621                 :          8 :                 return -1;
     622                 :            :         }
     623                 :         20 :         CU_ASSERT(offset == 0);
     624                 :         20 :         return 0;
     625                 :            : }
     626                 :            : 
     627                 :            : bool
     628                 :         40 : nvme_ns_has_supported_iocs_specific_data(struct spdk_nvme_ns *ns)
     629                 :            : {
     630      [ +  +  - ]:         40 :         switch (ns->csi) {
     631                 :         32 :         case SPDK_NVME_CSI_NVM:
     632                 :            :                 /*
     633                 :            :                  * NVM Command Set Specific Identify Namespace data structure
     634                 :            :                  * is currently all-zeroes, reserved for future use.
     635                 :            :                  */
     636                 :         32 :                 return false;
     637                 :          8 :         case SPDK_NVME_CSI_ZNS:
     638                 :          8 :                 return true;
     639                 :          0 :         default:
     640                 :          0 :                 SPDK_WARNLOG("Unsupported CSI: %u for NSID: %u\n", ns->csi, ns->id);
     641                 :          0 :                 return false;
     642                 :            :         }
     643                 :            : }
     644                 :            : 
     645                 :            : void
     646                 :         24 : nvme_ns_free_zns_specific_data(struct spdk_nvme_ns *ns)
     647                 :            : {
     648         [ -  + ]:         24 :         if (!ns->id) {
     649                 :          0 :                 return;
     650                 :            :         }
     651                 :            : 
     652         [ +  + ]:         24 :         if (ns->nsdata_zns) {
     653                 :          8 :                 spdk_free(ns->nsdata_zns);
     654                 :          8 :                 ns->nsdata_zns = NULL;
     655                 :            :         }
     656                 :            : }
     657                 :            : 
     658                 :            : void
     659                 :      73612 : nvme_ns_destruct(struct spdk_nvme_ns *ns)
     660                 :            : {
     661                 :      73612 : }
     662                 :            : 
     663                 :            : int
     664                 :         64 : nvme_ns_construct(struct spdk_nvme_ns *ns, uint32_t id,
     665                 :            :                   struct spdk_nvme_ctrlr *ctrlr)
     666                 :            : {
     667                 :         64 :         return 0;
     668                 :            : }
     669                 :            : 
     670                 :            : void
     671                 :          4 : spdk_pci_device_detach(struct spdk_pci_device *device)
     672                 :            : {
     673                 :          4 : }
     674                 :            : 
     675                 :            : #define DECLARE_AND_CONSTRUCT_CTRLR()   \
     676                 :            :         struct spdk_nvme_ctrlr  ctrlr = {};     \
     677                 :            :         struct spdk_nvme_qpair  adminq = {};    \
     678                 :            :         struct nvme_request     req;            \
     679                 :            :                                                 \
     680                 :            :         STAILQ_INIT(&adminq.free_req);              \
     681                 :            :         STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq);     \
     682                 :            :         ctrlr.adminq = &adminq;                                     \
     683                 :            :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM;
     684                 :            : 
     685                 :            : static void
     686                 :          4 : test_nvme_ctrlr_init_en_1_rdy_0(void)
     687                 :            : {
     688         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
     689                 :            : 
     690                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
     691                 :            : 
     692                 :            :         /*
     693                 :            :          * Initial state: CC.EN = 1, CSTS.RDY = 0
     694                 :            :          */
     695                 :          4 :         g_ut_nvme_regs.cc.bits.en = 1;
     696                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     697                 :            : 
     698         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
     699                 :          4 :         ctrlr.cdata.nn = 1;
     700                 :          4 :         ctrlr.page_size = 0x1000;
     701                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
     702         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
     703                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     704                 :            :         }
     705                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     706                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1);
     707                 :            : 
     708                 :            :         /*
     709                 :            :          * Transition to CSTS.RDY = 1.
     710                 :            :          * init() should set CC.EN = 0.
     711                 :            :          */
     712                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
     713                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     714                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_EN_0);
     715                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     716                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
     717                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
     718                 :            : 
     719                 :            :         /*
     720                 :            :          * Transition to CSTS.RDY = 0.
     721                 :            :          */
     722                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     723                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     724                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
     725                 :            : 
     726                 :            :         /*
     727                 :            :          * Start enabling the controller.
     728                 :            :          */
     729                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     730                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
     731                 :            : 
     732                 :            :         /*
     733                 :            :          * Transition to CC.EN = 1
     734                 :            :          */
     735                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     736                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
     737                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
     738                 :            : 
     739                 :            :         /*
     740                 :            :          * Transition to CSTS.RDY = 1.
     741                 :            :          */
     742                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
     743                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     744                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
     745                 :            : 
     746                 :            :         /*
     747                 :            :          * Transition to READY.
     748                 :            :          */
     749         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
     750                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
     751                 :            :         }
     752                 :            : 
     753                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
     754                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
     755                 :          4 : }
     756                 :            : 
     757                 :            : static void
     758                 :          4 : test_nvme_ctrlr_init_en_1_rdy_1(void)
     759                 :            : {
     760         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
     761                 :            : 
     762                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
     763                 :            : 
     764                 :            :         /*
     765                 :            :          * Initial state: CC.EN = 1, CSTS.RDY = 1
     766                 :            :          * init() should set CC.EN = 0.
     767                 :            :          */
     768                 :          4 :         g_ut_nvme_regs.cc.bits.en = 1;
     769                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
     770                 :            : 
     771         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
     772                 :          4 :         ctrlr.cdata.nn = 1;
     773                 :          4 :         ctrlr.page_size = 0x1000;
     774                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
     775         [ +  + ]:         28 :         while (ctrlr.state != NVME_CTRLR_STATE_SET_EN_0) {
     776                 :         24 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     777                 :            :         }
     778                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     779                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
     780                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
     781                 :            : 
     782                 :            :         /*
     783                 :            :          * Transition to CSTS.RDY = 0.
     784                 :            :          */
     785                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     786                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     787                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
     788                 :            : 
     789                 :            :         /*
     790                 :            :          * Start enabling the controller.
     791                 :            :          */
     792                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     793                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
     794                 :            : 
     795                 :            :         /*
     796                 :            :          * Transition to CC.EN = 1
     797                 :            :          */
     798                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     799                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
     800                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
     801                 :            : 
     802                 :            :         /*
     803                 :            :          * Transition to CSTS.RDY = 1.
     804                 :            :          */
     805                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
     806                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     807                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
     808                 :            : 
     809                 :            :         /*
     810                 :            :          * Transition to READY.
     811                 :            :          */
     812         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
     813                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
     814                 :            :         }
     815                 :            : 
     816                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
     817                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
     818                 :          4 : }
     819                 :            : 
     820                 :            : static void
     821                 :          4 : test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void)
     822                 :            : {
     823         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
     824                 :            : 
     825                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
     826                 :            : 
     827                 :            :         /*
     828                 :            :          * Initial state: CC.EN = 0, CSTS.RDY = 0
     829                 :            :          * init() should set CC.EN = 1.
     830                 :            :          */
     831                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
     832                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     833                 :            : 
     834                 :            :         /*
     835                 :            :          * Default round robin enabled
     836                 :            :          */
     837                 :          4 :         g_ut_nvme_regs.cap.bits.ams = 0x0;
     838                 :          4 :         ctrlr.cap = g_ut_nvme_regs.cap;
     839                 :            : 
     840         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
     841                 :          4 :         ctrlr.cdata.nn = 1;
     842                 :          4 :         ctrlr.page_size = 0x1000;
     843                 :            :         /*
     844                 :            :          * Case 1: default round robin arbitration mechanism selected
     845                 :            :          */
     846                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
     847                 :            : 
     848                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
     849         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
     850                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     851                 :            :         }
     852                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     853                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
     854                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     855                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
     856                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     857                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
     858                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     859                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
     860                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
     861                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
     862                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
     863                 :            : 
     864                 :            :         /*
     865                 :            :          * Complete and destroy the controller
     866                 :            :          */
     867                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
     868                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
     869                 :            : 
     870                 :            :         /*
     871                 :            :          * Reset to initial state
     872                 :            :          */
     873                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
     874                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     875                 :            : 
     876                 :            :         /*
     877                 :            :          * Case 2: weighted round robin arbitration mechanism selected
     878                 :            :          */
     879         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
     880                 :          4 :         ctrlr.cdata.nn = 1;
     881                 :          4 :         ctrlr.page_size = 0x1000;
     882                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
     883                 :            : 
     884                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
     885         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
     886                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     887                 :            :         }
     888                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     889                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
     890                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     891                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
     892                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     893                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
     894                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
     895                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
     896                 :            : 
     897                 :            :         /*
     898                 :            :          * Complete and destroy the controller
     899                 :            :          */
     900                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
     901                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
     902                 :            : 
     903                 :            :         /*
     904                 :            :          * Reset to initial state
     905                 :            :          */
     906                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
     907                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     908                 :            : 
     909                 :            :         /*
     910                 :            :          * Case 3: vendor specific arbitration mechanism selected
     911                 :            :          */
     912         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
     913                 :          4 :         ctrlr.cdata.nn = 1;
     914                 :          4 :         ctrlr.page_size = 0x1000;
     915                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
     916                 :            : 
     917                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
     918         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
     919                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     920                 :            :         }
     921                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     922                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
     923                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     924                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
     925                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     926                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
     927                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
     928                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
     929                 :            : 
     930                 :            :         /*
     931                 :            :          * Complete and destroy the controller
     932                 :            :          */
     933                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
     934                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
     935                 :            : 
     936                 :            :         /*
     937                 :            :          * Reset to initial state
     938                 :            :          */
     939                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
     940                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     941                 :            : 
     942                 :            :         /*
     943                 :            :          * Case 4: invalid arbitration mechanism selected
     944                 :            :          */
     945         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
     946                 :          4 :         ctrlr.cdata.nn = 1;
     947                 :          4 :         ctrlr.page_size = 0x1000;
     948                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;
     949                 :            : 
     950                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
     951         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
     952                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     953                 :            :         }
     954                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     955                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
     956                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     957                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
     958                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     959                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
     960                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
     961                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
     962                 :            : 
     963                 :            :         /*
     964                 :            :          * Complete and destroy the controller
     965                 :            :          */
     966                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
     967                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
     968                 :            : 
     969                 :            :         /*
     970                 :            :          * Reset to initial state
     971                 :            :          */
     972                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
     973                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
     974                 :            : 
     975                 :            :         /*
     976                 :            :          * Case 5: reset to default round robin arbitration mechanism
     977                 :            :          */
     978         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
     979                 :          4 :         ctrlr.cdata.nn = 1;
     980                 :          4 :         ctrlr.page_size = 0x1000;
     981                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
     982                 :            : 
     983                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
     984         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
     985                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     986                 :            :         }
     987                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     988                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
     989                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     990                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
     991                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     992                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
     993                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
     994                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
     995                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
     996                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
     997                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
     998                 :            : 
     999                 :            :         /*
    1000                 :            :          * Transition to CSTS.RDY = 1.
    1001                 :            :          */
    1002                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
    1003                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1004                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
    1005                 :            : 
    1006                 :            :         /*
    1007                 :            :          * Transition to READY.
    1008                 :            :          */
    1009         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    1010                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
    1011                 :            :         }
    1012                 :            : 
    1013                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1014                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1015                 :          4 : }
    1016                 :            : 
    1017                 :            : static void
    1018                 :          4 : test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void)
    1019                 :            : {
    1020         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    1021                 :            : 
    1022                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
    1023                 :            : 
    1024                 :            :         /*
    1025                 :            :          * Initial state: CC.EN = 0, CSTS.RDY = 0
    1026                 :            :          * init() should set CC.EN = 1.
    1027                 :            :          */
    1028                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1029                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1030                 :            : 
    1031                 :            :         /*
    1032                 :            :          * Weighted round robin enabled
    1033                 :            :          */
    1034                 :          4 :         g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_WRR;
    1035                 :          4 :         ctrlr.cap = g_ut_nvme_regs.cap;
    1036                 :            : 
    1037         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1038                 :          4 :         ctrlr.cdata.nn = 1;
    1039                 :          4 :         ctrlr.page_size = 0x1000;
    1040                 :            :         /*
    1041                 :            :          * Case 1: default round robin arbitration mechanism selected
    1042                 :            :          */
    1043                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
    1044                 :            : 
    1045                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1046         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1047                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1048                 :            :         }
    1049                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1050                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1051                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1052                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1053                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1054                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1055                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1056                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1057                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1058                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
    1059                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
    1060                 :            : 
    1061                 :            :         /*
    1062                 :            :          * Complete and destroy the controller
    1063                 :            :          */
    1064                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1065                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1066                 :            : 
    1067                 :            :         /*
    1068                 :            :          * Reset to initial state
    1069                 :            :          */
    1070                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1071                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1072                 :            : 
    1073                 :            :         /*
    1074                 :            :          * Case 2: weighted round robin arbitration mechanism selected
    1075                 :            :          */
    1076         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1077                 :          4 :         ctrlr.cdata.nn = 1;
    1078                 :          4 :         ctrlr.page_size = 0x1000;
    1079                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
    1080                 :            : 
    1081                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1082         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1083                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1084                 :            :         }
    1085                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1086                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1087                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1088                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1089                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1090                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1091                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1092                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1093                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1094                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
    1095                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR);
    1096                 :            : 
    1097                 :            :         /*
    1098                 :            :          * Complete and destroy the controller
    1099                 :            :          */
    1100                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1101                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1102                 :            : 
    1103                 :            :         /*
    1104                 :            :          * Reset to initial state
    1105                 :            :          */
    1106                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1107                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1108                 :            : 
    1109                 :            :         /*
    1110                 :            :          * Case 3: vendor specific arbitration mechanism selected
    1111                 :            :          */
    1112         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1113                 :          4 :         ctrlr.cdata.nn = 1;
    1114                 :          4 :         ctrlr.page_size = 0x1000;
    1115                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
    1116                 :            : 
    1117                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1118         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1119                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1120                 :            :         }
    1121                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1122                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1123                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1124                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1125                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1126                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1127                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
    1128                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
    1129                 :            : 
    1130                 :            :         /*
    1131                 :            :          * Complete and destroy the controller
    1132                 :            :          */
    1133                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1134                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1135                 :            : 
    1136                 :            :         /*
    1137                 :            :          * Reset to initial state
    1138                 :            :          */
    1139                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1140                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1141                 :            : 
    1142                 :            :         /*
    1143                 :            :          * Case 4: invalid arbitration mechanism selected
    1144                 :            :          */
    1145         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1146                 :          4 :         ctrlr.cdata.nn = 1;
    1147                 :          4 :         ctrlr.page_size = 0x1000;
    1148                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;
    1149                 :            : 
    1150                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1151         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1152                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1153                 :            :         }
    1154                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1155                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1156                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1157                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1158                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1159                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1160                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
    1161                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
    1162                 :            : 
    1163                 :            :         /*
    1164                 :            :          * Complete and destroy the controller
    1165                 :            :          */
    1166                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1167                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1168                 :            : 
    1169                 :            :         /*
    1170                 :            :          * Reset to initial state
    1171                 :            :          */
    1172                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1173                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1174                 :            : 
    1175                 :            :         /*
    1176                 :            :          * Case 5: reset to weighted round robin arbitration mechanism
    1177                 :            :          */
    1178         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1179                 :          4 :         ctrlr.cdata.nn = 1;
    1180                 :          4 :         ctrlr.page_size = 0x1000;
    1181                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
    1182                 :            : 
    1183                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1184         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1185                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1186                 :            :         }
    1187                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1188                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1189                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1190                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1191                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1192                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1193                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1194                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1195                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1196                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
    1197                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR);
    1198                 :            : 
    1199                 :            :         /*
    1200                 :            :          * Transition to CSTS.RDY = 1.
    1201                 :            :          */
    1202                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
    1203                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1204                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
    1205                 :            : 
    1206                 :            :         /*
    1207                 :            :          * Transition to READY.
    1208                 :            :          */
    1209         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    1210                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
    1211                 :            :         }
    1212                 :            : 
    1213                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1214                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1215                 :          4 : }
    1216                 :            : static void
    1217                 :          4 : test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void)
    1218                 :            : {
    1219         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    1220                 :            : 
    1221                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
    1222                 :            : 
    1223                 :            :         /*
    1224                 :            :          * Initial state: CC.EN = 0, CSTS.RDY = 0
    1225                 :            :          * init() should set CC.EN = 1.
    1226                 :            :          */
    1227                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1228                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1229                 :            : 
    1230                 :            :         /*
    1231                 :            :          * Default round robin enabled
    1232                 :            :          */
    1233                 :          4 :         g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_VS;
    1234                 :          4 :         ctrlr.cap = g_ut_nvme_regs.cap;
    1235                 :            : 
    1236         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1237                 :          4 :         ctrlr.cdata.nn = 1;
    1238                 :          4 :         ctrlr.page_size = 0x1000;
    1239                 :            :         /*
    1240                 :            :          * Case 1: default round robin arbitration mechanism selected
    1241                 :            :          */
    1242                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR;
    1243                 :            : 
    1244                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1245         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1246                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1247                 :            :         }
    1248                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1249                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1250                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1251                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1252                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1253                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1254                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1255                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1256                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1257                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
    1258                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
    1259                 :            : 
    1260                 :            :         /*
    1261                 :            :          * Complete and destroy the controller
    1262                 :            :          */
    1263                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1264                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1265                 :            : 
    1266                 :            :         /*
    1267                 :            :          * Reset to initial state
    1268                 :            :          */
    1269                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1270                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1271                 :            : 
    1272                 :            :         /*
    1273                 :            :          * Case 2: weighted round robin arbitration mechanism selected
    1274                 :            :          */
    1275         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1276                 :          4 :         ctrlr.cdata.nn = 1;
    1277                 :          4 :         ctrlr.page_size = 0x1000;
    1278                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;
    1279                 :            : 
    1280                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1281         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1282                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1283                 :            :         }
    1284                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1285                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1286                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1287                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1288                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1289                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1290                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
    1291                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
    1292                 :            : 
    1293                 :            :         /*
    1294                 :            :          * Complete and destroy the controller
    1295                 :            :          */
    1296                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1297                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1298                 :            : 
    1299                 :            :         /*
    1300                 :            :          * Reset to initial state
    1301                 :            :          */
    1302                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1303                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1304                 :            : 
    1305                 :            :         /*
    1306                 :            :          * Case 3: vendor specific arbitration mechanism selected
    1307                 :            :          */
    1308         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1309                 :          4 :         ctrlr.cdata.nn = 1;
    1310                 :          4 :         ctrlr.page_size = 0x1000;
    1311                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
    1312                 :            : 
    1313                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1314         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1315                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1316                 :            :         }
    1317                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1318                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1319                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1320                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1321                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1322                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1323                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1324                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1325                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1326                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
    1327                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS);
    1328                 :            : 
    1329                 :            :         /*
    1330                 :            :          * Complete and destroy the controller
    1331                 :            :          */
    1332                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1333                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1334                 :            : 
    1335                 :            :         /*
    1336                 :            :          * Reset to initial state
    1337                 :            :          */
    1338                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1339                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1340                 :            : 
    1341                 :            :         /*
    1342                 :            :          * Case 4: invalid arbitration mechanism selected
    1343                 :            :          */
    1344         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1345                 :          4 :         ctrlr.cdata.nn = 1;
    1346                 :          4 :         ctrlr.page_size = 0x1000;
    1347                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;
    1348                 :            : 
    1349                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1350         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1351                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1352                 :            :         }
    1353                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1354                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1355                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1356                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1357                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1358                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1359                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);
    1360                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
    1361                 :            : 
    1362                 :            :         /*
    1363                 :            :          * Complete and destroy the controller
    1364                 :            :          */
    1365                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1366                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1367                 :            : 
    1368                 :            :         /*
    1369                 :            :          * Reset to initial state
    1370                 :            :          */
    1371                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1372                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1373                 :            : 
    1374                 :            :         /*
    1375                 :            :          * Case 5: reset to vendor specific arbitration mechanism
    1376                 :            :          */
    1377         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1378                 :          4 :         ctrlr.cdata.nn = 1;
    1379                 :          4 :         ctrlr.page_size = 0x1000;
    1380                 :          4 :         ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;
    1381                 :            : 
    1382                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1383         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1384                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1385                 :            :         }
    1386                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1387                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1388                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1389                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1390                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1391                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1392                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1393                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1394                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1395                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
    1396                 :          4 :         CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS);
    1397                 :            : 
    1398                 :            :         /*
    1399                 :            :          * Transition to CSTS.RDY = 1.
    1400                 :            :          */
    1401                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
    1402                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1403                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
    1404                 :            : 
    1405                 :            :         /*
    1406                 :            :          * Transition to READY.
    1407                 :            :          */
    1408         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    1409                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
    1410                 :            :         }
    1411                 :            : 
    1412                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1413                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1414                 :          4 : }
    1415                 :            : 
    1416                 :            : static void
    1417                 :          4 : test_nvme_ctrlr_init_en_0_rdy_0(void)
    1418                 :            : {
    1419         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    1420                 :            : 
    1421                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
    1422                 :            : 
    1423                 :            :         /*
    1424                 :            :          * Initial state: CC.EN = 0, CSTS.RDY = 0
    1425                 :            :          * init() should set CC.EN = 1.
    1426                 :            :          */
    1427                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1428                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1429                 :            : 
    1430         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1431                 :          4 :         ctrlr.cdata.nn = 1;
    1432                 :          4 :         ctrlr.page_size = 0x1000;
    1433                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1434         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1435                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1436                 :            :         }
    1437                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1438                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1439                 :            : 
    1440                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1441                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1442                 :            : 
    1443                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1444                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1445                 :            : 
    1446                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1447                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1448                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1449                 :            : 
    1450                 :            :         /*
    1451                 :            :          * Transition to CSTS.RDY = 1.
    1452                 :            :          */
    1453                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
    1454                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1455                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
    1456                 :            : 
    1457                 :            :         /*
    1458                 :            :          * Transition to READY.
    1459                 :            :          */
    1460         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    1461                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
    1462                 :            :         }
    1463                 :            : 
    1464                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1465                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1466                 :          4 : }
    1467                 :            : 
    1468                 :            : static void
    1469                 :          4 : test_nvme_ctrlr_init_en_0_rdy_1(void)
    1470                 :            : {
    1471         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    1472                 :            : 
    1473                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
    1474                 :            : 
    1475                 :            :         /*
    1476                 :            :          * Initial state: CC.EN = 0, CSTS.RDY = 1
    1477                 :            :          */
    1478                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    1479                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
    1480                 :            : 
    1481         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    1482                 :          4 :         ctrlr.cdata.nn = 1;
    1483                 :          4 :         ctrlr.page_size = 0x1000;
    1484                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    1485         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    1486                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1487                 :            :         }
    1488                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1489                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    1490                 :            : 
    1491                 :            :         /*
    1492                 :            :          * Transition to CSTS.RDY = 0.
    1493                 :            :          */
    1494                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    1495                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1496                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    1497                 :            : 
    1498                 :            :         /*
    1499                 :            :          * Start enabling the controller.
    1500                 :            :          */
    1501                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1502                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    1503                 :            : 
    1504                 :            :         /*
    1505                 :            :          * Transition to CC.EN = 1
    1506                 :            :          */
    1507                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1508                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    1509                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    1510                 :            : 
    1511                 :            :         /*
    1512                 :            :          * Transition to CSTS.RDY = 1.
    1513                 :            :          */
    1514                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
    1515                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    1516                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
    1517                 :            : 
    1518                 :            :         /*
    1519                 :            :          * Transition to READY.
    1520                 :            :          */
    1521         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    1522                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
    1523                 :            :         }
    1524                 :            : 
    1525                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    1526                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    1527                 :          4 : }
    1528                 :            : 
    1529                 :            : static void
    1530                 :         16 : setup_qpairs(struct spdk_nvme_ctrlr *ctrlr, uint32_t num_io_queues)
    1531                 :            : {
    1532                 :            :         uint32_t i;
    1533                 :            : 
    1534         [ -  + ]:         16 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(ctrlr) == 0);
    1535                 :            : 
    1536                 :         16 :         ctrlr->page_size = 0x1000;
    1537                 :         16 :         ctrlr->opts.num_io_queues = num_io_queues;
    1538                 :         16 :         ctrlr->free_io_qids = spdk_bit_array_create(num_io_queues + 1);
    1539                 :         16 :         ctrlr->state = NVME_CTRLR_STATE_READY;
    1540         [ -  + ]:         16 :         SPDK_CU_ASSERT_FATAL(ctrlr->free_io_qids != NULL);
    1541                 :            : 
    1542                 :         16 :         spdk_bit_array_clear(ctrlr->free_io_qids, 0);
    1543         [ +  + ]:         48 :         for (i = 1; i <= num_io_queues; i++) {
    1544                 :         32 :                 spdk_bit_array_set(ctrlr->free_io_qids, i);
    1545                 :            :         }
    1546                 :         16 : }
    1547                 :            : 
    1548                 :            : static void
    1549                 :         16 : cleanup_qpairs(struct spdk_nvme_ctrlr *ctrlr)
    1550                 :            : {
    1551                 :         16 :         nvme_ctrlr_destruct(ctrlr);
    1552                 :         16 : }
    1553                 :            : 
    1554                 :            : static void
    1555                 :          4 : test_alloc_io_qpair_rr_1(void)
    1556                 :            : {
    1557                 :          4 :         struct spdk_nvme_io_qpair_opts opts;
    1558                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    1559                 :            :         struct spdk_nvme_qpair *q0;
    1560                 :            : 
    1561                 :          4 :         setup_qpairs(&ctrlr, 1);
    1562                 :            : 
    1563                 :            :         /*
    1564                 :            :          * Fake to simulate the controller with default round robin
    1565                 :            :          * arbitration mechanism.
    1566                 :            :          */
    1567                 :          4 :         g_ut_nvme_regs.cc.bits.ams = SPDK_NVME_CC_AMS_RR;
    1568                 :            : 
    1569                 :          4 :         spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
    1570                 :            : 
    1571                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0);
    1572         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 != NULL);
    1573         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
    1574                 :            :         /* Only 1 I/O qpair was allocated, so this should fail */
    1575         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0) == NULL);
    1576         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
    1577                 :            : 
    1578                 :            :         /*
    1579                 :            :          * Now that the qpair has been returned to the free list,
    1580                 :            :          * we should be able to allocate it again.
    1581                 :            :          */
    1582                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0);
    1583         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 != NULL);
    1584         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
    1585         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
    1586                 :            : 
    1587                 :            :         /* Only 0 qprio is acceptable for default round robin arbitration mechanism */
    1588                 :          4 :         opts.qprio = 1;
    1589                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1590         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 == NULL);
    1591                 :            : 
    1592                 :          4 :         opts.qprio = 2;
    1593                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1594         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 == NULL);
    1595                 :            : 
    1596                 :          4 :         opts.qprio = 3;
    1597                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1598         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 == NULL);
    1599                 :            : 
    1600                 :            :         /* Only 0 ~ 3 qprio is acceptable */
    1601                 :          4 :         opts.qprio = 4;
    1602         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL);
    1603                 :          4 :         opts.qprio = 0;
    1604                 :            : 
    1605                 :            :         /* IO qpair can only be created when ctrlr is in READY state */
    1606                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_ENABLE;
    1607                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1608         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 == NULL);
    1609                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_READY;
    1610                 :            : 
    1611                 :          4 :         cleanup_qpairs(&ctrlr);
    1612                 :          4 : }
    1613                 :            : 
    1614                 :            : static void
    1615                 :          4 : test_alloc_io_qpair_wrr_1(void)
    1616                 :            : {
    1617                 :          4 :         struct spdk_nvme_io_qpair_opts opts;
    1618                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    1619                 :            :         struct spdk_nvme_qpair *q0, *q1;
    1620                 :            : 
    1621                 :          4 :         setup_qpairs(&ctrlr, 2);
    1622                 :            : 
    1623                 :            :         /*
    1624                 :            :          * Fake to simulate the controller with weighted round robin
    1625                 :            :          * arbitration mechanism.
    1626                 :            :          */
    1627                 :          4 :         ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR;
    1628                 :            : 
    1629                 :          4 :         spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
    1630                 :            : 
    1631                 :            :         /*
    1632                 :            :          * Allocate 2 qpairs and free them
    1633                 :            :          */
    1634                 :          4 :         opts.qprio = 0;
    1635                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1636         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 != NULL);
    1637         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
    1638                 :            : 
    1639                 :          4 :         opts.qprio = 1;
    1640                 :          4 :         q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1641         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1 != NULL);
    1642         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1->qprio == 1);
    1643         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
    1644         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
    1645                 :            : 
    1646                 :            :         /*
    1647                 :            :          * Allocate 2 qpairs and free them in the reverse order
    1648                 :            :          */
    1649                 :          4 :         opts.qprio = 2;
    1650                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1651         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 != NULL);
    1652         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0->qprio == 2);
    1653                 :            : 
    1654                 :          4 :         opts.qprio = 3;
    1655                 :          4 :         q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1656         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1 != NULL);
    1657         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1->qprio == 3);
    1658         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
    1659         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
    1660                 :            : 
    1661                 :            :         /* Only 0 ~ 3 qprio is acceptable */
    1662                 :          4 :         opts.qprio = 4;
    1663         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL);
    1664                 :            : 
    1665                 :          4 :         cleanup_qpairs(&ctrlr);
    1666                 :          4 : }
    1667                 :            : 
    1668                 :            : static void
    1669                 :          4 : test_alloc_io_qpair_wrr_2(void)
    1670                 :            : {
    1671                 :          4 :         struct spdk_nvme_io_qpair_opts opts;
    1672                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    1673                 :            :         struct spdk_nvme_qpair *q0, *q1, *q2, *q3;
    1674                 :            : 
    1675                 :          4 :         setup_qpairs(&ctrlr, 4);
    1676                 :            : 
    1677                 :            :         /*
    1678                 :            :          * Fake to simulate the controller with weighted round robin
    1679                 :            :          * arbitration mechanism.
    1680                 :            :          */
    1681                 :          4 :         ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR;
    1682                 :            : 
    1683                 :          4 :         spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
    1684                 :            : 
    1685                 :          4 :         opts.qprio = 0;
    1686                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1687         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 != NULL);
    1688         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0->qprio == 0);
    1689                 :            : 
    1690                 :          4 :         opts.qprio = 1;
    1691                 :          4 :         q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1692         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1 != NULL);
    1693         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1->qprio == 1);
    1694                 :            : 
    1695                 :          4 :         opts.qprio = 2;
    1696                 :          4 :         q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1697         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q2 != NULL);
    1698         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q2->qprio == 2);
    1699                 :            : 
    1700                 :          4 :         opts.qprio = 3;
    1701                 :          4 :         q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1702         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q3 != NULL);
    1703         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q3->qprio == 3);
    1704                 :            : 
    1705                 :            :         /* Only 4 I/O qpairs was allocated, so this should fail */
    1706                 :          4 :         opts.qprio = 0;
    1707         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL);
    1708         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0);
    1709         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0);
    1710         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
    1711         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
    1712                 :            : 
    1713                 :            :         /*
    1714                 :            :          * Now that the qpair has been returned to the free list,
    1715                 :            :          * we should be able to allocate it again.
    1716                 :            :          *
    1717                 :            :          * Allocate 4 I/O qpairs and half of them with same qprio.
    1718                 :            :          */
    1719                 :          4 :         opts.qprio = 1;
    1720                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1721         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 != NULL);
    1722         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0->qprio == 1);
    1723                 :            : 
    1724                 :          4 :         opts.qprio = 1;
    1725                 :          4 :         q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1726         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1 != NULL);
    1727         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q1->qprio == 1);
    1728                 :            : 
    1729                 :          4 :         opts.qprio = 3;
    1730                 :          4 :         q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1731         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q2 != NULL);
    1732         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q2->qprio == 3);
    1733                 :            : 
    1734                 :          4 :         opts.qprio = 3;
    1735                 :          4 :         q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts));
    1736         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q3 != NULL);
    1737         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q3->qprio == 3);
    1738                 :            : 
    1739                 :            :         /*
    1740                 :            :          * Free all I/O qpairs in reverse order
    1741                 :            :          */
    1742         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0);
    1743         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0);
    1744         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0);
    1745         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0);
    1746                 :            : 
    1747                 :          4 :         cleanup_qpairs(&ctrlr);
    1748                 :          4 : }
    1749                 :            : 
    1750                 :            : bool g_connect_qpair_called = false;
    1751                 :            : int g_connect_qpair_return_code = 0;
    1752                 :            : int
    1753                 :        148 : nvme_transport_ctrlr_connect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
    1754                 :            : {
    1755                 :        148 :         g_connect_qpair_called = true;
    1756                 :        148 :         qpair->state = NVME_QPAIR_CONNECTED;
    1757                 :        148 :         return g_connect_qpair_return_code;
    1758                 :            : }
    1759                 :            : 
    1760                 :            : static void
    1761                 :          4 : test_spdk_nvme_ctrlr_reconnect_io_qpair(void)
    1762                 :            : {
    1763                 :          4 :         struct spdk_nvme_ctrlr  ctrlr = {};
    1764                 :          4 :         struct spdk_nvme_qpair  qpair = {};
    1765                 :            :         int rc;
    1766                 :            : 
    1767         [ -  + ]:          4 :         CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
    1768                 :            : 
    1769                 :            :         /* Various states of controller disconnect. */
    1770                 :          4 :         qpair.id = 1;
    1771                 :          4 :         qpair.ctrlr = &ctrlr;
    1772                 :          4 :         ctrlr.is_removed = 1;
    1773                 :          4 :         ctrlr.is_failed = 0;
    1774                 :          4 :         ctrlr.is_resetting = 0;
    1775                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1776                 :          4 :         CU_ASSERT(rc == -ENODEV)
    1777                 :            : 
    1778                 :          4 :         ctrlr.is_removed = 0;
    1779                 :          4 :         ctrlr.is_failed = 1;
    1780                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1781                 :          4 :         CU_ASSERT(rc == -ENXIO)
    1782                 :            : 
    1783                 :          4 :         ctrlr.is_failed = 0;
    1784                 :          4 :         ctrlr.is_resetting = 1;
    1785                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1786                 :          4 :         CU_ASSERT(rc == -EAGAIN)
    1787                 :            : 
    1788                 :            :         /* Confirm precedence for controller states: removed > resetting > failed */
    1789                 :          4 :         ctrlr.is_removed = 1;
    1790                 :          4 :         ctrlr.is_failed = 1;
    1791                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1792                 :          4 :         CU_ASSERT(rc == -ENODEV)
    1793                 :            : 
    1794                 :          4 :         ctrlr.is_removed = 0;
    1795                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1796                 :          4 :         CU_ASSERT(rc == -EAGAIN)
    1797                 :            : 
    1798                 :          4 :         ctrlr.is_resetting = 0;
    1799                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1800                 :          4 :         CU_ASSERT(rc == -ENXIO)
    1801                 :            : 
    1802                 :            :         /* qpair not failed. Make sure we don't call down to the transport */
    1803                 :          4 :         ctrlr.is_failed = 0;
    1804                 :          4 :         qpair.state = NVME_QPAIR_CONNECTED;
    1805                 :          4 :         g_connect_qpair_called = false;
    1806                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1807         [ -  + ]:          4 :         CU_ASSERT(g_connect_qpair_called == false);
    1808                 :          4 :         CU_ASSERT(rc == 0)
    1809                 :            : 
    1810                 :            :         /* transport qpair is failed. make sure we call down to the transport */
    1811                 :          4 :         qpair.state = NVME_QPAIR_DISCONNECTED;
    1812                 :          4 :         rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair);
    1813         [ -  + ]:          4 :         CU_ASSERT(g_connect_qpair_called == true);
    1814                 :          4 :         CU_ASSERT(rc == 0)
    1815                 :            : 
    1816         [ -  + ]:          4 :         CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
    1817                 :          4 : }
    1818                 :            : 
    1819                 :            : static void
    1820                 :          4 : test_nvme_ctrlr_fail(void)
    1821                 :            : {
    1822                 :          4 :         struct spdk_nvme_ctrlr  ctrlr = {};
    1823                 :            : 
    1824                 :          4 :         ctrlr.opts.num_io_queues = 0;
    1825                 :          4 :         nvme_ctrlr_fail(&ctrlr, false);
    1826                 :            : 
    1827         [ -  + ]:          4 :         CU_ASSERT(ctrlr.is_failed == true);
    1828                 :          4 : }
    1829                 :            : 
    1830                 :            : static void
    1831                 :          4 : test_nvme_ctrlr_construct_intel_support_log_page_list(void)
    1832                 :            : {
    1833                 :            :         bool    res;
    1834                 :          4 :         struct spdk_nvme_ctrlr                          ctrlr = {};
    1835                 :          4 :         struct spdk_nvme_intel_log_page_directory       payload = {};
    1836                 :          4 :         struct spdk_pci_id                              pci_id = {};
    1837                 :            : 
    1838                 :            :         /* Get quirks for a device with all 0 vendor/device id */
    1839                 :          4 :         ctrlr.quirks = nvme_get_quirks(&pci_id);
    1840                 :          4 :         CU_ASSERT(ctrlr.quirks == 0);
    1841                 :            : 
    1842                 :            :         /* Set the vendor to Intel, but provide no device id */
    1843                 :          4 :         pci_id.class_id = SPDK_PCI_CLASS_NVME;
    1844                 :          4 :         ctrlr.cdata.vid = pci_id.vendor_id = SPDK_PCI_VID_INTEL;
    1845                 :          4 :         payload.temperature_statistics_log_len = 1;
    1846                 :          4 :         ctrlr.quirks = nvme_get_quirks(&pci_id);
    1847         [ -  + ]:          4 :         memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
    1848                 :            : 
    1849                 :          4 :         nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
    1850                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY);
    1851                 :          4 :         CU_ASSERT(res == true);
    1852                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE);
    1853                 :          4 :         CU_ASSERT(res == true);
    1854                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY);
    1855                 :          4 :         CU_ASSERT(res == false);
    1856                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART);
    1857                 :          4 :         CU_ASSERT(res == false);
    1858                 :            : 
    1859                 :            :         /* set valid vendor id, device id and sub device id */
    1860                 :          4 :         ctrlr.cdata.vid = SPDK_PCI_VID_INTEL;
    1861                 :          4 :         payload.temperature_statistics_log_len = 0;
    1862                 :          4 :         pci_id.vendor_id = SPDK_PCI_VID_INTEL;
    1863                 :          4 :         pci_id.device_id = 0x0953;
    1864                 :          4 :         pci_id.subvendor_id = SPDK_PCI_VID_INTEL;
    1865                 :          4 :         pci_id.subdevice_id = 0x3702;
    1866                 :          4 :         ctrlr.quirks = nvme_get_quirks(&pci_id);
    1867         [ -  + ]:          4 :         memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
    1868                 :            : 
    1869                 :          4 :         nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
    1870                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY);
    1871                 :          4 :         CU_ASSERT(res == true);
    1872                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE);
    1873                 :          4 :         CU_ASSERT(res == false);
    1874                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY);
    1875                 :          4 :         CU_ASSERT(res == true);
    1876                 :          4 :         res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART);
    1877                 :          4 :         CU_ASSERT(res == false);
    1878                 :          4 : }
    1879                 :            : 
    1880                 :            : static void
    1881                 :          4 : test_nvme_ctrlr_set_supported_features(void)
    1882                 :            : {
    1883                 :            :         bool    res;
    1884                 :          4 :         struct spdk_nvme_ctrlr                  ctrlr = {};
    1885                 :            : 
    1886                 :            :         /* set a invalid vendor id */
    1887                 :          4 :         ctrlr.cdata.vid = 0xFFFF;
    1888                 :          4 :         nvme_ctrlr_set_supported_features(&ctrlr);
    1889                 :          4 :         res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION);
    1890                 :          4 :         CU_ASSERT(res == true);
    1891                 :          4 :         res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA);
    1892                 :          4 :         CU_ASSERT(res == false);
    1893                 :            : 
    1894                 :          4 :         ctrlr.cdata.vid = SPDK_PCI_VID_INTEL;
    1895                 :          4 :         nvme_ctrlr_set_supported_features(&ctrlr);
    1896                 :          4 :         res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION);
    1897                 :          4 :         CU_ASSERT(res == true);
    1898                 :          4 :         res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA);
    1899                 :          4 :         CU_ASSERT(res == true);
    1900                 :          4 : }
    1901                 :            : 
    1902                 :            : static void
    1903                 :          4 : test_ctrlr_get_default_ctrlr_opts(void)
    1904                 :            : {
    1905                 :          4 :         struct spdk_nvme_ctrlr_opts opts = {};
    1906                 :            : 
    1907                 :          4 :         CU_ASSERT(spdk_uuid_parse(&g_spdk_nvme_driver->default_extended_host_id,
    1908                 :            :                                   "e53e9258-c93b-48b5-be1a-f025af6d232a") == 0);
    1909                 :            : 
    1910                 :          4 :         memset(&opts, 0, sizeof(opts));
    1911                 :            : 
    1912                 :            :         /* set a smaller opts_size */
    1913                 :          4 :         CU_ASSERT(sizeof(opts) > 8);
    1914                 :          4 :         spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, 8);
    1915                 :          4 :         CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES);
    1916         [ -  + ]:          4 :         CU_ASSERT_FALSE(opts.use_cmb_sqs);
    1917                 :            :         /* check below fields are not initialized by default value */
    1918                 :          4 :         CU_ASSERT_EQUAL(opts.arb_mechanism, 0);
    1919                 :          4 :         CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 0);
    1920                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_size, 0);
    1921                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_requests, 0);
    1922         [ +  + ]:         36 :         for (int i = 0; i < 8; i++) {
    1923                 :         32 :                 CU_ASSERT(opts.host_id[i] == 0);
    1924                 :            :         }
    1925         [ +  + ]:         68 :         for (int i = 0; i < 16; i++) {
    1926                 :         64 :                 CU_ASSERT(opts.extended_host_id[i] == 0);
    1927                 :            :         }
    1928                 :          4 :         CU_ASSERT(strlen(opts.hostnqn) == 0);
    1929                 :          4 :         CU_ASSERT(strlen(opts.src_addr) == 0);
    1930                 :          4 :         CU_ASSERT(strlen(opts.src_svcid) == 0);
    1931                 :          4 :         CU_ASSERT_EQUAL(opts.admin_timeout_ms, 0);
    1932                 :            : 
    1933                 :            :         /* set a consistent opts_size */
    1934                 :          4 :         spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, sizeof(opts));
    1935                 :          4 :         CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES);
    1936         [ -  + ]:          4 :         CU_ASSERT_FALSE(opts.use_cmb_sqs);
    1937                 :          4 :         CU_ASSERT_EQUAL(opts.arb_mechanism, SPDK_NVME_CC_AMS_RR);
    1938                 :          4 :         CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 10 * 1000);
    1939                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE);
    1940                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
    1941         [ +  + ]:         36 :         for (int i = 0; i < 8; i++) {
    1942                 :         32 :                 CU_ASSERT(opts.host_id[i] == 0);
    1943                 :            :         }
    1944                 :          4 :         CU_ASSERT_STRING_EQUAL(opts.hostnqn,
    1945                 :            :                                "nqn.2014-08.org.nvmexpress:uuid:e53e9258-c93b-48b5-be1a-f025af6d232a");
    1946         [ -  + ]:          4 :         CU_ASSERT(memcmp(opts.extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
    1947                 :            :                          sizeof(opts.extended_host_id)) == 0);
    1948                 :          4 :         CU_ASSERT(strlen(opts.src_addr) == 0);
    1949                 :          4 :         CU_ASSERT(strlen(opts.src_svcid) == 0);
    1950                 :          4 :         CU_ASSERT_EQUAL(opts.admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
    1951                 :          4 : }
    1952                 :            : 
    1953                 :            : static void
    1954                 :          4 : test_ctrlr_get_default_io_qpair_opts(void)
    1955                 :            : {
    1956                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    1957                 :          4 :         struct spdk_nvme_io_qpair_opts opts = {};
    1958                 :            : 
    1959         [ -  + ]:          4 :         memset(&opts, 0, sizeof(opts));
    1960                 :            : 
    1961                 :            :         /* set a smaller opts_size */
    1962                 :          4 :         ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE;
    1963                 :          4 :         CU_ASSERT(sizeof(opts) > 8);
    1964                 :          4 :         spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, 8);
    1965                 :          4 :         CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT);
    1966                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE);
    1967                 :            :         /* check below field is not initialized by default value */
    1968                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_requests, 0);
    1969                 :            : 
    1970                 :            :         /* set a consistent opts_size */
    1971                 :          4 :         ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE;
    1972                 :          4 :         ctrlr.opts.io_queue_requests = DEFAULT_IO_QUEUE_REQUESTS;
    1973                 :          4 :         spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts));
    1974                 :          4 :         CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT);
    1975                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE);
    1976                 :          4 :         CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
    1977                 :          4 : }
    1978                 :            : 
    1979                 :            : #if 0 /* TODO: move to PCIe-specific unit test */
    1980                 :            : static void
    1981                 :            : test_nvme_ctrlr_alloc_cmb(void)
    1982                 :            : {
    1983                 :            :         int                     rc;
    1984                 :            :         uint64_t                offset;
    1985                 :            :         struct spdk_nvme_ctrlr  ctrlr = {};
    1986                 :            : 
    1987                 :            :         ctrlr.cmb_size = 0x1000000;
    1988                 :            :         ctrlr.cmb_current_offset = 0x100;
    1989                 :            :         rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x200, 0x1000, &offset);
    1990                 :            :         CU_ASSERT(rc == 0);
    1991                 :            :         CU_ASSERT(offset == 0x1000);
    1992                 :            :         CU_ASSERT(ctrlr.cmb_current_offset == 0x1200);
    1993                 :            : 
    1994                 :            :         rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800, 0x1000, &offset);
    1995                 :            :         CU_ASSERT(rc == 0);
    1996                 :            :         CU_ASSERT(offset == 0x2000);
    1997                 :            :         CU_ASSERT(ctrlr.cmb_current_offset == 0x2800);
    1998                 :            : 
    1999                 :            :         rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800000, 0x100000, &offset);
    2000                 :            :         CU_ASSERT(rc == 0);
    2001                 :            :         CU_ASSERT(offset == 0x100000);
    2002                 :            :         CU_ASSERT(ctrlr.cmb_current_offset == 0x900000);
    2003                 :            : 
    2004                 :            :         rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x8000000, 0x1000, &offset);
    2005                 :            :         CU_ASSERT(rc == -1);
    2006                 :            : }
    2007                 :            : #endif
    2008                 :            : 
    2009                 :            : static void
    2010                 :          4 : test_spdk_nvme_ctrlr_update_firmware(void)
    2011                 :            : {
    2012                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    2013                 :          4 :         void *payload = NULL;
    2014                 :          4 :         int point_payload = 1;
    2015                 :          4 :         int slot = 0;
    2016                 :          4 :         int ret = 0;
    2017                 :          4 :         struct spdk_nvme_status status;
    2018                 :          4 :         enum spdk_nvme_fw_commit_action commit_action = SPDK_NVME_FW_COMMIT_REPLACE_IMG;
    2019                 :            : 
    2020         [ -  + ]:          4 :         CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
    2021                 :            : 
    2022                 :            :         /* Set invalid size check function return value */
    2023                 :          4 :         set_size = 5;
    2024                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2025                 :          4 :         CU_ASSERT(ret == -1);
    2026                 :            : 
    2027                 :            :         /* When payload is NULL but set_size < min_page_size */
    2028                 :          4 :         set_size = 4;
    2029                 :          4 :         ctrlr.min_page_size = 5;
    2030                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2031                 :          4 :         CU_ASSERT(ret == -1);
    2032                 :            : 
    2033                 :            :         /* When payload not NULL but min_page_size is 0 */
    2034                 :          4 :         set_size = 4;
    2035                 :          4 :         ctrlr.min_page_size = 0;
    2036                 :          4 :         payload = &point_payload;
    2037                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2038                 :          4 :         CU_ASSERT(ret == -1);
    2039                 :            : 
    2040                 :            :         /* Check firmware image download when payload not NULL and min_page_size not 0 , status.cpl value is 1 */
    2041                 :          4 :         set_status_cpl = 1;
    2042                 :          4 :         set_size = 4;
    2043                 :          4 :         ctrlr.min_page_size = 5;
    2044                 :          4 :         payload = &point_payload;
    2045                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2046                 :          4 :         CU_ASSERT(ret == -ENXIO);
    2047                 :            : 
    2048                 :            :         /* Check firmware image download and set status.cpl value is 0 */
    2049                 :          4 :         set_status_cpl = 0;
    2050                 :          4 :         set_size = 4;
    2051                 :          4 :         ctrlr.min_page_size = 5;
    2052                 :          4 :         payload = &point_payload;
    2053                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2054                 :          4 :         CU_ASSERT(ret == -1);
    2055                 :            : 
    2056                 :            :         /* Check firmware commit */
    2057                 :          4 :         ctrlr.is_resetting = false;
    2058                 :          4 :         set_status_cpl = 0;
    2059                 :          4 :         slot = 1;
    2060                 :          4 :         set_size = 4;
    2061                 :          4 :         ctrlr.min_page_size = 5;
    2062                 :          4 :         payload = &point_payload;
    2063                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2064                 :          4 :         CU_ASSERT(ret == -ENXIO);
    2065                 :            : 
    2066                 :            :         /* Set size check firmware download and firmware commit */
    2067                 :          4 :         ctrlr.is_resetting = true;
    2068                 :          4 :         set_status_cpl = 0;
    2069                 :          4 :         slot = 1;
    2070                 :          4 :         set_size = 4;
    2071                 :          4 :         ctrlr.min_page_size = 5;
    2072                 :          4 :         payload = &point_payload;
    2073                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2074                 :          4 :         CU_ASSERT(ret == 0);
    2075                 :            : 
    2076                 :            :         /* nvme_wait_for_completion returns an error */
    2077                 :          4 :         g_wait_for_completion_return_val = -1;
    2078                 :          4 :         ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status);
    2079                 :          4 :         CU_ASSERT(ret == -ENXIO);
    2080                 :          4 :         CU_ASSERT(g_failed_status != NULL);
    2081         [ -  + ]:          4 :         CU_ASSERT(g_failed_status->timed_out == true);
    2082                 :            :         /* status should be freed by callback, which is not triggered in test env.
    2083                 :            :            Store status to global variable and free it manually.
    2084                 :            :            If spdk_nvme_ctrlr_update_firmware changes its behaviour and frees the status
    2085                 :            :            itself, we'll get a double free here.. */
    2086                 :          4 :         free(g_failed_status);
    2087                 :          4 :         g_failed_status = NULL;
    2088                 :          4 :         g_wait_for_completion_return_val = 0;
    2089                 :            : 
    2090         [ -  + ]:          4 :         CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
    2091                 :          4 :         set_status_cpl = 0;
    2092                 :          4 : }
    2093                 :            : 
    2094                 :            : int
    2095                 :          4 : nvme_ctrlr_cmd_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr, uint64_t prp1, uint64_t prp2,
    2096                 :            :                                       spdk_nvme_cmd_cb cb_fn, void *cb_arg)
    2097                 :            : {
    2098                 :          4 :         fake_cpl_sc(cb_fn, cb_arg);
    2099                 :          4 :         return 0;
    2100                 :            : }
    2101                 :            : 
    2102                 :            : static void
    2103                 :          4 : test_spdk_nvme_ctrlr_doorbell_buffer_config(void)
    2104                 :            : {
    2105                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    2106                 :          4 :         int ret = -1;
    2107                 :            : 
    2108                 :          4 :         ctrlr.cdata.oacs.doorbell_buffer_config = 1;
    2109                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
    2110                 :          4 :         ctrlr.page_size = 0x1000;
    2111                 :          4 :         MOCK_CLEAR(spdk_malloc);
    2112                 :          4 :         MOCK_CLEAR(spdk_zmalloc);
    2113                 :          4 :         ret = nvme_ctrlr_set_doorbell_buffer_config(&ctrlr);
    2114                 :          4 :         CU_ASSERT(ret == 0);
    2115                 :          4 :         nvme_ctrlr_free_doorbell_buffer(&ctrlr);
    2116                 :          4 : }
    2117                 :            : 
    2118                 :            : static void
    2119                 :          4 : test_nvme_ctrlr_test_active_ns(void)
    2120                 :            : {
    2121                 :            :         uint32_t                nsid, minor;
    2122                 :            :         size_t                  ns_id_count;
    2123                 :          4 :         struct spdk_nvme_ctrlr  ctrlr = {};
    2124                 :          4 :         uint32_t                active_ns_list[1531];
    2125                 :            : 
    2126         [ +  + ]:       6128 :         for (nsid = 1; nsid <= 1531; nsid++) {
    2127                 :       6124 :                 active_ns_list[nsid - 1] = nsid;
    2128                 :            :         }
    2129                 :            : 
    2130                 :          4 :         g_active_ns_list = active_ns_list;
    2131                 :            : 
    2132                 :          4 :         ctrlr.page_size = 0x1000;
    2133                 :            : 
    2134         [ +  + ]:         16 :         for (minor = 0; minor <= 2; minor++) {
    2135         [ -  + ]:         12 :                 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2136                 :         12 :                 ctrlr.state = NVME_CTRLR_STATE_READY;
    2137                 :            : 
    2138                 :         12 :                 ctrlr.vs.bits.mjr = 1;
    2139                 :         12 :                 ctrlr.vs.bits.mnr = minor;
    2140                 :         12 :                 ctrlr.vs.bits.ter = 0;
    2141                 :         12 :                 ctrlr.cdata.nn = 1531;
    2142                 :            : 
    2143                 :         12 :                 RB_INIT(&ctrlr.ns);
    2144                 :            : 
    2145                 :         12 :                 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2146                 :         12 :                 nvme_ctrlr_identify_active_ns(&ctrlr);
    2147                 :            : 
    2148         [ +  + ]:      18384 :                 for (nsid = 1; nsid <= ctrlr.cdata.nn; nsid++) {
    2149                 :      18372 :                         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true);
    2150                 :            :                 }
    2151                 :            : 
    2152         [ +  + ]:        348 :                 for (; nsid <= 1559; nsid++) {
    2153                 :        336 :                         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == false);
    2154                 :            :                 }
    2155                 :            : 
    2156                 :         12 :                 g_active_ns_list_length = 0;
    2157         [ +  + ]:         12 :                 if (minor <= 1) {
    2158                 :          8 :                         ctrlr.cdata.nn = 0;
    2159                 :            :                 }
    2160                 :         12 :                 nvme_ctrlr_identify_active_ns(&ctrlr);
    2161                 :         12 :                 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0);
    2162                 :            : 
    2163                 :         12 :                 g_active_ns_list_length = 1;
    2164         [ +  + ]:         12 :                 if (minor <= 1) {
    2165                 :          8 :                         ctrlr.cdata.nn = 1;
    2166                 :            :                 }
    2167                 :         12 :                 nvme_ctrlr_identify_active_ns(&ctrlr);
    2168                 :         12 :                 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true);
    2169                 :         12 :                 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false);
    2170                 :         12 :                 nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr);
    2171                 :         12 :                 CU_ASSERT(nsid == 1);
    2172                 :            : 
    2173         [ +  + ]:         12 :                 if (minor >= 2) {
    2174                 :            :                         /* For NVMe 1.2 and newer, the namespace list can have "holes" where
    2175                 :            :                          * some namespaces are not active. Test this. */
    2176                 :          4 :                         g_active_ns_list_length = 2;
    2177                 :          4 :                         g_active_ns_list[1] = 3;
    2178                 :          4 :                         nvme_ctrlr_identify_active_ns(&ctrlr);
    2179                 :          4 :                         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true);
    2180                 :          4 :                         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false);
    2181                 :          4 :                         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3) == true);
    2182                 :          4 :                         nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid);
    2183                 :          4 :                         CU_ASSERT(nsid == 3);
    2184                 :          4 :                         nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid);
    2185                 :          4 :                         CU_ASSERT(nsid == 0);
    2186                 :            : 
    2187                 :            :                         /* Reset the active namespace list array */
    2188                 :          4 :                         g_active_ns_list[1] = 2;
    2189                 :            :                 }
    2190                 :            : 
    2191                 :         12 :                 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2192         [ +  + ]:         12 :                 if (minor <= 1) {
    2193                 :          8 :                         ctrlr.cdata.nn = 1531;
    2194                 :            :                 }
    2195                 :         12 :                 nvme_ctrlr_identify_active_ns(&ctrlr);
    2196                 :            : 
    2197                 :         12 :                 ns_id_count = 0;
    2198         [ +  + ]:       9198 :                 for (nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr);
    2199         [ +  + ]:      18378 :                      nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid)) {
    2200                 :      18372 :                         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true);
    2201                 :      18372 :                         ns_id_count++;
    2202                 :            :                 }
    2203                 :         12 :                 CU_ASSERT(ns_id_count == ctrlr.cdata.nn);
    2204                 :            : 
    2205                 :         12 :                 nvme_ctrlr_destruct(&ctrlr);
    2206                 :            :         }
    2207                 :            : 
    2208                 :          4 :         g_active_ns_list = NULL;
    2209                 :          4 :         g_active_ns_list_length = 0;
    2210                 :          4 : }
    2211                 :            : 
    2212                 :            : static void
    2213                 :          4 : test_nvme_ctrlr_test_active_ns_error_case(void)
    2214                 :            : {
    2215                 :            :         int rc;
    2216                 :          4 :         struct spdk_nvme_ctrlr  ctrlr = {.state = NVME_CTRLR_STATE_READY};
    2217                 :            : 
    2218                 :          4 :         ctrlr.page_size = 0x1000;
    2219                 :          4 :         ctrlr.vs.bits.mjr = 1;
    2220                 :          4 :         ctrlr.vs.bits.mnr = 2;
    2221                 :          4 :         ctrlr.vs.bits.ter = 0;
    2222                 :          4 :         ctrlr.cdata.nn = 2;
    2223                 :            : 
    2224                 :          4 :         set_status_code = SPDK_NVME_SC_INVALID_FIELD;
    2225                 :          4 :         rc = nvme_ctrlr_identify_active_ns(&ctrlr);
    2226                 :          4 :         CU_ASSERT(rc == -ENXIO);
    2227                 :          4 :         set_status_code = SPDK_NVME_SC_SUCCESS;
    2228                 :          4 : }
    2229                 :            : 
    2230                 :            : static void
    2231                 :          4 : test_nvme_ctrlr_init_delay(void)
    2232                 :            : {
    2233         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2234                 :            : 
    2235                 :          4 :         memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));
    2236                 :            : 
    2237                 :            :         /*
    2238                 :            :          * Initial state: CC.EN = 0, CSTS.RDY = 0
    2239                 :            :          * init() should set CC.EN = 1.
    2240                 :            :          */
    2241                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    2242                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    2243                 :            : 
    2244         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2245                 :            :         /* Test that the initialization delay works correctly.  We only
    2246                 :            :          * do the initialization delay on SSDs that require it, so
    2247                 :            :          * set that quirk here.
    2248                 :            :          */
    2249                 :          4 :         ctrlr.quirks = NVME_QUIRK_DELAY_BEFORE_INIT;
    2250                 :          4 :         ctrlr.cdata.nn = 1;
    2251                 :          4 :         ctrlr.page_size = 0x1000;
    2252                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_INIT_DELAY;
    2253                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2254                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    2255                 :          4 :         CU_ASSERT(ctrlr.sleep_timeout_tsc != 0);
    2256                 :            : 
    2257                 :            :         /* delay 1s, just return as sleep time isn't enough */
    2258                 :          4 :         spdk_delay_us(1 * spdk_get_ticks_hz());
    2259                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2260                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
    2261                 :          4 :         CU_ASSERT(ctrlr.sleep_timeout_tsc != 0);
    2262                 :            : 
    2263                 :            :         /* sleep timeout, start to initialize */
    2264                 :          4 :         spdk_delay_us(2 * spdk_get_ticks_hz());
    2265         [ +  + ]:         20 :         while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
    2266                 :         16 :                 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2267                 :            :         }
    2268                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2269                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    2270                 :            : 
    2271                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2272                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    2273                 :            : 
    2274                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2275                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
    2276                 :            : 
    2277                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2278                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
    2279                 :          4 :         CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
    2280                 :            : 
    2281                 :            :         /*
    2282                 :            :          * Transition to CSTS.RDY = 1.
    2283                 :            :          */
    2284                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 1;
    2285                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2286                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
    2287                 :            : 
    2288                 :            :         /*
    2289                 :            :          * Transition to READY.
    2290                 :            :          */
    2291         [ +  + ]:         64 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    2292                 :         60 :                 nvme_ctrlr_process_init(&ctrlr);
    2293                 :            :         }
    2294                 :            : 
    2295                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    2296                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2297                 :          4 : }
    2298                 :            : 
    2299                 :            : static void
    2300                 :          4 : test_spdk_nvme_ctrlr_set_trid(void)
    2301                 :            : {
    2302                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {{0}};
    2303                 :          4 :         struct spdk_nvme_transport_id new_trid = {{0}};
    2304                 :            : 
    2305                 :          4 :         CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
    2306                 :            : 
    2307                 :          4 :         ctrlr.is_failed = false;
    2308                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA;
    2309                 :          4 :         snprintf(ctrlr.trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1");
    2310                 :          4 :         snprintf(ctrlr.trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.8");
    2311                 :          4 :         snprintf(ctrlr.trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4420");
    2312                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EPERM);
    2313                 :            : 
    2314                 :          4 :         ctrlr.is_failed = true;
    2315                 :          4 :         new_trid.trtype = SPDK_NVME_TRANSPORT_TCP;
    2316                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL);
    2317                 :          4 :         CU_ASSERT(ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA);
    2318                 :            : 
    2319                 :          4 :         new_trid.trtype = SPDK_NVME_TRANSPORT_RDMA;
    2320                 :          4 :         snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode2");
    2321                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL);
    2322                 :          4 :         CU_ASSERT(strncmp(ctrlr.trid.subnqn, "nqn.2016-06.io.spdk:cnode1", SPDK_NVMF_NQN_MAX_LEN) == 0);
    2323                 :            : 
    2324                 :            : 
    2325                 :          4 :         snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1");
    2326                 :          4 :         snprintf(new_trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.9");
    2327                 :          4 :         snprintf(new_trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4421");
    2328                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == 0);
    2329                 :          4 :         CU_ASSERT(strncmp(ctrlr.trid.traddr, "192.168.100.9", SPDK_NVMF_TRADDR_MAX_LEN) == 0);
    2330                 :          4 :         CU_ASSERT(strncmp(ctrlr.trid.trsvcid, "4421", SPDK_NVMF_TRSVCID_MAX_LEN) == 0);
    2331                 :            : 
    2332                 :          4 :         CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
    2333                 :          4 : }
    2334                 :            : 
    2335                 :            : static void
    2336                 :          4 : test_nvme_ctrlr_init_set_nvmf_ioccsz(void)
    2337                 :            : {
    2338                 :          4 :         struct spdk_nvme_ctrlr_data cdata = {};
    2339         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2340                 :            :         /* equivalent of 4096 bytes */
    2341                 :          4 :         cdata.nvmf_specific.ioccsz = 260;
    2342                 :          4 :         cdata.nvmf_specific.icdoff = 1;
    2343                 :          4 :         g_cdata = &cdata;
    2344                 :            : 
    2345                 :            :         /* Check PCI trtype, */
    2346         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2347                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
    2348                 :            : 
    2349                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
    2350                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2351                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
    2352                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2353                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2354                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2355                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2356                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2357                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
    2358                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2359                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
    2360                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2361                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2362                 :            : 
    2363                 :          4 :         CU_ASSERT(ctrlr.ioccsz_bytes == 0);
    2364                 :          4 :         CU_ASSERT(ctrlr.icdoff == 0);
    2365                 :            : 
    2366                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2367                 :            : 
    2368                 :            :         /* Check RDMA trtype, */
    2369         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2370                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA;
    2371                 :            : 
    2372                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
    2373                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2374                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
    2375                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2376                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2377                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2378                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2379                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2380                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
    2381                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2382                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
    2383                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2384                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2385                 :            : 
    2386                 :          4 :         CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
    2387                 :          4 :         CU_ASSERT(ctrlr.icdoff == 1);
    2388                 :          4 :         ctrlr.ioccsz_bytes = 0;
    2389                 :          4 :         ctrlr.icdoff = 0;
    2390                 :            : 
    2391                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2392                 :            : 
    2393                 :            :         /* Check TCP trtype, */
    2394         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2395                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_TCP;
    2396                 :            : 
    2397                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
    2398                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2399                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
    2400                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2401                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2402                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2403                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2404                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2405                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
    2406                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2407                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
    2408                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2409                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2410                 :            : 
    2411                 :          4 :         CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
    2412                 :          4 :         CU_ASSERT(ctrlr.icdoff == 1);
    2413                 :          4 :         ctrlr.ioccsz_bytes = 0;
    2414                 :          4 :         ctrlr.icdoff = 0;
    2415                 :            : 
    2416                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2417                 :            : 
    2418                 :            :         /* Check FC trtype, */
    2419         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2420                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_FC;
    2421                 :            : 
    2422                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
    2423                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2424                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
    2425                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2426                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2427                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2428                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2429                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2430                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
    2431                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2432                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
    2433                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2434                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2435                 :            : 
    2436                 :          4 :         CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
    2437                 :          4 :         CU_ASSERT(ctrlr.icdoff == 1);
    2438                 :          4 :         ctrlr.ioccsz_bytes = 0;
    2439                 :          4 :         ctrlr.icdoff = 0;
    2440                 :            : 
    2441                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2442                 :            : 
    2443                 :            :         /* Check CUSTOM trtype, */
    2444         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2445                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM;
    2446                 :            : 
    2447                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
    2448                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2449                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
    2450                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2451                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2452                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2453                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2454                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2455                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
    2456                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2457                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
    2458                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2459                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2460                 :            : 
    2461                 :          4 :         CU_ASSERT(ctrlr.ioccsz_bytes == 0);
    2462                 :          4 :         CU_ASSERT(ctrlr.icdoff == 0);
    2463                 :            : 
    2464                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2465                 :            : 
    2466                 :            :         /* Check CUSTOM_FABRICS trtype, */
    2467         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2468                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM_FABRICS;
    2469                 :            : 
    2470                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
    2471                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2472                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
    2473                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2474                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2475                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2476                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2477                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2478                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
    2479                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2480                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
    2481                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2482                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2483                 :            : 
    2484                 :          4 :         CU_ASSERT(ctrlr.ioccsz_bytes == 4096);
    2485                 :          4 :         CU_ASSERT(ctrlr.icdoff == 1);
    2486                 :          4 :         ctrlr.ioccsz_bytes = 0;
    2487                 :          4 :         ctrlr.icdoff = 0;
    2488                 :            : 
    2489                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2490                 :            : 
    2491                 :          4 :         g_cdata = NULL;
    2492                 :          4 : }
    2493                 :            : 
    2494                 :            : static void
    2495                 :          4 : test_nvme_ctrlr_init_set_num_queues(void)
    2496                 :            : {
    2497         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2498                 :            : 
    2499         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2500                 :            : 
    2501                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
    2502                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2503                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
    2504                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2505                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2506                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2507                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2508                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    2509                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
    2510                 :            : 
    2511                 :          4 :         ctrlr.opts.num_io_queues = 64;
    2512                 :            :         /* Num queues is zero-based. So, use 31 to get 32 queues */
    2513                 :          4 :         fake_cpl.cdw0 = 31 + (31 << 16);
    2514                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_ACTIVE_NS */
    2515                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
    2516                 :          4 :         CU_ASSERT(ctrlr.opts.num_io_queues == 32);
    2517                 :          4 :         fake_cpl.cdw0 = 0;
    2518                 :            : 
    2519                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2520                 :          4 : }
    2521                 :            : 
    2522                 :            : static void
    2523                 :          4 : test_nvme_ctrlr_init_set_keep_alive_timeout(void)
    2524                 :            : {
    2525         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2526                 :            : 
    2527         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2528                 :            : 
    2529                 :          4 :         ctrlr.opts.keep_alive_timeout_ms = 60000;
    2530                 :          4 :         ctrlr.cdata.kas = 1;
    2531                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
    2532                 :          4 :         fake_cpl.cdw0 = 120000;
    2533                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */
    2534                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2535                 :          4 :         CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 120000);
    2536                 :          4 :         fake_cpl.cdw0 = 0;
    2537                 :            : 
    2538                 :            :         /* Target does not support Get Feature "Keep Alive Timer" */
    2539                 :          4 :         ctrlr.opts.keep_alive_timeout_ms = 60000;
    2540                 :          4 :         ctrlr.cdata.kas = 1;
    2541                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
    2542                 :          4 :         set_status_code = SPDK_NVME_SC_INVALID_FIELD;
    2543                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */
    2544                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
    2545                 :          4 :         CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 60000);
    2546                 :          4 :         set_status_code = SPDK_NVME_SC_SUCCESS;
    2547                 :            : 
    2548                 :            :         /* Target fails Get Feature "Keep Alive Timer" for another reason */
    2549                 :          4 :         ctrlr.opts.keep_alive_timeout_ms = 60000;
    2550                 :          4 :         ctrlr.cdata.kas = 1;
    2551                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
    2552                 :          4 :         set_status_code = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR;
    2553                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> ERROR */
    2554                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
    2555                 :          4 :         set_status_code = SPDK_NVME_SC_SUCCESS;
    2556                 :            : 
    2557                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2558                 :          4 : }
    2559                 :            : 
    2560                 :            : static void
    2561                 :          4 : test_alloc_io_qpair_fail(void)
    2562                 :            : {
    2563                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    2564                 :            :         struct spdk_nvme_qpair *q0;
    2565                 :            : 
    2566                 :          4 :         setup_qpairs(&ctrlr, 1);
    2567                 :            : 
    2568                 :            :         /* Modify the connect_qpair return code to inject a failure */
    2569                 :          4 :         g_connect_qpair_return_code = 1;
    2570                 :            : 
    2571                 :            :         /* Attempt to allocate a qpair, this should fail */
    2572                 :          4 :         q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0);
    2573         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(q0 == NULL);
    2574                 :            : 
    2575                 :            :         /* Verify that the qpair is removed from the lists */
    2576         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(TAILQ_EMPTY(&ctrlr.active_io_qpairs));
    2577                 :            : 
    2578                 :          4 :         g_connect_qpair_return_code = 0;
    2579                 :          4 :         cleanup_qpairs(&ctrlr);
    2580                 :          4 : }
    2581                 :            : 
    2582                 :            : static void
    2583                 :          4 : test_nvme_ctrlr_add_remove_process(void)
    2584                 :            : {
    2585                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    2586                 :          4 :         void *devhandle = (void *)0xDEADBEEF;
    2587                 :          4 :         struct spdk_nvme_ctrlr_process *proc = NULL;
    2588                 :            :         int rc;
    2589                 :            : 
    2590                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
    2591                 :          4 :         TAILQ_INIT(&ctrlr.active_procs);
    2592                 :            : 
    2593                 :          4 :         rc = nvme_ctrlr_add_process(&ctrlr, devhandle);
    2594                 :          4 :         CU_ASSERT(rc == 0);
    2595                 :          4 :         proc = TAILQ_FIRST(&ctrlr.active_procs);
    2596         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(proc != NULL);
    2597         [ -  + ]:          4 :         CU_ASSERT(proc->is_primary == true);
    2598                 :          4 :         CU_ASSERT(proc->pid == getpid());
    2599                 :          4 :         CU_ASSERT(proc->devhandle == (void *)0xDEADBEEF);
    2600                 :          4 :         CU_ASSERT(proc->ref == 0);
    2601                 :            : 
    2602                 :          4 :         nvme_ctrlr_remove_process(&ctrlr, proc);
    2603                 :          4 :         CU_ASSERT(TAILQ_EMPTY(&ctrlr.active_procs));
    2604                 :          4 : }
    2605                 :            : 
    2606                 :            : static void
    2607                 :          4 : test_nvme_ctrlr_set_arbitration_feature(void)
    2608                 :            : {
    2609                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    2610                 :            : 
    2611                 :          4 :         ctrlr.opts.arbitration_burst = 6;
    2612                 :          4 :         ctrlr.flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
    2613                 :          4 :         ctrlr.opts.low_priority_weight = 1;
    2614                 :          4 :         ctrlr.opts.medium_priority_weight = 2;
    2615                 :          4 :         ctrlr.opts.high_priority_weight = 3;
    2616                 :            :         /* g_ut_cdw11 used to record value command feature set. */
    2617                 :          4 :         g_ut_cdw11 = 0;
    2618                 :            : 
    2619                 :            :         /* arbitration_burst count available. */
    2620                 :          4 :         nvme_ctrlr_set_arbitration_feature(&ctrlr);
    2621                 :          4 :         CU_ASSERT((uint8_t)g_ut_cdw11 == 6);
    2622                 :          4 :         CU_ASSERT((uint8_t)(g_ut_cdw11 >> 8) == 1);
    2623                 :          4 :         CU_ASSERT((uint8_t)(g_ut_cdw11 >> 16) == 2);
    2624                 :          4 :         CU_ASSERT((uint8_t)(g_ut_cdw11 >> 24) == 3);
    2625                 :            : 
    2626                 :            :         /* arbitration_burst unavailable. */
    2627                 :          4 :         g_ut_cdw11 = 0;
    2628                 :          4 :         ctrlr.opts.arbitration_burst = 8;
    2629                 :            : 
    2630                 :          4 :         nvme_ctrlr_set_arbitration_feature(&ctrlr);
    2631                 :          4 :         CU_ASSERT(g_ut_cdw11 == 0);
    2632                 :          4 : }
    2633                 :            : 
    2634                 :            : static void
    2635                 :          4 : test_nvme_ctrlr_set_state(void)
    2636                 :            : {
    2637                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    2638                 :          4 :         MOCK_SET(spdk_get_ticks, 0);
    2639                 :            : 
    2640                 :          4 :         nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000);
    2641                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2642                 :          4 :         CU_ASSERT(ctrlr.state_timeout_tsc == 1000000);
    2643                 :            : 
    2644                 :          4 :         nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 0);
    2645                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2646                 :          4 :         CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
    2647                 :            : 
    2648                 :            :         /* Time out ticks causes integer overflow. */
    2649                 :          4 :         MOCK_SET(spdk_get_ticks, UINT64_MAX);
    2650                 :            : 
    2651                 :          4 :         nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000);
    2652                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
    2653                 :          4 :         CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
    2654                 :          4 :         MOCK_CLEAR(spdk_get_ticks);
    2655                 :          4 : }
    2656                 :            : 
    2657                 :            : static void
    2658                 :          4 : test_nvme_ctrlr_active_ns_list_v0(void)
    2659                 :            : {
    2660         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2661                 :            : 
    2662         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2663                 :            : 
    2664                 :          4 :         ctrlr.vs.bits.mjr = 1;
    2665                 :          4 :         ctrlr.vs.bits.mnr = 0;
    2666                 :          4 :         ctrlr.vs.bits.ter = 0;
    2667                 :          4 :         ctrlr.cdata.nn = 1024;
    2668                 :            : 
    2669                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
    2670         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2671         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2672                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
    2673                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
    2674                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
    2675                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1);
    2676                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024);
    2677                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
    2678                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0);
    2679                 :            : 
    2680                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2681                 :          4 : }
    2682                 :            : 
    2683                 :            : static void
    2684                 :          4 : test_nvme_ctrlr_active_ns_list_v2(void)
    2685                 :            : {
    2686                 :            :         uint32_t i;
    2687                 :          4 :         uint32_t active_ns_list[1024];
    2688         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2689                 :            : 
    2690         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2691                 :            : 
    2692                 :          4 :         ctrlr.vs.bits.mjr = 1;
    2693                 :          4 :         ctrlr.vs.bits.mnr = 2;
    2694                 :          4 :         ctrlr.vs.bits.ter = 0;
    2695                 :          4 :         ctrlr.cdata.nn = 4096;
    2696                 :            : 
    2697                 :          4 :         g_active_ns_list = active_ns_list;
    2698                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2699                 :            : 
    2700                 :            :         /* No active namespaces */
    2701                 :          4 :         memset(active_ns_list, 0, sizeof(active_ns_list));
    2702                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
    2703         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2704         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2705                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
    2706                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
    2707                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
    2708                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0);
    2709                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
    2710                 :            : 
    2711                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2712                 :            : 
    2713                 :            :         /* 1024 active namespaces - one full page */
    2714                 :          4 :         memset(active_ns_list, 0, sizeof(active_ns_list));
    2715         [ +  + ]:       4100 :         for (i = 0; i < 1024; ++i) {
    2716                 :       4096 :                 active_ns_list[i] = i + 1;
    2717                 :            :         }
    2718                 :            : 
    2719         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2720                 :            : 
    2721                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
    2722                 :          4 :         g_active_ns_list = active_ns_list;
    2723                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2724         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2725         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2726                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
    2727                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
    2728                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
    2729                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1);
    2730                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024);
    2731                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
    2732                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0);
    2733                 :            : 
    2734                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2735                 :            : 
    2736                 :            :         /* 1023 active namespaces - full page minus one  */
    2737                 :          4 :         memset(active_ns_list, 0, sizeof(active_ns_list));
    2738         [ +  + ]:       4096 :         for (i = 0; i < 1023; ++i) {
    2739                 :       4092 :                 active_ns_list[i] = i + 1;
    2740                 :            :         }
    2741                 :            : 
    2742         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2743                 :            : 
    2744                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
    2745         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2746         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
    2747                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1));
    2748                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1023));
    2749                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024));
    2750                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025));
    2751                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1);
    2752                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 0);
    2753                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0);
    2754                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0);
    2755                 :            : 
    2756                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2757                 :            : 
    2758                 :          4 :         g_active_ns_list = NULL;
    2759                 :          4 :         g_active_ns_list_length = 0;
    2760                 :          4 : }
    2761                 :            : 
    2762                 :            : static void
    2763                 :          4 : test_nvme_ctrlr_ns_mgmt(void)
    2764                 :            : {
    2765         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2766                 :          4 :         uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
    2767                 :          4 :         uint32_t active_ns_list2[] = { 1, 2, 3, 100, 1024 };
    2768                 :          4 :         struct spdk_nvme_ns_data nsdata = {};
    2769                 :          4 :         struct spdk_nvme_ctrlr_list ctrlr_list = {};
    2770                 :            :         uint32_t nsid;
    2771                 :            : 
    2772         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2773                 :            : 
    2774                 :          4 :         ctrlr.vs.bits.mjr = 1;
    2775                 :          4 :         ctrlr.vs.bits.mnr = 2;
    2776                 :          4 :         ctrlr.vs.bits.ter = 0;
    2777                 :          4 :         ctrlr.cdata.nn = 4096;
    2778                 :            : 
    2779                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
    2780                 :          4 :         g_active_ns_list = active_ns_list;
    2781                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2782         [ +  + ]:         40 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    2783         [ -  + ]:         36 :                 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2784                 :            :         }
    2785                 :            : 
    2786                 :          4 :         fake_cpl.cdw0 = 3;
    2787                 :          4 :         nsid = spdk_nvme_ctrlr_create_ns(&ctrlr, &nsdata);
    2788                 :          4 :         fake_cpl.cdw0 = 0;
    2789                 :          4 :         CU_ASSERT(nsid == 3);
    2790                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
    2791                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
    2792                 :            : 
    2793                 :          4 :         g_active_ns_list = active_ns_list2;
    2794                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2);
    2795                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_attach_ns(&ctrlr, 3, &ctrlr_list) == 0);
    2796                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
    2797                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
    2798                 :            : 
    2799                 :          4 :         g_active_ns_list = active_ns_list;
    2800                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2801                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_detach_ns(&ctrlr, 3, &ctrlr_list) == 0);
    2802                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
    2803                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
    2804                 :            : 
    2805                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_delete_ns(&ctrlr, 3) == 0);
    2806                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3));
    2807                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL);
    2808                 :          4 :         g_active_ns_list = NULL;
    2809                 :          4 :         g_active_ns_list_length = 0;
    2810                 :            : 
    2811                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2812                 :          4 : }
    2813                 :            : 
    2814                 :            : static void
    2815                 :          4 : check_en_set_rdy(void)
    2816                 :            : {
    2817         [ +  - ]:          4 :         if (g_ut_nvme_regs.cc.bits.en == 1) {
    2818                 :          4 :                 g_ut_nvme_regs.csts.bits.rdy = 1;
    2819                 :            :         }
    2820                 :          4 : }
    2821                 :            : 
    2822                 :            : static void
    2823                 :          4 : test_nvme_ctrlr_reset(void)
    2824                 :            : {
    2825         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2826                 :          4 :         struct spdk_nvme_ctrlr_data cdata = { .nn = 4096 };
    2827                 :          4 :         uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
    2828                 :          4 :         uint32_t active_ns_list2[] = { 1, 100, 1024 };
    2829                 :            : 
    2830         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2831                 :            : 
    2832                 :          4 :         g_ut_nvme_regs.vs.bits.mjr = 1;
    2833                 :          4 :         g_ut_nvme_regs.vs.bits.mnr = 2;
    2834                 :          4 :         g_ut_nvme_regs.vs.bits.ter = 0;
    2835                 :          4 :         nvme_ctrlr_get_vs(&ctrlr, &ctrlr.vs);
    2836                 :          4 :         ctrlr.cdata.nn = 2048;
    2837                 :            : 
    2838                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
    2839                 :          4 :         g_active_ns_list = active_ns_list;
    2840                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2841         [ +  + ]:         40 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    2842         [ -  + ]:         36 :                 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2843                 :            :         }
    2844                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 2048);
    2845                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL);
    2846                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2));
    2847                 :            : 
    2848                 :            :         /* Reset controller with changed number of namespaces */
    2849                 :          4 :         g_cdata = &cdata;
    2850                 :          4 :         g_active_ns_list = active_ns_list2;
    2851                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2);
    2852         [ -  + ]:          4 :         STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq);
    2853                 :          4 :         g_ut_nvme_regs.cc.raw = 0;
    2854                 :          4 :         g_ut_nvme_regs.csts.raw = 0;
    2855                 :          4 :         g_set_reg_cb = check_en_set_rdy;
    2856                 :          4 :         g_wait_for_completion_return_val = -ENXIO;
    2857                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_reset(&ctrlr) == 0);
    2858                 :          4 :         g_set_reg_cb = NULL;
    2859                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
    2860                 :          4 :         g_cdata = NULL;
    2861                 :          4 :         g_active_ns_list = NULL;
    2862                 :          4 :         g_active_ns_list_length = 0;
    2863                 :            : 
    2864                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 4096);
    2865                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL);
    2866                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2));
    2867                 :            : 
    2868                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    2869                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2870                 :            : 
    2871                 :          4 :         g_wait_for_completion_return_val = 0;
    2872                 :          4 : }
    2873                 :            : 
    2874                 :            : static uint32_t g_aer_cb_counter;
    2875                 :            : 
    2876                 :            : static void
    2877                 :         12 : aer_cb(void *aer_cb_arg, const struct spdk_nvme_cpl *cpl)
    2878                 :            : {
    2879                 :         12 :         g_aer_cb_counter++;
    2880                 :         12 : }
    2881                 :            : 
    2882                 :            : static void
    2883                 :          4 : test_nvme_ctrlr_aer_callback(void)
    2884                 :            : {
    2885         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2886                 :          4 :         uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
    2887                 :          4 :         union spdk_nvme_async_event_completion  aer_event = {
    2888                 :            :                 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE,
    2889                 :            :                 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED
    2890                 :            :         };
    2891                 :          4 :         struct spdk_nvme_cpl aer_cpl = {
    2892                 :            :                 .status.sct = SPDK_NVME_SCT_GENERIC,
    2893                 :            :                 .status.sc = SPDK_NVME_SC_SUCCESS,
    2894                 :          4 :                 .cdw0 = aer_event.raw
    2895                 :            :         };
    2896                 :            : 
    2897         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2898                 :            : 
    2899                 :          4 :         ctrlr.vs.bits.mjr = 1;
    2900                 :          4 :         ctrlr.vs.bits.mnr = 2;
    2901                 :          4 :         ctrlr.vs.bits.ter = 0;
    2902                 :          4 :         ctrlr.cdata.nn = 4096;
    2903                 :            : 
    2904                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
    2905                 :          4 :         g_active_ns_list = active_ns_list;
    2906                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2907         [ +  + ]:         56 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    2908         [ -  + ]:         52 :                 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2909                 :            :         }
    2910                 :            : 
    2911                 :          4 :         CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0);
    2912                 :          4 :         spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL);
    2913                 :            : 
    2914                 :            :         /* Async event */
    2915                 :          4 :         g_aer_cb_counter = 0;
    2916                 :          4 :         nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
    2917                 :          4 :         nvme_ctrlr_complete_queued_async_events(&ctrlr);
    2918                 :          4 :         CU_ASSERT(g_aer_cb_counter == 1);
    2919                 :          4 :         g_active_ns_list = NULL;
    2920                 :          4 :         g_active_ns_list_length = 0;
    2921                 :            : 
    2922                 :          4 :         nvme_ctrlr_free_processes(&ctrlr);
    2923                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2924                 :          4 : }
    2925                 :            : 
    2926                 :            : static void
    2927                 :          4 : test_nvme_ctrlr_ns_attr_changed(void)
    2928                 :            : {
    2929         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    2930                 :          4 :         uint32_t active_ns_list[] = { 1, 2, 100, 1024 };
    2931                 :          4 :         uint32_t active_ns_list2[] = { 1, 2, 1024 };
    2932                 :          4 :         uint32_t active_ns_list3[] = { 1, 2, 101, 1024 };
    2933                 :          4 :         union spdk_nvme_async_event_completion  aer_event = {
    2934                 :            :                 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE,
    2935                 :            :                 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED
    2936                 :            :         };
    2937                 :          4 :         struct spdk_nvme_cpl aer_cpl = {
    2938                 :            :                 .status.sct = SPDK_NVME_SCT_GENERIC,
    2939                 :            :                 .status.sc = SPDK_NVME_SC_SUCCESS,
    2940                 :          4 :                 .cdw0 = aer_event.raw
    2941                 :            :         };
    2942                 :            : 
    2943         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    2944                 :            : 
    2945                 :          4 :         ctrlr.vs.bits.mjr = 1;
    2946                 :          4 :         ctrlr.vs.bits.mnr = 3;
    2947                 :          4 :         ctrlr.vs.bits.ter = 0;
    2948                 :          4 :         ctrlr.cap.bits.css |= SPDK_NVME_CAP_CSS_IOCS;
    2949                 :          4 :         ctrlr.cdata.nn = 4096;
    2950                 :            : 
    2951                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
    2952                 :          4 :         g_active_ns_list = active_ns_list;
    2953                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list);
    2954                 :            : 
    2955         [ +  + ]:         56 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    2956         [ -  + ]:         52 :                 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    2957                 :            :         }
    2958                 :            : 
    2959                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100));
    2960                 :            : 
    2961                 :          4 :         CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0);
    2962                 :          4 :         spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL);
    2963                 :            : 
    2964                 :            :         /* Remove NS 100 */
    2965                 :          4 :         g_aer_cb_counter = 0;
    2966                 :          4 :         g_active_ns_list = active_ns_list2;
    2967                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2);
    2968                 :          4 :         nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
    2969                 :          4 :         nvme_ctrlr_complete_queued_async_events(&ctrlr);
    2970                 :          4 :         CU_ASSERT(g_aer_cb_counter == 1);
    2971                 :          4 :         CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100));
    2972                 :            : 
    2973                 :            :         /* Add NS 101 */
    2974                 :          4 :         g_active_ns_list = active_ns_list3;
    2975                 :          4 :         g_active_ns_list_length = SPDK_COUNTOF(active_ns_list3);
    2976                 :          4 :         nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
    2977                 :          4 :         nvme_ctrlr_complete_queued_async_events(&ctrlr);
    2978                 :          4 :         CU_ASSERT(g_aer_cb_counter == 2);
    2979                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 101));
    2980                 :            : 
    2981                 :          4 :         g_active_ns_list = NULL;
    2982                 :          4 :         g_active_ns_list_length = 0;
    2983                 :          4 :         nvme_ctrlr_free_processes(&ctrlr);
    2984                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    2985                 :          4 : }
    2986                 :            : 
    2987                 :            : static void
    2988                 :          4 : test_nvme_ctrlr_identify_namespaces_iocs_specific_next(void)
    2989                 :            : {
    2990                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    2991                 :            :         uint32_t prev_nsid;
    2992                 :          4 :         struct spdk_nvme_ns ns[5] = {};
    2993                 :          4 :         struct spdk_nvme_ctrlr ns_ctrlr[5] = {};
    2994                 :          4 :         int rc = 0;
    2995                 :            :         int i;
    2996                 :            : 
    2997                 :          4 :         RB_INIT(&ctrlr.ns);
    2998         [ +  + ]:         24 :         for (i = 0; i < 5; i++) {
    2999                 :         20 :                 ns[i].id = i + 1;
    3000                 :         20 :                 ns[i].active = true;
    3001                 :            :         }
    3002                 :            : 
    3003         [ -  + ]:          4 :         CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
    3004                 :            : 
    3005                 :          4 :         ctrlr.cdata.nn = 5;
    3006                 :            :         /* case 1: No first/next active NS, move on to the next state, expect: pass */
    3007                 :          4 :         prev_nsid = 0;
    3008                 :          4 :         ctrlr.active_ns_count = 0;
    3009                 :          4 :         ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
    3010                 :          4 :         rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
    3011                 :          4 :         CU_ASSERT(rc == 0);
    3012                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES);
    3013                 :          4 :         CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
    3014                 :            : 
    3015                 :            :         /* case 2: move on to the next active NS, and no namespace with (supported) iocs specific data found , expect: pass */
    3016                 :            :         memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
    3017                 :            :         memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc));
    3018                 :          4 :         prev_nsid = 1;
    3019         [ +  + ]:         24 :         for (i = 0; i < 5; i++) {
    3020                 :         20 :                 RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]);
    3021                 :            :         }
    3022                 :          4 :         ctrlr.active_ns_count = 5;
    3023                 :          4 :         ns[1].csi = SPDK_NVME_CSI_NVM;
    3024                 :          4 :         ns[1].id = 2;
    3025                 :          4 :         rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
    3026                 :          4 :         CU_ASSERT(rc == 0);
    3027                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES);
    3028                 :          4 :         CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
    3029                 :            : 
    3030                 :            :         /* case 3: ns.csi is SPDK_NVME_CSI_ZNS, do not loop, expect: pass */
    3031                 :            :         memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
    3032                 :            :         memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc));
    3033                 :          4 :         ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
    3034                 :          4 :         prev_nsid = 0;
    3035                 :          4 :         ctrlr.active_ns_count = 5;
    3036                 :            : 
    3037         [ +  + ]:         24 :         for (int i = 0; i < 5; i++) {
    3038                 :         20 :                 ns[i].csi = SPDK_NVME_CSI_NVM;
    3039                 :         20 :                 ns[i].id = i + 1;
    3040                 :         20 :                 ns[i].ctrlr = &ns_ctrlr[i];
    3041                 :            :         }
    3042                 :          4 :         ns[4].csi = SPDK_NVME_CSI_ZNS;
    3043                 :          4 :         ns_ctrlr[4].opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
    3044                 :            : 
    3045                 :          4 :         rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
    3046                 :          4 :         CU_ASSERT(rc == 0);
    3047                 :          4 :         CU_ASSERT(ctrlr.state == 0);
    3048                 :          4 :         CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
    3049                 :          4 :         CU_ASSERT(ns_ctrlr[4].state == NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC);
    3050                 :          4 :         CU_ASSERT(ns_ctrlr[4].state_timeout_tsc == NVME_TIMEOUT_INFINITE);
    3051                 :            : 
    3052         [ +  + ]:         24 :         for (int i = 0; i < 5; i++) {
    3053                 :         20 :                 nvme_ns_free_zns_specific_data(&ns[i]);
    3054                 :            :         }
    3055                 :            : 
    3056                 :            :         /* case 4: nvme_ctrlr_identify_ns_iocs_specific_async return 1, expect: false */
    3057                 :            :         memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
    3058                 :            :         memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc));
    3059                 :          4 :         prev_nsid = 1;
    3060                 :          4 :         ctrlr.active_ns_count = 5;
    3061                 :          4 :         ns[1].csi = SPDK_NVME_CSI_ZNS;
    3062                 :          4 :         g_fail_next_identify = true;
    3063                 :          4 :         rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid);
    3064                 :          4 :         CU_ASSERT(rc == 1);
    3065                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
    3066                 :          4 :         CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE);
    3067                 :            : 
    3068         [ -  + ]:          4 :         CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
    3069                 :          4 : }
    3070                 :            : 
    3071                 :            : static void
    3072                 :          4 : test_nvme_ctrlr_set_supported_log_pages(void)
    3073                 :            : {
    3074                 :            :         int rc;
    3075                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    3076                 :            : 
    3077                 :            :         /* ana supported */
    3078         [ -  + ]:          4 :         memset(&ctrlr, 0, sizeof(ctrlr));
    3079                 :          4 :         ctrlr.cdata.cmic.ana_reporting = true;
    3080                 :          4 :         ctrlr.cdata.lpa.celp = 1;
    3081                 :          4 :         ctrlr.cdata.nanagrpid = 1;
    3082                 :          4 :         ctrlr.active_ns_count = 1;
    3083                 :            : 
    3084                 :          4 :         rc = nvme_ctrlr_set_supported_log_pages(&ctrlr);
    3085                 :          4 :         CU_ASSERT(rc == 0);
    3086         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true);
    3087         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true);
    3088         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true);
    3089                 :          4 :         CU_ASSERT(ctrlr.ana_log_page_size == sizeof(struct spdk_nvme_ana_page) +
    3090                 :            :                   sizeof(struct spdk_nvme_ana_group_descriptor) * 1 + sizeof(uint32_t) * 1);
    3091         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] == true);
    3092                 :          4 :         free(ctrlr.ana_log_page);
    3093                 :          4 :         free(ctrlr.copied_ana_desc);
    3094                 :          4 : }
    3095                 :            : 
    3096                 :            : static void
    3097                 :          4 : test_nvme_ctrlr_set_intel_supported_log_pages(void)
    3098                 :            : {
    3099         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    3100                 :            : 
    3101         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    3102                 :            : 
    3103                 :          4 :         ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE;
    3104                 :          4 :         ctrlr.cdata.vid = SPDK_PCI_VID_INTEL;
    3105                 :          4 :         ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
    3106                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES;
    3107                 :            : 
    3108                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    3109                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES);
    3110                 :            : 
    3111                 :          4 :         set_status_code = SPDK_NVME_SC_SUCCESS;
    3112                 :          4 :         CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
    3113                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES);
    3114                 :            : 
    3115         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true);
    3116         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true);
    3117         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true);
    3118         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] == true);
    3119         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] == true);
    3120         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] == true);
    3121         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_SMART] == true);
    3122         [ -  + ]:          4 :         CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] == true);
    3123                 :            : 
    3124                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    3125                 :          4 : }
    3126                 :            : 
    3127                 :            : #define UT_ANA_DESC_SIZE        (sizeof(struct spdk_nvme_ana_group_descriptor) +        \
    3128                 :            :                                  sizeof(uint32_t))
    3129                 :            : static void
    3130                 :          4 : test_nvme_ctrlr_parse_ana_log_page(void)
    3131                 :            : {
    3132                 :            :         int rc, i;
    3133                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    3134                 :          4 :         struct spdk_nvme_ns ns[3] = {};
    3135                 :          4 :         struct spdk_nvme_ana_page ana_hdr;
    3136                 :          4 :         char _ana_desc[UT_ANA_DESC_SIZE];
    3137                 :            :         struct spdk_nvme_ana_group_descriptor *ana_desc;
    3138                 :            :         uint32_t offset;
    3139                 :            : 
    3140                 :          4 :         RB_INIT(&ctrlr.ns);
    3141         [ +  + ]:         16 :         for (i = 0; i < 3; i++) {
    3142                 :         12 :                 ns[i].id = i + 1;
    3143                 :         12 :                 ns[i].active = true;
    3144                 :         12 :                 RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]);
    3145                 :            :         }
    3146                 :            : 
    3147                 :          4 :         CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0);
    3148                 :            : 
    3149                 :          4 :         ctrlr.cdata.nn = 3;
    3150                 :          4 :         ctrlr.cdata.nanagrpid = 3;
    3151                 :          4 :         ctrlr.active_ns_count = 3;
    3152                 :            : 
    3153                 :          4 :         rc = nvme_ctrlr_update_ana_log_page(&ctrlr);
    3154                 :          4 :         CU_ASSERT(rc == 0);
    3155                 :          4 :         CU_ASSERT(ctrlr.ana_log_page != NULL);
    3156                 :          4 :         CU_ASSERT(ctrlr.copied_ana_desc != NULL);
    3157                 :            : 
    3158                 :            :         /*
    3159                 :            :          * Create ANA log page data - There are three ANA groups.
    3160                 :            :          * Each ANA group has a namespace and has a different ANA state.
    3161                 :            :          */
    3162                 :          4 :         memset(&ana_hdr, 0, sizeof(ana_hdr));
    3163                 :          4 :         ana_hdr.num_ana_group_desc = 3;
    3164                 :            : 
    3165         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(sizeof(ana_hdr) <= ctrlr.ana_log_page_size);
    3166                 :          4 :         memcpy((char *)ctrlr.ana_log_page, (char *)&ana_hdr, sizeof(ana_hdr));
    3167                 :          4 :         offset = sizeof(ana_hdr);
    3168                 :            : 
    3169                 :          4 :         ana_desc = (struct spdk_nvme_ana_group_descriptor *)_ana_desc;
    3170         [ -  + ]:          4 :         memset(ana_desc, 0, UT_ANA_DESC_SIZE);
    3171                 :          4 :         ana_desc->num_of_nsid = 1;
    3172                 :            : 
    3173                 :          4 :         ana_desc->ana_group_id = 1;
    3174                 :          4 :         ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE;
    3175                 :          4 :         ana_desc->nsid[0] = 3;
    3176                 :            : 
    3177         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size);
    3178   [ -  +  -  + ]:          4 :         memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE);
    3179                 :          4 :         offset += UT_ANA_DESC_SIZE;
    3180                 :            : 
    3181                 :          4 :         ana_desc->ana_group_id = 2;
    3182                 :          4 :         ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE;
    3183                 :          4 :         ana_desc->nsid[0] = 2;
    3184                 :            : 
    3185         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size);
    3186   [ -  +  -  + ]:          4 :         memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE);
    3187                 :          4 :         offset += UT_ANA_DESC_SIZE;
    3188                 :            : 
    3189                 :          4 :         ana_desc->ana_group_id = 3;
    3190                 :          4 :         ana_desc->ana_state = SPDK_NVME_ANA_INACCESSIBLE_STATE;
    3191                 :          4 :         ana_desc->nsid[0] = 1;
    3192                 :            : 
    3193         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size);
    3194   [ -  +  -  + ]:          4 :         memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE);
    3195                 :            : 
    3196                 :            :         /* Parse the created ANA log page data, and update ANA states. */
    3197                 :          4 :         rc = nvme_ctrlr_parse_ana_log_page(&ctrlr, nvme_ctrlr_update_ns_ana_states,
    3198                 :            :                                            &ctrlr);
    3199                 :          4 :         CU_ASSERT(rc == 0);
    3200                 :          4 :         CU_ASSERT(ns[0].ana_group_id == 3);
    3201                 :          4 :         CU_ASSERT(ns[0].ana_state == SPDK_NVME_ANA_INACCESSIBLE_STATE);
    3202                 :          4 :         CU_ASSERT(ns[1].ana_group_id == 2);
    3203                 :          4 :         CU_ASSERT(ns[1].ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE);
    3204                 :          4 :         CU_ASSERT(ns[2].ana_group_id == 1);
    3205                 :          4 :         CU_ASSERT(ns[2].ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE);
    3206                 :            : 
    3207                 :          4 :         CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0);
    3208                 :            : 
    3209                 :          4 :         free(ctrlr.ana_log_page);
    3210                 :          4 :         free(ctrlr.copied_ana_desc);
    3211                 :          4 : }
    3212                 :            : 
    3213                 :            : static void
    3214                 :          4 : test_nvme_ctrlr_ana_resize(void)
    3215                 :            : {
    3216         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    3217                 :          4 :         uint32_t active_ns_list[] = { 1, 2, 3, 4 };
    3218                 :          4 :         struct spdk_nvme_ana_page ana_hdr = {
    3219                 :            :                 .change_count = 0,
    3220                 :            :                 .num_ana_group_desc = 1
    3221                 :            :         };
    3222                 :          4 :         uint8_t ana_desc_buf[sizeof(struct spdk_nvme_ana_group_descriptor) + 4 * sizeof(uint32_t)] = {};
    3223                 :          4 :         struct spdk_nvme_ana_group_descriptor *ana_desc =
    3224                 :            :                 (struct spdk_nvme_ana_group_descriptor *)ana_desc_buf;
    3225                 :            :         struct spdk_nvme_ns *ns;
    3226                 :          4 :         union spdk_nvme_async_event_completion aer_event = {
    3227                 :            :                 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE,
    3228                 :            :                 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED
    3229                 :            :         };
    3230                 :          4 :         struct spdk_nvme_cpl aer_cpl = {
    3231                 :            :                 .status.sct = SPDK_NVME_SCT_GENERIC,
    3232                 :            :                 .status.sc = SPDK_NVME_SC_SUCCESS,
    3233                 :          4 :                 .cdw0 = aer_event.raw
    3234                 :            :         };
    3235                 :            :         uint32_t i;
    3236                 :            : 
    3237         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    3238         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_add_process(&ctrlr, NULL) == 0);
    3239                 :            : 
    3240                 :          4 :         ctrlr.vs.bits.mjr = 1;
    3241                 :          4 :         ctrlr.vs.bits.mnr = 4;
    3242                 :          4 :         ctrlr.vs.bits.ter = 0;
    3243                 :          4 :         ctrlr.cdata.nn = 4096;
    3244                 :          4 :         ctrlr.cdata.cmic.ana_reporting = true;
    3245                 :          4 :         ctrlr.cdata.nanagrpid = 1;
    3246                 :            : 
    3247                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
    3248                 :            :         /* Start with 2 active namespaces */
    3249                 :          4 :         g_active_ns_list = active_ns_list;
    3250                 :          4 :         g_active_ns_list_length = 2;
    3251                 :          4 :         g_ana_hdr = &ana_hdr;
    3252                 :          4 :         g_ana_descs = &ana_desc;
    3253                 :          4 :         ana_desc->ana_group_id = 1;
    3254                 :          4 :         ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE;
    3255                 :          4 :         ana_desc->num_of_nsid = 2;
    3256         [ +  + ]:         12 :         for (i = 0; i < ana_desc->num_of_nsid; ++i) {
    3257                 :          8 :                 ana_desc->nsid[i] = i + 1;
    3258                 :            :         }
    3259                 :            : 
    3260                 :            :         /* Bring controller to ready state */
    3261         [ +  + ]:         56 :         while (ctrlr.state != NVME_CTRLR_STATE_READY) {
    3262         [ -  + ]:         52 :                 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    3263                 :            :         }
    3264                 :            : 
    3265         [ +  + ]:         12 :         for (i = 0; i < ana_desc->num_of_nsid; ++i) {
    3266                 :          8 :                 ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1);
    3267                 :          8 :                 CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE);
    3268                 :            :         }
    3269                 :            : 
    3270                 :            :         /* Add more namespaces */
    3271                 :          4 :         g_active_ns_list_length = 4;
    3272                 :          4 :         nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
    3273                 :          4 :         nvme_ctrlr_complete_queued_async_events(&ctrlr);
    3274                 :            : 
    3275                 :            :         /* Update ANA log with new namespaces */
    3276                 :          4 :         ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE;
    3277                 :          4 :         ana_desc->num_of_nsid = 4;
    3278         [ +  + ]:         20 :         for (i = 0; i < ana_desc->num_of_nsid; ++i) {
    3279                 :         16 :                 ana_desc->nsid[i] = i + 1;
    3280                 :            :         }
    3281                 :          4 :         aer_event.bits.async_event_info = SPDK_NVME_ASYNC_EVENT_ANA_CHANGE;
    3282                 :          4 :         aer_cpl.cdw0 = aer_event.raw;
    3283                 :          4 :         nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl);
    3284                 :          4 :         nvme_ctrlr_complete_queued_async_events(&ctrlr);
    3285                 :            : 
    3286         [ +  + ]:         20 :         for (i = 0; i < ana_desc->num_of_nsid; ++i) {
    3287                 :         16 :                 ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1);
    3288                 :         16 :                 CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE);
    3289                 :            :         }
    3290                 :            : 
    3291                 :          4 :         g_active_ns_list = NULL;
    3292                 :          4 :         g_active_ns_list_length = 0;
    3293                 :          4 :         g_ana_hdr = NULL;
    3294                 :          4 :         g_ana_descs = NULL;
    3295                 :          4 :         nvme_ctrlr_free_processes(&ctrlr);
    3296                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    3297                 :          4 : }
    3298                 :            : 
    3299                 :            : static void
    3300                 :          4 : test_nvme_ctrlr_get_memory_domains(void)
    3301                 :            : {
    3302                 :          4 :         struct spdk_nvme_ctrlr ctrlr = {};
    3303                 :            : 
    3304                 :          4 :         MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 1);
    3305                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 1);
    3306                 :            : 
    3307                 :          4 :         MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 0);
    3308                 :          4 :         CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 0);
    3309                 :            : 
    3310                 :          4 :         MOCK_CLEAR(nvme_transport_ctrlr_get_memory_domains);
    3311                 :          4 : }
    3312                 :            : 
    3313                 :            : static void
    3314                 :          4 : test_nvme_transport_ctrlr_ready(void)
    3315                 :            : {
    3316         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    3317                 :            : 
    3318                 :            :         /* Transport init succeeded */
    3319                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
    3320         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    3321                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
    3322                 :            : 
    3323                 :            :         /* Transport init failed */
    3324                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
    3325                 :          4 :         MOCK_SET(nvme_transport_ctrlr_ready, -1);
    3326         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == -1);
    3327                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
    3328                 :          4 :         MOCK_CLEAR(nvme_transport_ctrlr_ready);
    3329                 :          4 : }
    3330                 :            : 
    3331                 :            : static void
    3332                 :          4 : test_nvme_ctrlr_disable(void)
    3333                 :            : {
    3334         [ +  - ]:          4 :         DECLARE_AND_CONSTRUCT_CTRLR();
    3335                 :            :         int rc;
    3336                 :            : 
    3337         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);
    3338                 :            : 
    3339                 :          4 :         ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
    3340         [ -  + ]:          4 :         SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0);
    3341                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
    3342                 :            : 
    3343                 :            :         /* Start a Controller Level Reset. */
    3344                 :          4 :         ctrlr.is_disconnecting = true;
    3345                 :          4 :         nvme_ctrlr_disable(&ctrlr);
    3346                 :            : 
    3347                 :          4 :         g_ut_nvme_regs.cc.bits.en = 0;
    3348                 :            : 
    3349                 :          4 :         rc = nvme_ctrlr_disable_poll(&ctrlr);
    3350                 :          4 :         CU_ASSERT(rc == -EAGAIN);
    3351                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
    3352                 :            : 
    3353                 :          4 :         g_ut_nvme_regs.csts.bits.rdy = 0;
    3354                 :            : 
    3355                 :          4 :         rc = nvme_ctrlr_disable_poll(&ctrlr);
    3356                 :          4 :         CU_ASSERT(rc == 0);
    3357                 :          4 :         CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
    3358                 :            : 
    3359                 :          4 :         g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
    3360                 :          4 :         nvme_ctrlr_destruct(&ctrlr);
    3361                 :          4 : }
    3362                 :            : 
    3363                 :            : int
    3364                 :          4 : main(int argc, char **argv)
    3365                 :            : {
    3366                 :          4 :         CU_pSuite       suite = NULL;
    3367                 :            :         unsigned int    num_failures;
    3368                 :            : 
    3369                 :          4 :         CU_initialize_registry();
    3370                 :            : 
    3371                 :          4 :         suite = CU_add_suite("nvme_ctrlr", NULL, NULL);
    3372                 :            : 
    3373                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_0);
    3374                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_1);
    3375                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0);
    3376                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_1);
    3377                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_rr);
    3378                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr);
    3379                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_vs);
    3380                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_delay);
    3381                 :          4 :         CU_ADD_TEST(suite, test_alloc_io_qpair_rr_1);
    3382                 :          4 :         CU_ADD_TEST(suite, test_ctrlr_get_default_ctrlr_opts);
    3383                 :          4 :         CU_ADD_TEST(suite, test_ctrlr_get_default_io_qpair_opts);
    3384                 :          4 :         CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_1);
    3385                 :          4 :         CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_2);
    3386                 :          4 :         CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_update_firmware);
    3387                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_fail);
    3388                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_construct_intel_support_log_page_list);
    3389                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_features);
    3390                 :          4 :         CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_doorbell_buffer_config);
    3391                 :            : #if 0 /* TODO: move to PCIe-specific unit test */
    3392                 :            :         CU_ADD_TEST(suite, test_nvme_ctrlr_alloc_cmb);
    3393                 :            : #endif
    3394                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns);
    3395                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns_error_case);
    3396                 :          4 :         CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_reconnect_io_qpair);
    3397                 :          4 :         CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_set_trid);
    3398                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_nvmf_ioccsz);
    3399                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_num_queues);
    3400                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_keep_alive_timeout);
    3401                 :          4 :         CU_ADD_TEST(suite, test_alloc_io_qpair_fail);
    3402                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_add_remove_process);
    3403                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_set_arbitration_feature);
    3404                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_set_state);
    3405                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v0);
    3406                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v2);
    3407                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_ns_mgmt);
    3408                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_reset);
    3409                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_aer_callback);
    3410                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_ns_attr_changed);
    3411                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_identify_namespaces_iocs_specific_next);
    3412                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_log_pages);
    3413                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_set_intel_supported_log_pages);
    3414                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_parse_ana_log_page);
    3415                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_ana_resize);
    3416                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_get_memory_domains);
    3417                 :          4 :         CU_ADD_TEST(suite, test_nvme_transport_ctrlr_ready);
    3418                 :          4 :         CU_ADD_TEST(suite, test_nvme_ctrlr_disable);
    3419                 :            : 
    3420                 :          4 :         num_failures = spdk_ut_run_tests(argc, argv, NULL);
    3421                 :          4 :         CU_cleanup_registry();
    3422                 :          4 :         return num_failures;
    3423                 :            : }

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